Lines Matching refs:Rd
349 void ArmToMipsAssembler::protectConditionalOperands(int Rd) in protectConditionalOperands() argument
351 if (Rd == cond.r1) { in protectConditionalOperands()
355 if (cond.type == CMP_COND && Rd == cond.r2) { in protectConditionalOperands()
412 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
418 protectConditionalOperands(Rd); in dataProcessing()
429 mMips->AND(Rd, Rn, src); in dataProcessing()
431 mMips->ANDI(Rd, Rn, src); in dataProcessing()
438 mMips->ADDU(Rd, Rn, src); in dataProcessing()
440 mMips->ADDIU(Rd, Rn, src); in dataProcessing()
447 mMips->SUBU(Rd, Rn, src); in dataProcessing()
449 mMips->SUBIU(Rd, Rn, src); in dataProcessing()
455 mMips->XOR(Rd, Rn, src); in dataProcessing()
457 mMips->XORI(Rd, Rn, src); in dataProcessing()
463 mMips->OR(Rd, Rn, src); in dataProcessing()
465 mMips->ORI(Rd, Rn, src); in dataProcessing()
476 mMips->AND(Rd, Rn, R_at); in dataProcessing()
485 mMips->SUBU(Rd, src, Rn); // subu with the parameters reversed in dataProcessing()
490 mMips->MOVE(Rd, Op2); in dataProcessing()
493 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
495 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
498 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
502 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
503 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
504 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
506 mMips->ROTR(Rd, amode.reg, amode.value); in dataProcessing()
508 mMips->RORIsyn(Rd, amode.reg, amode.value); in dataProcessing()
521 mMips->NOR(Rd, Op2, 0); // NOT is NOR with 0 in dataProcessing()
525 mMips->LUI(Rd, (amode.value >> 16)); in dataProcessing()
527 mMips->ORI(Rd, Rd, (amode.value & 0x0000ffff)); in dataProcessing()
530 mMips->ORI(Rd, 0, amode.value); in dataProcessing()
534 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; in dataProcessing()
535 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break; in dataProcessing()
536 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; in dataProcessing()
538 mMips->ROTR(Rd, amode.reg, amode.value); in dataProcessing()
540 mMips->RORIsyn(Rd, amode.reg, amode.value); in dataProcessing()
549 mMips->NOR(Rd, Rd, 0); // NOT is NOR with 0 in dataProcessing()
595 cond.r1 = Rd; in dataProcessing()
608 int Rd, int Rm, int Rs, int Rn) { in MLA() argument
613 mMips->ADDU(Rd, R_at, Rn); in MLA()
616 cond.r1 = Rd; in MLA()
621 int Rd, int Rm, int Rs) { in MUL() argument
623 mMips->MUL(Rd, Rm, Rs); in MUL()
626 cond.r1 = Rd; in MUL()
762 void ArmToMipsAssembler::LDR(int cc __unused, int Rd, int Rn, uint32_t offset) in LDR() argument
776 mMips->LW(Rd, Rn, amode.value); in LDR()
785 mMips->LW(Rd, Rn, 0); in LDR()
791 mMips->LW(Rd, R_at, 0); in LDR()
796 void ArmToMipsAssembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset) in LDRB() argument
807 mMips->LBU(Rd, Rn, amode.value); in LDRB()
813 mMips->LBU(Rd, Rn, 0); in LDRB()
819 mMips->LBU(Rd, R_at, 0); in LDRB()
825 void ArmToMipsAssembler::STR(int cc __unused, int Rd, int Rn, uint32_t offset) in STR() argument
843 mMips->SW(Rd, Rn, 0); in STR()
846 mMips->SW(Rd, Rn, amode.value); in STR()
850 mMips->SW(Rd, Rn, 0); in STR()
856 mMips->SW(Rd, R_at, 0); in STR()
861 void ArmToMipsAssembler::STRB(int cc __unused, int Rd, int Rn, uint32_t offset) in STRB() argument
872 mMips->SB(Rd, Rn, amode.value); in STRB()
878 mMips->SB(Rd, Rn, 0); in STRB()
884 mMips->SB(Rd, R_at, 0); in STRB()
889 void ArmToMipsAssembler::LDRH(int cc __unused, int Rd, int Rn, uint32_t offset) in LDRH() argument
899 mMips->LHU(Rd, Rn, amode.value); in LDRH()
902 mMips->LHU(Rd, Rn, 0); in LDRH()
912 mMips->LHU(Rd, R_at, 0); in LDRH()
917 void ArmToMipsAssembler::LDRSB(int cc __unused, int Rd __unused, in LDRSB()
925 void ArmToMipsAssembler::LDRSH(int cc __unused, int Rd __unused, in LDRSH()
933 void ArmToMipsAssembler::STRH(int cc __unused, int Rd, int Rn, uint32_t offset) in STRH() argument
943 mMips->SH(Rd, Rn, amode.value); in STRH()
946 mMips->SH(Rd, Rn, 0); in STRH()
956 mMips->SH(Rd, R_at, 0); in STRH()
1002 int Rd __unused, int Rm __unused) { in SWP()
1010 int Rd __unused, int Rm __unused) { in SWPB()
1040 void ArmToMipsAssembler::CLZ(int cc __unused, int Rd, int Rm) in CLZ() argument
1043 mMips->CLZ(Rd, Rm); in CLZ()
1046 void ArmToMipsAssembler::QADD(int cc __unused, int Rd __unused, in QADD()
1055 void ArmToMipsAssembler::QDADD(int cc __unused, int Rd __unused, in QDADD()
1064 void ArmToMipsAssembler::QSUB(int cc __unused, int Rd __unused, in QSUB()
1073 void ArmToMipsAssembler::QDSUB(int cc __unused, int Rd __unused, in QDSUB()
1084 int Rd, int Rm, int Rs) in SMUL() argument
1118 mMips->MUL(Rd, R_at, R_at2); in SMUL()
1123 int Rd, int Rm, int Rs) in SMULW() argument
1138 mMips->MFHI(Rd); in SMULW()
1143 int Rd, int Rm, int Rs, int Rn) in SMLA() argument
1179 mMips->ADDU(Rd, R_at, Rn); in SMLA()
1193 int Rd __unused, int Rm __unused, in SMLAW()
1203 void ArmToMipsAssembler::UXTB16(int cc __unused, int Rd, int Rm, int rotate) in UXTB16() argument
1211 mMips->AND(Rd, Rm, 0x00FF00FF); in UXTB16()
1214 void ArmToMipsAssembler::UBFX(int cc __unused, int Rd __unused, in UBFX()
1439 void MIPSAssembler::ADDU(int Rd, int Rs, int Rt) in ADDU() argument
1442 | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF); in ADDU()
1452 void MIPSAssembler::SUBU(int Rd, int Rs, int Rt) in SUBU() argument
1455 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in SUBU()
1465 void MIPSAssembler::NEGU(int Rd, int Rs) // really subu(d, zero, s) in NEGU() argument
1467 MIPSAssembler::SUBU(Rd, 0, Rs); in NEGU()
1470 void MIPSAssembler::MUL(int Rd, int Rs, int Rt) in MUL() argument
1473 (Rs<<RS_SHF) | (Rt<<RT_SHF) | (Rd<<RD_SHF) ; in MUL()
1508 void MIPSAssembler::SEB(int Rd, int Rt) // sign-extend byte (mips32r2) in SEB() argument
1511 (Rt<<RT_SHF) | (Rd<<RD_SHF); in SEB()
1514 void MIPSAssembler::SEH(int Rd, int Rt) // sign-extend half-word (mips32r2) in SEH() argument
1517 (Rt<<RT_SHF) | (Rd<<RD_SHF); in SEH()
1527 void MIPSAssembler::SLT(int Rd, int Rs, int Rt) in SLT() argument
1530 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in SLT()
1539 void MIPSAssembler::SLTU(int Rd, int Rs, int Rt) in SLTU() argument
1542 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in SLTU()
1557 void MIPSAssembler::AND(int Rd, int Rs, int Rt) in AND() argument
1560 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in AND()
1569 void MIPSAssembler::OR(int Rd, int Rs, int Rt) in OR() argument
1572 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in OR()
1580 void MIPSAssembler::NOR(int Rd, int Rs, int Rt) in NOR() argument
1583 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in NOR()
1586 void MIPSAssembler::NOT(int Rd, int Rs) in NOT() argument
1588 MIPSAssembler::NOR(Rd, Rs, 0); // NOT(d,s) = NOR(d,s,zero) in NOT()
1591 void MIPSAssembler::XOR(int Rd, int Rs, int Rt) in XOR() argument
1594 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in XOR()
1602 void MIPSAssembler::SLL(int Rd, int Rt, int shft) in SLL() argument
1605 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF); in SLL()
1608 void MIPSAssembler::SLLV(int Rd, int Rt, int Rs) in SLLV() argument
1611 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in SLLV()
1614 void MIPSAssembler::SRL(int Rd, int Rt, int shft) in SRL() argument
1617 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF); in SRL()
1620 void MIPSAssembler::SRLV(int Rd, int Rt, int Rs) in SRLV() argument
1623 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in SRLV()
1626 void MIPSAssembler::SRA(int Rd, int Rt, int shft) in SRA() argument
1629 (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF); in SRA()
1632 void MIPSAssembler::SRAV(int Rd, int Rt, int Rs) in SRAV() argument
1635 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in SRAV()
1638 void MIPSAssembler::ROTR(int Rd, int Rt, int shft) // mips32r2 in ROTR() argument
1642 (1<<RS_SHF) | (Rd<<RD_SHF) | (Rt<<RT_SHF) | (shft<<RE_SHF); in ROTR()
1645 void MIPSAssembler::ROTRV(int Rd, int Rt, int Rs) // mips32r2 in ROTRV() argument
1649 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF) | (1<<RE_SHF); in ROTRV()
1653 void MIPSAssembler::RORsyn(int Rd, int Rt, int Rs) in RORsyn() argument
1658 MIPSAssembler::SRLV(Rd, Rt, Rs); in RORsyn()
1659 MIPSAssembler::OR(Rd, Rd, R_at2); in RORsyn()
1663 void MIPSAssembler::RORIsyn(int Rd, int Rt, int rot) in RORIsyn() argument
1668 MIPSAssembler::SRL(Rd, Rt, rot); in RORIsyn()
1669 MIPSAssembler::OR(Rd, Rd, R_at2); in RORIsyn()
1672 void MIPSAssembler::CLO(int Rd, int Rs) in CLO() argument
1676 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF); in CLO()
1679 void MIPSAssembler::CLZ(int Rd, int Rs) in CLZ() argument
1683 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rd<<RT_SHF); in CLZ()
1686 void MIPSAssembler::WSBH(int Rd, int Rt) // mips32r2 in WSBH() argument
1689 (Rt<<RT_SHF) | (Rd<<RD_SHF); in WSBH()
1753 void MIPSAssembler::MOVE(int Rd, int Rs) in MOVE() argument
1757 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (0<<RT_SHF); in MOVE()
1760 void MIPSAssembler::MOVN(int Rd, int Rs, int Rt) in MOVN() argument
1763 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in MOVN()
1766 void MIPSAssembler::MOVZ(int Rd, int Rs, int Rt) in MOVZ() argument
1769 (Rd<<RD_SHF) | (Rs<<RS_SHF) | (Rt<<RT_SHF); in MOVZ()
1772 void MIPSAssembler::MFHI(int Rd) in MFHI() argument
1774 *mPC++ = (spec_op<<OP_SHF) | (mfhi_fn<<FUNC_SHF) | (Rd<<RD_SHF); in MFHI()
1777 void MIPSAssembler::MFLO(int Rd) in MFLO() argument
1779 *mPC++ = (spec_op<<OP_SHF) | (mflo_fn<<FUNC_SHF) | (Rd<<RD_SHF); in MFLO()