'H$D(# FVP Basearm,vfp-basearm,vexpress"1chosen=serial0aliases/I/smb/motherboard/iofpga@3,00000000/uart@090000/Q/smb/motherboard/iofpga@3,00000000/uart@0a0000/Y/smb/motherboard/iofpga@3,00000000/uart@0b0000/a/smb/motherboard/iofpga@3,00000000/uart@0c0000psci#arm,psci-1.0arm,psci-0.2arm,psciismcp| cpus"1cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 idle-states arm,pscicpu-sleep-0arm,idle-state(d  cluster-sleep-0arm,idle-state   cpu@0cpu arm,armv8'+psci9  cpu@1cpu arm,armv8'+psci9  cpu@2cpu arm,armv8'+psci9  cpu@3cpu arm,armv8'+psci9  cpu@100cpu arm,armv8'+psci9  cpu@101cpu arm,armv8'+psci9  cpu@102cpu arm,armv8'+psci9  cpu@103cpu arm,armv8'+psci9   memory@80000000memory 'interrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gicI"Z@',, ,@ ,`  o  timerarm,armv8-timer0o   ztimer@2a810000arm,armv7-timer-mem'*z"1frame@2a830000 o'*pmuarm,armv8-pmuv30o<=>?smb simple-bus"1x I ?            !!""##$$%%&&''(())**motherboardrs1arm,vexpress,v2m-p1simple-bus"1Iflash@0,00000000arm,vexpress-flashcfi-flash'vram@2,00000000arm,vexpress-vram 'ethernet@2,02000000smsc,lan91c111 'oclk24mhz fixed-clockzn6 v2m:clk24mhz refclk1mhz fixed-clockzB@v2m:refclk1mhz  refclk32khz fixed-clockzv2m:refclk32khz  iofpga@3,00000000arm,amba-bussimple-bus"1 sysreg@010000arm,vexpress-sysreg'  sysctl@020000arm,sp810arm,primecell'   refclktimclkapb_pclk0timerclken0timerclken1timerclken2timerclken3 aaci@040000arm,pl041arm,primecell'o   apb_pclkmmci@050000arm,pl180arm,primecell'o  , 5>L mclkapb_pclkkmi@060000arm,pl050arm,primecell'o  KMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecell'o  KMIREFCLKapb_pclkuart@090000arm,pl011arm,primecell' o uartclkapb_pclkuart@0a0000arm,pl011arm,primecell' o uartclkapb_pclkuart@0b0000arm,pl011arm,primecell' o uartclkapb_pclkuart@0c0000arm,pl011arm,primecell' o uartclkapb_pclkwdt@0f0000arm,sp805arm,primecell'o  wdogclkapb_pclktimer@110000arm,sp804arm,primecell'o timclken1timclken2apb_pclktimer@120000arm,sp804arm,primecell'o timclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecell'o  apb_pclkclcd@1f0000arm,pl111arm,primecell'o clcdclkapb_pclkXXVGA]evirtio_block@0130000 virtio,mmio'o*fixedregulator@0regulator-fixedq3V32Z2Z mcc#arm,vexpress,config-bussimple-busosc@1arm,vexpress-oscjep v2m:oscclk1 muxfpga@0arm,vexpress-muxfpgadvimode@0arm,vexpress-dvimode panelspanel@0panelXXVGA< =*07DQh[ejFB_VMODE_NONINTERLACEDpTIM2_BCDTIM2_IPC&uCNTL_LCDTFTCNTL_BGRCNTL_LCDVCOMP(1)(zCLCD_CAP_5551CLCD_CAP_565CLCD_CAP_888 modelcompatibleinterrupt-parent#address-cells#size-cellsstdout-pathserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_onsys_poweroffsys_resetcpuentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namescd-gpioswp-gpiosmax-frequencyvmmc-supplymodeuse_dmaframebufferregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangerefreshxresyrespixclockleft_marginright_marginupper_marginlower_marginhsync_lenvsync_lensyncvmodetim2cntlcapsbpp