/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(0),
    UINT64_C(44040192),	// ADCri
    UINT64_C(10485760),	// ADCrr
    UINT64_C(10485760),	// ADCrsi
    UINT64_C(10485776),	// ADCrsr
    UINT64_C(41943040),	// ADDri
    UINT64_C(8388608),	// ADDrr
    UINT64_C(8388608),	// ADDrsi
    UINT64_C(8388624),	// ADDrsr
    UINT64_C(34537472),	// ADR
    UINT64_C(4088398656),	// AESD
    UINT64_C(4088398592),	// AESE
    UINT64_C(4088398784),	// AESIMC
    UINT64_C(4088398720),	// AESMC
    UINT64_C(33554432),	// ANDri
    UINT64_C(0),	// ANDrr
    UINT64_C(0),	// ANDrsi
    UINT64_C(16),	// ANDrsr
    UINT64_C(130023455),	// BFC
    UINT64_C(130023440),	// BFI
    UINT64_C(62914560),	// BICri
    UINT64_C(29360128),	// BICrr
    UINT64_C(29360128),	// BICrsi
    UINT64_C(29360144),	// BICrsr
    UINT64_C(3776970864),	// BKPT
    UINT64_C(3942645760),	// BL
    UINT64_C(3778019120),	// BLX
    UINT64_C(19922736),	// BLX_pred
    UINT64_C(4194304000),	// BLXi
    UINT64_C(184549376),	// BL_pred
    UINT64_C(3778019088),	// BX
    UINT64_C(19922720),	// BXJ
    UINT64_C(19922718),	// BX_RET
    UINT64_C(19922704),	// BX_pred
    UINT64_C(167772160),	// Bcc
    UINT64_C(234881024),	// CDP
    UINT64_C(4261412864),	// CDP2
    UINT64_C(4118802463),	// CLREX
    UINT64_C(24055568),	// CLZ
    UINT64_C(57671680),	// CMNri
    UINT64_C(24117248),	// CMNzrr
    UINT64_C(24117248),	// CMNzrsi
    UINT64_C(24117264),	// CMNzrsr
    UINT64_C(55574528),	// CMPri
    UINT64_C(22020096),	// CMPrr
    UINT64_C(22020096),	// CMPrsi
    UINT64_C(22020112),	// CMPrsr
    UINT64_C(4043440128),	// CPS1p
    UINT64_C(4043309056),	// CPS2p
    UINT64_C(4043440128),	// CPS3p
    UINT64_C(3774873664),	// CRC32B
    UINT64_C(3774874176),	// CRC32CB
    UINT64_C(3776971328),	// CRC32CH
    UINT64_C(3779068480),	// CRC32CW
    UINT64_C(3776970816),	// CRC32H
    UINT64_C(3779067968),	// CRC32W
    UINT64_C(52490480),	// DBG
    UINT64_C(4118802512),	// DMB
    UINT64_C(4118802496),	// DSB
    UINT64_C(35651584),	// EORri
    UINT64_C(2097152),	// EORrr
    UINT64_C(2097152),	// EORrsi
    UINT64_C(2097168),	// EORrsr
    UINT64_C(23068782),	// ERET
    UINT64_C(246418176),	// FCONSTD
    UINT64_C(246417664),	// FCONSTH
    UINT64_C(246417920),	// FCONSTS
    UINT64_C(221252353),	// FLDMXDB_UPD
    UINT64_C(210766593),	// FLDMXIA
    UINT64_C(212863745),	// FLDMXIA_UPD
    UINT64_C(250739216),	// FMSTAT
    UINT64_C(220203777),	// FSTMXDB_UPD
    UINT64_C(209718017),	// FSTMXIA
    UINT64_C(211815169),	// FSTMXIA_UPD
    UINT64_C(52490240),	// HINT
    UINT64_C(3774873712),	// HLT
    UINT64_C(3779068016),	// HVC
    UINT64_C(4118802528),	// ISB
    UINT64_C(26217631),	// LDA
    UINT64_C(30411935),	// LDAB
    UINT64_C(26218143),	// LDAEX
    UINT64_C(30412447),	// LDAEXB
    UINT64_C(28315295),	// LDAEXD
    UINT64_C(32509599),	// LDAEXH
    UINT64_C(32509087),	// LDAH
    UINT64_C(4249878528),	// LDC2L_OFFSET
    UINT64_C(4241489920),	// LDC2L_OPTION
    UINT64_C(4235198464),	// LDC2L_POST
    UINT64_C(4251975680),	// LDC2L_PRE
    UINT64_C(4245684224),	// LDC2_OFFSET
    UINT64_C(4237295616),	// LDC2_OPTION
    UINT64_C(4231004160),	// LDC2_POST
    UINT64_C(4247781376),	// LDC2_PRE
    UINT64_C(223346688),	// LDCL_OFFSET
    UINT64_C(214958080),	// LDCL_OPTION
    UINT64_C(208666624),	// LDCL_POST
    UINT64_C(225443840),	// LDCL_PRE
    UINT64_C(219152384),	// LDC_OFFSET
    UINT64_C(210763776),	// LDC_OPTION
    UINT64_C(204472320),	// LDC_POST
    UINT64_C(221249536),	// LDC_PRE
    UINT64_C(135266304),	// LDMDA
    UINT64_C(137363456),	// LDMDA_UPD
    UINT64_C(152043520),	// LDMDB
    UINT64_C(154140672),	// LDMDB_UPD
    UINT64_C(143654912),	// LDMIA
    UINT64_C(145752064),	// LDMIA_UPD
    UINT64_C(160432128),	// LDMIB
    UINT64_C(162529280),	// LDMIB_UPD
    UINT64_C(74448896),	// LDRBT_POST_IMM
    UINT64_C(108003328),	// LDRBT_POST_REG
    UINT64_C(72351744),	// LDRB_POST_IMM
    UINT64_C(105906176),	// LDRB_POST_REG
    UINT64_C(91226112),	// LDRB_PRE_IMM
    UINT64_C(124780544),	// LDRB_PRE_REG
    UINT64_C(89128960),	// LDRBi12
    UINT64_C(122683392),	// LDRBrs
    UINT64_C(16777424),	// LDRD
    UINT64_C(208),	// LDRD_POST
    UINT64_C(18874576),	// LDRD_PRE
    UINT64_C(26218399),	// LDREX
    UINT64_C(30412703),	// LDREXB
    UINT64_C(28315551),	// LDREXD
    UINT64_C(32509855),	// LDREXH
    UINT64_C(17825968),	// LDRH
    UINT64_C(7340208),	// LDRHTi
    UINT64_C(3145904),	// LDRHTr
    UINT64_C(1048752),	// LDRH_POST
    UINT64_C(19923120),	// LDRH_PRE
    UINT64_C(17826000),	// LDRSB
    UINT64_C(7340240),	// LDRSBTi
    UINT64_C(3145936),	// LDRSBTr
    UINT64_C(1048784),	// LDRSB_POST
    UINT64_C(19923152),	// LDRSB_PRE
    UINT64_C(17826032),	// LDRSH
    UINT64_C(7340272),	// LDRSHTi
    UINT64_C(3145968),	// LDRSHTr
    UINT64_C(1048816),	// LDRSH_POST
    UINT64_C(19923184),	// LDRSH_PRE
    UINT64_C(70254592),	// LDRT_POST_IMM
    UINT64_C(103809024),	// LDRT_POST_REG
    UINT64_C(68157440),	// LDR_POST_IMM
    UINT64_C(101711872),	// LDR_POST_REG
    UINT64_C(87031808),	// LDR_PRE_IMM
    UINT64_C(120586240),	// LDR_PRE_REG
    UINT64_C(85917696),	// LDRcp
    UINT64_C(84934656),	// LDRi12
    UINT64_C(118489088),	// LDRrs
    UINT64_C(234881040),	// MCR
    UINT64_C(4261412880),	// MCR2
    UINT64_C(205520896),	// MCRR
    UINT64_C(4232052736),	// MCRR2
    UINT64_C(2097296),	// MLA
    UINT64_C(6291600),	// MLS
    UINT64_C(27324430),	// MOVPCLR
    UINT64_C(54525952),	// MOVTi16
    UINT64_C(60817408),	// MOVi
    UINT64_C(50331648),	// MOVi16
    UINT64_C(27262976),	// MOVr
    UINT64_C(27262976),	// MOVr_TC
    UINT64_C(27262976),	// MOVsi
    UINT64_C(27262992),	// MOVsr
    UINT64_C(235929616),	// MRC
    UINT64_C(4262461456),	// MRC2
    UINT64_C(206569472),	// MRRC
    UINT64_C(4233101312),	// MRRC2
    UINT64_C(17760256),	// MRS
    UINT64_C(16777728),	// MRSbanked
    UINT64_C(21954560),	// MRSsys
    UINT64_C(18935808),	// MSR
    UINT64_C(18936320),	// MSRbanked
    UINT64_C(52490240),	// MSRi
    UINT64_C(144),	// MUL
    UINT64_C(65011712),	// MVNi
    UINT64_C(31457280),	// MVNr
    UINT64_C(31457280),	// MVNsi
    UINT64_C(31457296),	// MVNsr
    UINT64_C(58720256),	// ORRri
    UINT64_C(25165824),	// ORRrr
    UINT64_C(25165824),	// ORRrsi
    UINT64_C(25165840),	// ORRrsr
    UINT64_C(109051920),	// PKHBT
    UINT64_C(109051984),	// PKHTB
    UINT64_C(4111527936),	// PLDWi12
    UINT64_C(4145082368),	// PLDWrs
    UINT64_C(4115722240),	// PLDi12
    UINT64_C(4149276672),	// PLDrs
    UINT64_C(4098945024),	// PLIi12
    UINT64_C(4132499456),	// PLIrs
    UINT64_C(16777296),	// QADD
    UINT64_C(102764304),	// QADD16
    UINT64_C(102764432),	// QADD8
    UINT64_C(102764336),	// QASX
    UINT64_C(20971600),	// QDADD
    UINT64_C(23068752),	// QDSUB
    UINT64_C(102764368),	// QSAX
    UINT64_C(18874448),	// QSUB
    UINT64_C(102764400),	// QSUB16
    UINT64_C(102764528),	// QSUB8
    UINT64_C(117378864),	// RBIT
    UINT64_C(113184560),	// REV
    UINT64_C(113184688),	// REV16
    UINT64_C(117378992),	// REVSH
    UINT64_C(4161800704),	// RFEDA
    UINT64_C(4163897856),	// RFEDA_UPD
    UINT64_C(4178577920),	// RFEDB
    UINT64_C(4180675072),	// RFEDB_UPD
    UINT64_C(4170189312),	// RFEIA
    UINT64_C(4172286464),	// RFEIA_UPD
    UINT64_C(4186966528),	// RFEIB
    UINT64_C(4189063680),	// RFEIB_UPD
    UINT64_C(39845888),	// RSBri
    UINT64_C(6291456),	// RSBrr
    UINT64_C(6291456),	// RSBrsi
    UINT64_C(6291472),	// RSBrsr
    UINT64_C(48234496),	// RSCri
    UINT64_C(14680064),	// RSCrr
    UINT64_C(14680064),	// RSCrsi
    UINT64_C(14680080),	// RSCrsr
    UINT64_C(101715728),	// SADD16
    UINT64_C(101715856),	// SADD8
    UINT64_C(101715760),	// SASX
    UINT64_C(46137344),	// SBCri
    UINT64_C(12582912),	// SBCrr
    UINT64_C(12582912),	// SBCrsi
    UINT64_C(12582928),	// SBCrsr
    UINT64_C(127926352),	// SBFX
    UINT64_C(118550544),	// SDIV
    UINT64_C(109055920),	// SEL
    UINT64_C(4043374592),	// SETEND
    UINT64_C(4044357632),	// SETPAN
    UINT64_C(4060089408),	// SHA1C
    UINT64_C(4088988352),	// SHA1H
    UINT64_C(4062186560),	// SHA1M
    UINT64_C(4061137984),	// SHA1P
    UINT64_C(4063235136),	// SHA1SU0
    UINT64_C(4089054080),	// SHA1SU1
    UINT64_C(4076866624),	// SHA256H
    UINT64_C(4077915200),	// SHA256H2
    UINT64_C(4089054144),	// SHA256SU0
    UINT64_C(4078963776),	// SHA256SU1
    UINT64_C(103812880),	// SHADD16
    UINT64_C(103813008),	// SHADD8
    UINT64_C(103812912),	// SHASX
    UINT64_C(103812944),	// SHSAX
    UINT64_C(103812976),	// SHSUB16
    UINT64_C(103813104),	// SHSUB8
    UINT64_C(23068784),	// SMC
    UINT64_C(16777344),	// SMLABB
    UINT64_C(16777408),	// SMLABT
    UINT64_C(117440528),	// SMLAD
    UINT64_C(117440560),	// SMLADX
    UINT64_C(14680208),	// SMLAL
    UINT64_C(20971648),	// SMLALBB
    UINT64_C(20971712),	// SMLALBT
    UINT64_C(121634832),	// SMLALD
    UINT64_C(121634864),	// SMLALDX
    UINT64_C(20971680),	// SMLALTB
    UINT64_C(20971744),	// SMLALTT
    UINT64_C(16777376),	// SMLATB
    UINT64_C(16777440),	// SMLATT
    UINT64_C(18874496),	// SMLAWB
    UINT64_C(18874560),	// SMLAWT
    UINT64_C(117440592),	// SMLSD
    UINT64_C(117440624),	// SMLSDX
    UINT64_C(121634896),	// SMLSLD
    UINT64_C(121634928),	// SMLSLDX
    UINT64_C(122683408),	// SMMLA
    UINT64_C(122683440),	// SMMLAR
    UINT64_C(122683600),	// SMMLS
    UINT64_C(122683632),	// SMMLSR
    UINT64_C(122744848),	// SMMUL
    UINT64_C(122744880),	// SMMULR
    UINT64_C(117501968),	// SMUAD
    UINT64_C(117502000),	// SMUADX
    UINT64_C(23068800),	// SMULBB
    UINT64_C(23068864),	// SMULBT
    UINT64_C(12583056),	// SMULL
    UINT64_C(23068832),	// SMULTB
    UINT64_C(23068896),	// SMULTT
    UINT64_C(18874528),	// SMULWB
    UINT64_C(18874592),	// SMULWT
    UINT64_C(117502032),	// SMUSD
    UINT64_C(117502064),	// SMUSDX
    UINT64_C(4165797120),	// SRSDA
    UINT64_C(4167894272),	// SRSDA_UPD
    UINT64_C(4182574336),	// SRSDB
    UINT64_C(4184671488),	// SRSDB_UPD
    UINT64_C(4174185728),	// SRSIA
    UINT64_C(4176282880),	// SRSIA_UPD
    UINT64_C(4190962944),	// SRSIB
    UINT64_C(4193060096),	// SRSIB_UPD
    UINT64_C(111149072),	// SSAT
    UINT64_C(111152944),	// SSAT16
    UINT64_C(101715792),	// SSAX
    UINT64_C(101715824),	// SSUB16
    UINT64_C(101715952),	// SSUB8
    UINT64_C(4248829952),	// STC2L_OFFSET
    UINT64_C(4240441344),	// STC2L_OPTION
    UINT64_C(4234149888),	// STC2L_POST
    UINT64_C(4250927104),	// STC2L_PRE
    UINT64_C(4244635648),	// STC2_OFFSET
    UINT64_C(4236247040),	// STC2_OPTION
    UINT64_C(4229955584),	// STC2_POST
    UINT64_C(4246732800),	// STC2_PRE
    UINT64_C(222298112),	// STCL_OFFSET
    UINT64_C(213909504),	// STCL_OPTION
    UINT64_C(207618048),	// STCL_POST
    UINT64_C(224395264),	// STCL_PRE
    UINT64_C(218103808),	// STC_OFFSET
    UINT64_C(209715200),	// STC_OPTION
    UINT64_C(203423744),	// STC_POST
    UINT64_C(220200960),	// STC_PRE
    UINT64_C(25230480),	// STL
    UINT64_C(29424784),	// STLB
    UINT64_C(25169552),	// STLEX
    UINT64_C(29363856),	// STLEXB
    UINT64_C(27266704),	// STLEXD
    UINT64_C(31461008),	// STLEXH
    UINT64_C(31521936),	// STLH
    UINT64_C(134217728),	// STMDA
    UINT64_C(136314880),	// STMDA_UPD
    UINT64_C(150994944),	// STMDB
    UINT64_C(153092096),	// STMDB_UPD
    UINT64_C(142606336),	// STMIA
    UINT64_C(144703488),	// STMIA_UPD
    UINT64_C(159383552),	// STMIB
    UINT64_C(161480704),	// STMIB_UPD
    UINT64_C(73400320),	// STRBT_POST_IMM
    UINT64_C(106954752),	// STRBT_POST_REG
    UINT64_C(71303168),	// STRB_POST_IMM
    UINT64_C(104857600),	// STRB_POST_REG
    UINT64_C(90177536),	// STRB_PRE_IMM
    UINT64_C(123731968),	// STRB_PRE_REG
    UINT64_C(88080384),	// STRBi12
    UINT64_C(121634816),	// STRBrs
    UINT64_C(16777456),	// STRD
    UINT64_C(240),	// STRD_POST
    UINT64_C(18874608),	// STRD_PRE
    UINT64_C(25169808),	// STREX
    UINT64_C(29364112),	// STREXB
    UINT64_C(27266960),	// STREXD
    UINT64_C(31461264),	// STREXH
    UINT64_C(16777392),	// STRH
    UINT64_C(6291632),	// STRHTi
    UINT64_C(2097328),	// STRHTr
    UINT64_C(176),	// STRH_POST
    UINT64_C(18874544),	// STRH_PRE
    UINT64_C(69206016),	// STRT_POST_IMM
    UINT64_C(102760448),	// STRT_POST_REG
    UINT64_C(67108864),	// STR_POST_IMM
    UINT64_C(100663296),	// STR_POST_REG
    UINT64_C(85983232),	// STR_PRE_IMM
    UINT64_C(119537664),	// STR_PRE_REG
    UINT64_C(83886080),	// STRi12
    UINT64_C(117440512),	// STRrs
    UINT64_C(37748736),	// SUBri
    UINT64_C(4194304),	// SUBrr
    UINT64_C(4194304),	// SUBrsi
    UINT64_C(4194320),	// SUBrsr
    UINT64_C(251658240),	// SVC
    UINT64_C(16777360),	// SWP
    UINT64_C(20971664),	// SWPB
    UINT64_C(111149168),	// SXTAB
    UINT64_C(109052016),	// SXTAB16
    UINT64_C(112197744),	// SXTAH
    UINT64_C(112132208),	// SXTB
    UINT64_C(110035056),	// SXTB16
    UINT64_C(113180784),	// SXTH
    UINT64_C(53477376),	// TEQri
    UINT64_C(19922944),	// TEQrr
    UINT64_C(19922944),	// TEQrsi
    UINT64_C(19922960),	// TEQrsr
    UINT64_C(3892305662),	// TRAP
    UINT64_C(3892240112),	// TRAPNaCl
    UINT64_C(3810586642),	// TSB
    UINT64_C(51380224),	// TSTri
    UINT64_C(17825792),	// TSTrr
    UINT64_C(17825792),	// TSTrsi
    UINT64_C(17825808),	// TSTrsr
    UINT64_C(105910032),	// UADD16
    UINT64_C(105910160),	// UADD8
    UINT64_C(105910064),	// UASX
    UINT64_C(132120656),	// UBFX
    UINT64_C(3891265776),	// UDF
    UINT64_C(120647696),	// UDIV
    UINT64_C(108007184),	// UHADD16
    UINT64_C(108007312),	// UHADD8
    UINT64_C(108007216),	// UHASX
    UINT64_C(108007248),	// UHSAX
    UINT64_C(108007280),	// UHSUB16
    UINT64_C(108007408),	// UHSUB8
    UINT64_C(4194448),	// UMAAL
    UINT64_C(10485904),	// UMLAL
    UINT64_C(8388752),	// UMULL
    UINT64_C(106958608),	// UQADD16
    UINT64_C(106958736),	// UQADD8
    UINT64_C(106958640),	// UQASX
    UINT64_C(106958672),	// UQSAX
    UINT64_C(106958704),	// UQSUB16
    UINT64_C(106958832),	// UQSUB8
    UINT64_C(125890576),	// USAD8
    UINT64_C(125829136),	// USADA8
    UINT64_C(115343376),	// USAT
    UINT64_C(115347248),	// USAT16
    UINT64_C(105910096),	// USAX
    UINT64_C(105910128),	// USUB16
    UINT64_C(105910256),	// USUB8
    UINT64_C(115343472),	// UXTAB
    UINT64_C(113246320),	// UXTAB16
    UINT64_C(116392048),	// UXTAH
    UINT64_C(116326512),	// UXTB
    UINT64_C(114229360),	// UXTB16
    UINT64_C(117375088),	// UXTH
    UINT64_C(4070573312),	// VABALsv2i64
    UINT64_C(4069524736),	// VABALsv4i32
    UINT64_C(4068476160),	// VABALsv8i16
    UINT64_C(4087350528),	// VABALuv2i64
    UINT64_C(4086301952),	// VABALuv4i32
    UINT64_C(4085253376),	// VABALuv8i16
    UINT64_C(4060088144),	// VABAsv16i8
    UINT64_C(4062185232),	// VABAsv2i32
    UINT64_C(4061136656),	// VABAsv4i16
    UINT64_C(4062185296),	// VABAsv4i32
    UINT64_C(4061136720),	// VABAsv8i16
    UINT64_C(4060088080),	// VABAsv8i8
    UINT64_C(4076865360),	// VABAuv16i8
    UINT64_C(4078962448),	// VABAuv2i32
    UINT64_C(4077913872),	// VABAuv4i16
    UINT64_C(4078962512),	// VABAuv4i32
    UINT64_C(4077913936),	// VABAuv8i16
    UINT64_C(4076865296),	// VABAuv8i8
    UINT64_C(4070573824),	// VABDLsv2i64
    UINT64_C(4069525248),	// VABDLsv4i32
    UINT64_C(4068476672),	// VABDLsv8i16
    UINT64_C(4087351040),	// VABDLuv2i64
    UINT64_C(4086302464),	// VABDLuv4i32
    UINT64_C(4085253888),	// VABDLuv8i16
    UINT64_C(4078963968),	// VABDfd
    UINT64_C(4078964032),	// VABDfq
    UINT64_C(4080012544),	// VABDhd
    UINT64_C(4080012608),	// VABDhq
    UINT64_C(4060088128),	// VABDsv16i8
    UINT64_C(4062185216),	// VABDsv2i32
    UINT64_C(4061136640),	// VABDsv4i16
    UINT64_C(4062185280),	// VABDsv4i32
    UINT64_C(4061136704),	// VABDsv8i16
    UINT64_C(4060088064),	// VABDsv8i8
    UINT64_C(4076865344),	// VABDuv16i8
    UINT64_C(4078962432),	// VABDuv2i32
    UINT64_C(4077913856),	// VABDuv4i16
    UINT64_C(4078962496),	// VABDuv4i32
    UINT64_C(4077913920),	// VABDuv8i16
    UINT64_C(4076865280),	// VABDuv8i8
    UINT64_C(246418368),	// VABSD
    UINT64_C(246417856),	// VABSH
    UINT64_C(246418112),	// VABSS
    UINT64_C(4088989440),	// VABSfd
    UINT64_C(4088989504),	// VABSfq
    UINT64_C(4088727296),	// VABShd
    UINT64_C(4088727360),	// VABShq
    UINT64_C(4088464192),	// VABSv16i8
    UINT64_C(4088988416),	// VABSv2i32
    UINT64_C(4088726272),	// VABSv4i16
    UINT64_C(4088988480),	// VABSv4i32
    UINT64_C(4088726336),	// VABSv8i16
    UINT64_C(4088464128),	// VABSv8i8
    UINT64_C(4076867088),	// VACGEfd
    UINT64_C(4076867152),	// VACGEfq
    UINT64_C(4077915664),	// VACGEhd
    UINT64_C(4077915728),	// VACGEhq
    UINT64_C(4078964240),	// VACGTfd
    UINT64_C(4078964304),	// VACGTfq
    UINT64_C(4080012816),	// VACGThd
    UINT64_C(4080012880),	// VACGThq
    UINT64_C(238029568),	// VADDD
    UINT64_C(238029056),	// VADDH
    UINT64_C(4070573056),	// VADDHNv2i32
    UINT64_C(4069524480),	// VADDHNv4i16
    UINT64_C(4068475904),	// VADDHNv8i8
    UINT64_C(4070572032),	// VADDLsv2i64
    UINT64_C(4069523456),	// VADDLsv4i32
    UINT64_C(4068474880),	// VADDLsv8i16
    UINT64_C(4087349248),	// VADDLuv2i64
    UINT64_C(4086300672),	// VADDLuv4i32
    UINT64_C(4085252096),	// VADDLuv8i16
    UINT64_C(238029312),	// VADDS
    UINT64_C(4070572288),	// VADDWsv2i64
    UINT64_C(4069523712),	// VADDWsv4i32
    UINT64_C(4068475136),	// VADDWsv8i16
    UINT64_C(4087349504),	// VADDWuv2i64
    UINT64_C(4086300928),	// VADDWuv4i32
    UINT64_C(4085252352),	// VADDWuv8i16
    UINT64_C(4060089600),	// VADDfd
    UINT64_C(4060089664),	// VADDfq
    UINT64_C(4061138176),	// VADDhd
    UINT64_C(4061138240),	// VADDhq
    UINT64_C(4060088384),	// VADDv16i8
    UINT64_C(4063234048),	// VADDv1i64
    UINT64_C(4062185472),	// VADDv2i32
    UINT64_C(4063234112),	// VADDv2i64
    UINT64_C(4061136896),	// VADDv4i16
    UINT64_C(4062185536),	// VADDv4i32
    UINT64_C(4061136960),	// VADDv8i16
    UINT64_C(4060088320),	// VADDv8i8
    UINT64_C(4060086544),	// VANDd
    UINT64_C(4060086608),	// VANDq
    UINT64_C(4061135120),	// VBICd
    UINT64_C(4068475184),	// VBICiv2i32
    UINT64_C(4068477232),	// VBICiv4i16
    UINT64_C(4068475248),	// VBICiv4i32
    UINT64_C(4068477296),	// VBICiv8i16
    UINT64_C(4061135184),	// VBICq
    UINT64_C(4080009488),	// VBIFd
    UINT64_C(4080009552),	// VBIFq
    UINT64_C(4078960912),	// VBITd
    UINT64_C(4078960976),	// VBITq
    UINT64_C(4077912336),	// VBSLd
    UINT64_C(4077912400),	// VBSLq
    UINT64_C(4237297664),	// VCADDv2f32
    UINT64_C(4236249088),	// VCADDv4f16
    UINT64_C(4237297728),	// VCADDv4f32
    UINT64_C(4236249152),	// VCADDv8f16
    UINT64_C(4060089856),	// VCEQfd
    UINT64_C(4060089920),	// VCEQfq
    UINT64_C(4061138432),	// VCEQhd
    UINT64_C(4061138496),	// VCEQhq
    UINT64_C(4076865616),	// VCEQv16i8
    UINT64_C(4078962704),	// VCEQv2i32
    UINT64_C(4077914128),	// VCEQv4i16
    UINT64_C(4078962768),	// VCEQv4i32
    UINT64_C(4077914192),	// VCEQv8i16
    UINT64_C(4076865552),	// VCEQv8i8
    UINT64_C(4088463680),	// VCEQzv16i8
    UINT64_C(4088988928),	// VCEQzv2f32
    UINT64_C(4088987904),	// VCEQzv2i32
    UINT64_C(4088726784),	// VCEQzv4f16
    UINT64_C(4088988992),	// VCEQzv4f32
    UINT64_C(4088725760),	// VCEQzv4i16
    UINT64_C(4088987968),	// VCEQzv4i32
    UINT64_C(4088726848),	// VCEQzv8f16
    UINT64_C(4088725824),	// VCEQzv8i16
    UINT64_C(4088463616),	// VCEQzv8i8
    UINT64_C(4076867072),	// VCGEfd
    UINT64_C(4076867136),	// VCGEfq
    UINT64_C(4077915648),	// VCGEhd
    UINT64_C(4077915712),	// VCGEhq
    UINT64_C(4060087120),	// VCGEsv16i8
    UINT64_C(4062184208),	// VCGEsv2i32
    UINT64_C(4061135632),	// VCGEsv4i16
    UINT64_C(4062184272),	// VCGEsv4i32
    UINT64_C(4061135696),	// VCGEsv8i16
    UINT64_C(4060087056),	// VCGEsv8i8
    UINT64_C(4076864336),	// VCGEuv16i8
    UINT64_C(4078961424),	// VCGEuv2i32
    UINT64_C(4077912848),	// VCGEuv4i16
    UINT64_C(4078961488),	// VCGEuv4i32
    UINT64_C(4077912912),	// VCGEuv8i16
    UINT64_C(4076864272),	// VCGEuv8i8
    UINT64_C(4088463552),	// VCGEzv16i8
    UINT64_C(4088988800),	// VCGEzv2f32
    UINT64_C(4088987776),	// VCGEzv2i32
    UINT64_C(4088726656),	// VCGEzv4f16
    UINT64_C(4088988864),	// VCGEzv4f32
    UINT64_C(4088725632),	// VCGEzv4i16
    UINT64_C(4088987840),	// VCGEzv4i32
    UINT64_C(4088726720),	// VCGEzv8f16
    UINT64_C(4088725696),	// VCGEzv8i16
    UINT64_C(4088463488),	// VCGEzv8i8
    UINT64_C(4078964224),	// VCGTfd
    UINT64_C(4078964288),	// VCGTfq
    UINT64_C(4080012800),	// VCGThd
    UINT64_C(4080012864),	// VCGThq
    UINT64_C(4060087104),	// VCGTsv16i8
    UINT64_C(4062184192),	// VCGTsv2i32
    UINT64_C(4061135616),	// VCGTsv4i16
    UINT64_C(4062184256),	// VCGTsv4i32
    UINT64_C(4061135680),	// VCGTsv8i16
    UINT64_C(4060087040),	// VCGTsv8i8
    UINT64_C(4076864320),	// VCGTuv16i8
    UINT64_C(4078961408),	// VCGTuv2i32
    UINT64_C(4077912832),	// VCGTuv4i16
    UINT64_C(4078961472),	// VCGTuv4i32
    UINT64_C(4077912896),	// VCGTuv8i16
    UINT64_C(4076864256),	// VCGTuv8i8
    UINT64_C(4088463424),	// VCGTzv16i8
    UINT64_C(4088988672),	// VCGTzv2f32
    UINT64_C(4088987648),	// VCGTzv2i32
    UINT64_C(4088726528),	// VCGTzv4f16
    UINT64_C(4088988736),	// VCGTzv4f32
    UINT64_C(4088725504),	// VCGTzv4i16
    UINT64_C(4088987712),	// VCGTzv4i32
    UINT64_C(4088726592),	// VCGTzv8f16
    UINT64_C(4088725568),	// VCGTzv8i16
    UINT64_C(4088463360),	// VCGTzv8i8
    UINT64_C(4088463808),	// VCLEzv16i8
    UINT64_C(4088989056),	// VCLEzv2f32
    UINT64_C(4088988032),	// VCLEzv2i32
    UINT64_C(4088726912),	// VCLEzv4f16
    UINT64_C(4088989120),	// VCLEzv4f32
    UINT64_C(4088725888),	// VCLEzv4i16
    UINT64_C(4088988096),	// VCLEzv4i32
    UINT64_C(4088726976),	// VCLEzv8f16
    UINT64_C(4088725952),	// VCLEzv8i16
    UINT64_C(4088463744),	// VCLEzv8i8
    UINT64_C(4088398912),	// VCLSv16i8
    UINT64_C(4088923136),	// VCLSv2i32
    UINT64_C(4088660992),	// VCLSv4i16
    UINT64_C(4088923200),	// VCLSv4i32
    UINT64_C(4088661056),	// VCLSv8i16
    UINT64_C(4088398848),	// VCLSv8i8
    UINT64_C(4088463936),	// VCLTzv16i8
    UINT64_C(4088989184),	// VCLTzv2f32
    UINT64_C(4088988160),	// VCLTzv2i32
    UINT64_C(4088727040),	// VCLTzv4f16
    UINT64_C(4088989248),	// VCLTzv4f32
    UINT64_C(4088726016),	// VCLTzv4i16
    UINT64_C(4088988224),	// VCLTzv4i32
    UINT64_C(4088727104),	// VCLTzv8f16
    UINT64_C(4088726080),	// VCLTzv8i16
    UINT64_C(4088463872),	// VCLTzv8i8
    UINT64_C(4088399040),	// VCLZv16i8
    UINT64_C(4088923264),	// VCLZv2i32
    UINT64_C(4088661120),	// VCLZv4i16
    UINT64_C(4088923328),	// VCLZv4i32
    UINT64_C(4088661184),	// VCLZv8i16
    UINT64_C(4088398976),	// VCLZv8i8
    UINT64_C(4231006208),	// VCMLAv2f32
    UINT64_C(4269803520),	// VCMLAv2f32_indexed
    UINT64_C(4229957632),	// VCMLAv4f16
    UINT64_C(4261414912),	// VCMLAv4f16_indexed
    UINT64_C(4231006272),	// VCMLAv4f32
    UINT64_C(4269803584),	// VCMLAv4f32_indexed
    UINT64_C(4229957696),	// VCMLAv8f16
    UINT64_C(4261414976),	// VCMLAv8f16_indexed
    UINT64_C(246680384),	// VCMPD
    UINT64_C(246680512),	// VCMPED
    UINT64_C(246680000),	// VCMPEH
    UINT64_C(246680256),	// VCMPES
    UINT64_C(246746048),	// VCMPEZD
    UINT64_C(246745536),	// VCMPEZH
    UINT64_C(246745792),	// VCMPEZS
    UINT64_C(246679872),	// VCMPH
    UINT64_C(246680128),	// VCMPS
    UINT64_C(246745920),	// VCMPZD
    UINT64_C(246745408),	// VCMPZH
    UINT64_C(246745664),	// VCMPZS
    UINT64_C(4088399104),	// VCNTd
    UINT64_C(4088399168),	// VCNTq
    UINT64_C(4089118720),	// VCVTANSDf
    UINT64_C(4088856576),	// VCVTANSDh
    UINT64_C(4089118784),	// VCVTANSQf
    UINT64_C(4088856640),	// VCVTANSQh
    UINT64_C(4089118848),	// VCVTANUDf
    UINT64_C(4088856704),	// VCVTANUDh
    UINT64_C(4089118912),	// VCVTANUQf
    UINT64_C(4088856768),	// VCVTANUQh
    UINT64_C(4273736640),	// VCVTASD
    UINT64_C(4273736128),	// VCVTASH
    UINT64_C(4273736384),	// VCVTASS
    UINT64_C(4273736512),	// VCVTAUD
    UINT64_C(4273736000),	// VCVTAUH
    UINT64_C(4273736256),	// VCVTAUS
    UINT64_C(246614848),	// VCVTBDH
    UINT64_C(246549312),	// VCVTBHD
    UINT64_C(246549056),	// VCVTBHS
    UINT64_C(246614592),	// VCVTBSH
    UINT64_C(246876864),	// VCVTDS
    UINT64_C(4089119488),	// VCVTMNSDf
    UINT64_C(4088857344),	// VCVTMNSDh
    UINT64_C(4089119552),	// VCVTMNSQf
    UINT64_C(4088857408),	// VCVTMNSQh
    UINT64_C(4089119616),	// VCVTMNUDf
    UINT64_C(4088857472),	// VCVTMNUDh
    UINT64_C(4089119680),	// VCVTMNUQf
    UINT64_C(4088857536),	// VCVTMNUQh
    UINT64_C(4273933248),	// VCVTMSD
    UINT64_C(4273932736),	// VCVTMSH
    UINT64_C(4273932992),	// VCVTMSS
    UINT64_C(4273933120),	// VCVTMUD
    UINT64_C(4273932608),	// VCVTMUH
    UINT64_C(4273932864),	// VCVTMUS
    UINT64_C(4089118976),	// VCVTNNSDf
    UINT64_C(4088856832),	// VCVTNNSDh
    UINT64_C(4089119040),	// VCVTNNSQf
    UINT64_C(4088856896),	// VCVTNNSQh
    UINT64_C(4089119104),	// VCVTNNUDf
    UINT64_C(4088856960),	// VCVTNNUDh
    UINT64_C(4089119168),	// VCVTNNUQf
    UINT64_C(4088857024),	// VCVTNNUQh
    UINT64_C(4273802176),	// VCVTNSD
    UINT64_C(4273801664),	// VCVTNSH
    UINT64_C(4273801920),	// VCVTNSS
    UINT64_C(4273802048),	// VCVTNUD
    UINT64_C(4273801536),	// VCVTNUH
    UINT64_C(4273801792),	// VCVTNUS
    UINT64_C(4089119232),	// VCVTPNSDf
    UINT64_C(4088857088),	// VCVTPNSDh
    UINT64_C(4089119296),	// VCVTPNSQf
    UINT64_C(4088857152),	// VCVTPNSQh
    UINT64_C(4089119360),	// VCVTPNUDf
    UINT64_C(4088857216),	// VCVTPNUDh
    UINT64_C(4089119424),	// VCVTPNUQf
    UINT64_C(4088857280),	// VCVTPNUQh
    UINT64_C(4273867712),	// VCVTPSD
    UINT64_C(4273867200),	// VCVTPSH
    UINT64_C(4273867456),	// VCVTPSS
    UINT64_C(4273867584),	// VCVTPUD
    UINT64_C(4273867072),	// VCVTPUH
    UINT64_C(4273867328),	// VCVTPUS
    UINT64_C(246877120),	// VCVTSD
    UINT64_C(246614976),	// VCVTTDH
    UINT64_C(246549440),	// VCVTTHD
    UINT64_C(246549184),	// VCVTTHS
    UINT64_C(246614720),	// VCVTTSH
    UINT64_C(4088792576),	// VCVTf2h
    UINT64_C(4089120512),	// VCVTf2sd
    UINT64_C(4089120576),	// VCVTf2sq
    UINT64_C(4089120640),	// VCVTf2ud
    UINT64_C(4089120704),	// VCVTf2uq
    UINT64_C(4068478736),	// VCVTf2xsd
    UINT64_C(4068478800),	// VCVTf2xsq
    UINT64_C(4085255952),	// VCVTf2xud
    UINT64_C(4085256016),	// VCVTf2xuq
    UINT64_C(4088792832),	// VCVTh2f
    UINT64_C(4088858368),	// VCVTh2sd
    UINT64_C(4088858432),	// VCVTh2sq
    UINT64_C(4088858496),	// VCVTh2ud
    UINT64_C(4088858560),	// VCVTh2uq
    UINT64_C(4068478224),	// VCVTh2xsd
    UINT64_C(4068478288),	// VCVTh2xsq
    UINT64_C(4085255440),	// VCVTh2xud
    UINT64_C(4085255504),	// VCVTh2xuq
    UINT64_C(4089120256),	// VCVTs2fd
    UINT64_C(4089120320),	// VCVTs2fq
    UINT64_C(4088858112),	// VCVTs2hd
    UINT64_C(4088858176),	// VCVTs2hq
    UINT64_C(4089120384),	// VCVTu2fd
    UINT64_C(4089120448),	// VCVTu2fq
    UINT64_C(4088858240),	// VCVTu2hd
    UINT64_C(4088858304),	// VCVTu2hq
    UINT64_C(4068478480),	// VCVTxs2fd
    UINT64_C(4068478544),	// VCVTxs2fq
    UINT64_C(4068477968),	// VCVTxs2hd
    UINT64_C(4068478032),	// VCVTxs2hq
    UINT64_C(4085255696),	// VCVTxu2fd
    UINT64_C(4085255760),	// VCVTxu2fq
    UINT64_C(4085255184),	// VCVTxu2hd
    UINT64_C(4085255248),	// VCVTxu2hq
    UINT64_C(243272448),	// VDIVD
    UINT64_C(243271936),	// VDIVH
    UINT64_C(243272192),	// VDIVS
    UINT64_C(243272496),	// VDUP16d
    UINT64_C(245369648),	// VDUP16q
    UINT64_C(243272464),	// VDUP32d
    UINT64_C(245369616),	// VDUP32q
    UINT64_C(247466768),	// VDUP8d
    UINT64_C(249563920),	// VDUP8q
    UINT64_C(4088531968),	// VDUPLN16d
    UINT64_C(4088532032),	// VDUPLN16q
    UINT64_C(4088663040),	// VDUPLN32d
    UINT64_C(4088663104),	// VDUPLN32q
    UINT64_C(4088466432),	// VDUPLN8d
    UINT64_C(4088466496),	// VDUPLN8q
    UINT64_C(4076863760),	// VEORd
    UINT64_C(4076863824),	// VEORq
    UINT64_C(4071620608),	// VEXTd16
    UINT64_C(4071620608),	// VEXTd32
    UINT64_C(4071620608),	// VEXTd8
    UINT64_C(4071620672),	// VEXTq16
    UINT64_C(4071620672),	// VEXTq32
    UINT64_C(4071620672),	// VEXTq64
    UINT64_C(4071620672),	// VEXTq8
    UINT64_C(245369600),	// VFMAD
    UINT64_C(245369088),	// VFMAH
    UINT64_C(245369344),	// VFMAS
    UINT64_C(4060089360),	// VFMAfd
    UINT64_C(4060089424),	// VFMAfq
    UINT64_C(4061137936),	// VFMAhd
    UINT64_C(4061138000),	// VFMAhq
    UINT64_C(245369664),	// VFMSD
    UINT64_C(245369152),	// VFMSH
    UINT64_C(245369408),	// VFMSS
    UINT64_C(4062186512),	// VFMSfd
    UINT64_C(4062186576),	// VFMSfq
    UINT64_C(4063235088),	// VFMShd
    UINT64_C(4063235152),	// VFMShq
    UINT64_C(244321088),	// VFNMAD
    UINT64_C(244320576),	// VFNMAH
    UINT64_C(244320832),	// VFNMAS
    UINT64_C(244321024),	// VFNMSD
    UINT64_C(244320512),	// VFNMSH
    UINT64_C(244320768),	// VFNMSS
    UINT64_C(235932432),	// VGETLNi32
    UINT64_C(235932464),	// VGETLNs16
    UINT64_C(240126736),	// VGETLNs8
    UINT64_C(244321072),	// VGETLNu16
    UINT64_C(248515344),	// VGETLNu8
    UINT64_C(4060086336),	// VHADDsv16i8
    UINT64_C(4062183424),	// VHADDsv2i32
    UINT64_C(4061134848),	// VHADDsv4i16
    UINT64_C(4062183488),	// VHADDsv4i32
    UINT64_C(4061134912),	// VHADDsv8i16
    UINT64_C(4060086272),	// VHADDsv8i8
    UINT64_C(4076863552),	// VHADDuv16i8
    UINT64_C(4078960640),	// VHADDuv2i32
    UINT64_C(4077912064),	// VHADDuv4i16
    UINT64_C(4078960704),	// VHADDuv4i32
    UINT64_C(4077912128),	// VHADDuv8i16
    UINT64_C(4076863488),	// VHADDuv8i8
    UINT64_C(4060086848),	// VHSUBsv16i8
    UINT64_C(4062183936),	// VHSUBsv2i32
    UINT64_C(4061135360),	// VHSUBsv4i16
    UINT64_C(4062184000),	// VHSUBsv4i32
    UINT64_C(4061135424),	// VHSUBsv8i16
    UINT64_C(4060086784),	// VHSUBsv8i8
    UINT64_C(4076864064),	// VHSUBuv16i8
    UINT64_C(4078961152),	// VHSUBuv2i32
    UINT64_C(4077912576),	// VHSUBuv4i16
    UINT64_C(4078961216),	// VHSUBuv4i32
    UINT64_C(4077912640),	// VHSUBuv8i16
    UINT64_C(4076864000),	// VHSUBuv8i8
    UINT64_C(4272949952),	// VINSH
    UINT64_C(247008192),	// VJCVT
    UINT64_C(4104129615),	// VLD1DUPd16
    UINT64_C(4104129613),	// VLD1DUPd16wb_fixed
    UINT64_C(4104129600),	// VLD1DUPd16wb_register
    UINT64_C(4104129679),	// VLD1DUPd32
    UINT64_C(4104129677),	// VLD1DUPd32wb_fixed
    UINT64_C(4104129664),	// VLD1DUPd32wb_register
    UINT64_C(4104129551),	// VLD1DUPd8
    UINT64_C(4104129549),	// VLD1DUPd8wb_fixed
    UINT64_C(4104129536),	// VLD1DUPd8wb_register
    UINT64_C(4104129647),	// VLD1DUPq16
    UINT64_C(4104129645),	// VLD1DUPq16wb_fixed
    UINT64_C(4104129632),	// VLD1DUPq16wb_register
    UINT64_C(4104129711),	// VLD1DUPq32
    UINT64_C(4104129709),	// VLD1DUPq32wb_fixed
    UINT64_C(4104129696),	// VLD1DUPq32wb_register
    UINT64_C(4104129583),	// VLD1DUPq8
    UINT64_C(4104129581),	// VLD1DUPq8wb_fixed
    UINT64_C(4104129568),	// VLD1DUPq8wb_register
    UINT64_C(4104127503),	// VLD1LNd16
    UINT64_C(4104127488),	// VLD1LNd16_UPD
    UINT64_C(4104128527),	// VLD1LNd32
    UINT64_C(4104128512),	// VLD1LNd32_UPD
    UINT64_C(4104126479),	// VLD1LNd8
    UINT64_C(4104126464),	// VLD1LNd8_UPD
    UINT64_C(0),	// VLD1LNq16Pseudo
    UINT64_C(0),	// VLD1LNq16Pseudo_UPD
    UINT64_C(0),	// VLD1LNq32Pseudo
    UINT64_C(0),	// VLD1LNq32Pseudo_UPD
    UINT64_C(0),	// VLD1LNq8Pseudo
    UINT64_C(0),	// VLD1LNq8Pseudo_UPD
    UINT64_C(4095739727),	// VLD1d16
    UINT64_C(4095738447),	// VLD1d16Q
    UINT64_C(0),	// VLD1d16QPseudo
    UINT64_C(4095738445),	// VLD1d16Qwb_fixed
    UINT64_C(4095738432),	// VLD1d16Qwb_register
    UINT64_C(4095739471),	// VLD1d16T
    UINT64_C(0),	// VLD1d16TPseudo
    UINT64_C(4095739469),	// VLD1d16Twb_fixed
    UINT64_C(4095739456),	// VLD1d16Twb_register
    UINT64_C(4095739725),	// VLD1d16wb_fixed
    UINT64_C(4095739712),	// VLD1d16wb_register
    UINT64_C(4095739791),	// VLD1d32
    UINT64_C(4095738511),	// VLD1d32Q
    UINT64_C(0),	// VLD1d32QPseudo
    UINT64_C(4095738509),	// VLD1d32Qwb_fixed
    UINT64_C(4095738496),	// VLD1d32Qwb_register
    UINT64_C(4095739535),	// VLD1d32T
    UINT64_C(0),	// VLD1d32TPseudo
    UINT64_C(4095739533),	// VLD1d32Twb_fixed
    UINT64_C(4095739520),	// VLD1d32Twb_register
    UINT64_C(4095739789),	// VLD1d32wb_fixed
    UINT64_C(4095739776),	// VLD1d32wb_register
    UINT64_C(4095739855),	// VLD1d64
    UINT64_C(4095738575),	// VLD1d64Q
    UINT64_C(0),	// VLD1d64QPseudo
    UINT64_C(0),	// VLD1d64QPseudoWB_fixed
    UINT64_C(0),	// VLD1d64QPseudoWB_register
    UINT64_C(4095738573),	// VLD1d64Qwb_fixed
    UINT64_C(4095738560),	// VLD1d64Qwb_register
    UINT64_C(4095739599),	// VLD1d64T
    UINT64_C(0),	// VLD1d64TPseudo
    UINT64_C(0),	// VLD1d64TPseudoWB_fixed
    UINT64_C(0),	// VLD1d64TPseudoWB_register
    UINT64_C(4095739597),	// VLD1d64Twb_fixed
    UINT64_C(4095739584),	// VLD1d64Twb_register
    UINT64_C(4095739853),	// VLD1d64wb_fixed
    UINT64_C(4095739840),	// VLD1d64wb_register
    UINT64_C(4095739663),	// VLD1d8
    UINT64_C(4095738383),	// VLD1d8Q
    UINT64_C(0),	// VLD1d8QPseudo
    UINT64_C(4095738381),	// VLD1d8Qwb_fixed
    UINT64_C(4095738368),	// VLD1d8Qwb_register
    UINT64_C(4095739407),	// VLD1d8T
    UINT64_C(0),	// VLD1d8TPseudo
    UINT64_C(4095739405),	// VLD1d8Twb_fixed
    UINT64_C(4095739392),	// VLD1d8Twb_register
    UINT64_C(4095739661),	// VLD1d8wb_fixed
    UINT64_C(4095739648),	// VLD1d8wb_register
    UINT64_C(4095740495),	// VLD1q16
    UINT64_C(0),	// VLD1q16HighQPseudo
    UINT64_C(0),	// VLD1q16HighTPseudo
    UINT64_C(0),	// VLD1q16LowQPseudo_UPD
    UINT64_C(0),	// VLD1q16LowTPseudo_UPD
    UINT64_C(4095740493),	// VLD1q16wb_fixed
    UINT64_C(4095740480),	// VLD1q16wb_register
    UINT64_C(4095740559),	// VLD1q32
    UINT64_C(0),	// VLD1q32HighQPseudo
    UINT64_C(0),	// VLD1q32HighTPseudo
    UINT64_C(0),	// VLD1q32LowQPseudo_UPD
    UINT64_C(0),	// VLD1q32LowTPseudo_UPD
    UINT64_C(4095740557),	// VLD1q32wb_fixed
    UINT64_C(4095740544),	// VLD1q32wb_register
    UINT64_C(4095740623),	// VLD1q64
    UINT64_C(0),	// VLD1q64HighQPseudo
    UINT64_C(0),	// VLD1q64HighTPseudo
    UINT64_C(0),	// VLD1q64LowQPseudo_UPD
    UINT64_C(0),	// VLD1q64LowTPseudo_UPD
    UINT64_C(4095740621),	// VLD1q64wb_fixed
    UINT64_C(4095740608),	// VLD1q64wb_register
    UINT64_C(4095740431),	// VLD1q8
    UINT64_C(0),	// VLD1q8HighQPseudo
    UINT64_C(0),	// VLD1q8HighTPseudo
    UINT64_C(0),	// VLD1q8LowQPseudo_UPD
    UINT64_C(0),	// VLD1q8LowTPseudo_UPD
    UINT64_C(4095740429),	// VLD1q8wb_fixed
    UINT64_C(4095740416),	// VLD1q8wb_register
    UINT64_C(4104129871),	// VLD2DUPd16
    UINT64_C(4104129869),	// VLD2DUPd16wb_fixed
    UINT64_C(4104129856),	// VLD2DUPd16wb_register
    UINT64_C(4104129903),	// VLD2DUPd16x2
    UINT64_C(4104129901),	// VLD2DUPd16x2wb_fixed
    UINT64_C(4104129888),	// VLD2DUPd16x2wb_register
    UINT64_C(4104129935),	// VLD2DUPd32
    UINT64_C(4104129933),	// VLD2DUPd32wb_fixed
    UINT64_C(4104129920),	// VLD2DUPd32wb_register
    UINT64_C(4104129967),	// VLD2DUPd32x2
    UINT64_C(4104129965),	// VLD2DUPd32x2wb_fixed
    UINT64_C(4104129952),	// VLD2DUPd32x2wb_register
    UINT64_C(4104129807),	// VLD2DUPd8
    UINT64_C(4104129805),	// VLD2DUPd8wb_fixed
    UINT64_C(4104129792),	// VLD2DUPd8wb_register
    UINT64_C(4104129839),	// VLD2DUPd8x2
    UINT64_C(4104129837),	// VLD2DUPd8x2wb_fixed
    UINT64_C(4104129824),	// VLD2DUPd8x2wb_register
    UINT64_C(0),	// VLD2DUPq16EvenPseudo
    UINT64_C(0),	// VLD2DUPq16OddPseudo
    UINT64_C(0),	// VLD2DUPq32EvenPseudo
    UINT64_C(0),	// VLD2DUPq32OddPseudo
    UINT64_C(0),	// VLD2DUPq8EvenPseudo
    UINT64_C(0),	// VLD2DUPq8OddPseudo
    UINT64_C(4104127759),	// VLD2LNd16
    UINT64_C(0),	// VLD2LNd16Pseudo
    UINT64_C(0),	// VLD2LNd16Pseudo_UPD
    UINT64_C(4104127744),	// VLD2LNd16_UPD
    UINT64_C(4104128783),	// VLD2LNd32
    UINT64_C(0),	// VLD2LNd32Pseudo
    UINT64_C(0),	// VLD2LNd32Pseudo_UPD
    UINT64_C(4104128768),	// VLD2LNd32_UPD
    UINT64_C(4104126735),	// VLD2LNd8
    UINT64_C(0),	// VLD2LNd8Pseudo
    UINT64_C(0),	// VLD2LNd8Pseudo_UPD
    UINT64_C(4104126720),	// VLD2LNd8_UPD
    UINT64_C(4104127791),	// VLD2LNq16
    UINT64_C(0),	// VLD2LNq16Pseudo
    UINT64_C(0),	// VLD2LNq16Pseudo_UPD
    UINT64_C(4104127776),	// VLD2LNq16_UPD
    UINT64_C(4104128847),	// VLD2LNq32
    UINT64_C(0),	// VLD2LNq32Pseudo
    UINT64_C(0),	// VLD2LNq32Pseudo_UPD
    UINT64_C(4104128832),	// VLD2LNq32_UPD
    UINT64_C(4095740239),	// VLD2b16
    UINT64_C(4095740237),	// VLD2b16wb_fixed
    UINT64_C(4095740224),	// VLD2b16wb_register
    UINT64_C(4095740303),	// VLD2b32
    UINT64_C(4095740301),	// VLD2b32wb_fixed
    UINT64_C(4095740288),	// VLD2b32wb_register
    UINT64_C(4095740175),	// VLD2b8
    UINT64_C(4095740173),	// VLD2b8wb_fixed
    UINT64_C(4095740160),	// VLD2b8wb_register
    UINT64_C(4095739983),	// VLD2d16
    UINT64_C(4095739981),	// VLD2d16wb_fixed
    UINT64_C(4095739968),	// VLD2d16wb_register
    UINT64_C(4095740047),	// VLD2d32
    UINT64_C(4095740045),	// VLD2d32wb_fixed
    UINT64_C(4095740032),	// VLD2d32wb_register
    UINT64_C(4095739919),	// VLD2d8
    UINT64_C(4095739917),	// VLD2d8wb_fixed
    UINT64_C(4095739904),	// VLD2d8wb_register
    UINT64_C(4095738703),	// VLD2q16
    UINT64_C(0),	// VLD2q16Pseudo
    UINT64_C(0),	// VLD2q16PseudoWB_fixed
    UINT64_C(0),	// VLD2q16PseudoWB_register
    UINT64_C(4095738701),	// VLD2q16wb_fixed
    UINT64_C(4095738688),	// VLD2q16wb_register
    UINT64_C(4095738767),	// VLD2q32
    UINT64_C(0),	// VLD2q32Pseudo
    UINT64_C(0),	// VLD2q32PseudoWB_fixed
    UINT64_C(0),	// VLD2q32PseudoWB_register
    UINT64_C(4095738765),	// VLD2q32wb_fixed
    UINT64_C(4095738752),	// VLD2q32wb_register
    UINT64_C(4095738639),	// VLD2q8
    UINT64_C(0),	// VLD2q8Pseudo
    UINT64_C(0),	// VLD2q8PseudoWB_fixed
    UINT64_C(0),	// VLD2q8PseudoWB_register
    UINT64_C(4095738637),	// VLD2q8wb_fixed
    UINT64_C(4095738624),	// VLD2q8wb_register
    UINT64_C(4104130127),	// VLD3DUPd16
    UINT64_C(0),	// VLD3DUPd16Pseudo
    UINT64_C(0),	// VLD3DUPd16Pseudo_UPD
    UINT64_C(4104130112),	// VLD3DUPd16_UPD
    UINT64_C(4104130191),	// VLD3DUPd32
    UINT64_C(0),	// VLD3DUPd32Pseudo
    UINT64_C(0),	// VLD3DUPd32Pseudo_UPD
    UINT64_C(4104130176),	// VLD3DUPd32_UPD
    UINT64_C(4104130063),	// VLD3DUPd8
    UINT64_C(0),	// VLD3DUPd8Pseudo
    UINT64_C(0),	// VLD3DUPd8Pseudo_UPD
    UINT64_C(4104130048),	// VLD3DUPd8_UPD
    UINT64_C(4104130159),	// VLD3DUPq16
    UINT64_C(0),	// VLD3DUPq16EvenPseudo
    UINT64_C(0),	// VLD3DUPq16OddPseudo
    UINT64_C(4104130144),	// VLD3DUPq16_UPD
    UINT64_C(4104130223),	// VLD3DUPq32
    UINT64_C(0),	// VLD3DUPq32EvenPseudo
    UINT64_C(0),	// VLD3DUPq32OddPseudo
    UINT64_C(4104130208),	// VLD3DUPq32_UPD
    UINT64_C(4104130095),	// VLD3DUPq8
    UINT64_C(0),	// VLD3DUPq8EvenPseudo
    UINT64_C(0),	// VLD3DUPq8OddPseudo
    UINT64_C(4104130080),	// VLD3DUPq8_UPD
    UINT64_C(4104128015),	// VLD3LNd16
    UINT64_C(0),	// VLD3LNd16Pseudo
    UINT64_C(0),	// VLD3LNd16Pseudo_UPD
    UINT64_C(4104128000),	// VLD3LNd16_UPD
    UINT64_C(4104129039),	// VLD3LNd32
    UINT64_C(0),	// VLD3LNd32Pseudo
    UINT64_C(0),	// VLD3LNd32Pseudo_UPD
    UINT64_C(4104129024),	// VLD3LNd32_UPD
    UINT64_C(4104126991),	// VLD3LNd8
    UINT64_C(0),	// VLD3LNd8Pseudo
    UINT64_C(0),	// VLD3LNd8Pseudo_UPD
    UINT64_C(4104126976),	// VLD3LNd8_UPD
    UINT64_C(4104128047),	// VLD3LNq16
    UINT64_C(0),	// VLD3LNq16Pseudo
    UINT64_C(0),	// VLD3LNq16Pseudo_UPD
    UINT64_C(4104128032),	// VLD3LNq16_UPD
    UINT64_C(4104129103),	// VLD3LNq32
    UINT64_C(0),	// VLD3LNq32Pseudo
    UINT64_C(0),	// VLD3LNq32Pseudo_UPD
    UINT64_C(4104129088),	// VLD3LNq32_UPD
    UINT64_C(4095738959),	// VLD3d16
    UINT64_C(0),	// VLD3d16Pseudo
    UINT64_C(0),	// VLD3d16Pseudo_UPD
    UINT64_C(4095738944),	// VLD3d16_UPD
    UINT64_C(4095739023),	// VLD3d32
    UINT64_C(0),	// VLD3d32Pseudo
    UINT64_C(0),	// VLD3d32Pseudo_UPD
    UINT64_C(4095739008),	// VLD3d32_UPD
    UINT64_C(4095738895),	// VLD3d8
    UINT64_C(0),	// VLD3d8Pseudo
    UINT64_C(0),	// VLD3d8Pseudo_UPD
    UINT64_C(4095738880),	// VLD3d8_UPD
    UINT64_C(4095739215),	// VLD3q16
    UINT64_C(0),	// VLD3q16Pseudo_UPD
    UINT64_C(4095739200),	// VLD3q16_UPD
    UINT64_C(0),	// VLD3q16oddPseudo
    UINT64_C(0),	// VLD3q16oddPseudo_UPD
    UINT64_C(4095739279),	// VLD3q32
    UINT64_C(0),	// VLD3q32Pseudo_UPD
    UINT64_C(4095739264),	// VLD3q32_UPD
    UINT64_C(0),	// VLD3q32oddPseudo
    UINT64_C(0),	// VLD3q32oddPseudo_UPD
    UINT64_C(4095739151),	// VLD3q8
    UINT64_C(0),	// VLD3q8Pseudo_UPD
    UINT64_C(4095739136),	// VLD3q8_UPD
    UINT64_C(0),	// VLD3q8oddPseudo
    UINT64_C(0),	// VLD3q8oddPseudo_UPD
    UINT64_C(4104130383),	// VLD4DUPd16
    UINT64_C(0),	// VLD4DUPd16Pseudo
    UINT64_C(0),	// VLD4DUPd16Pseudo_UPD
    UINT64_C(4104130368),	// VLD4DUPd16_UPD
    UINT64_C(4104130447),	// VLD4DUPd32
    UINT64_C(0),	// VLD4DUPd32Pseudo
    UINT64_C(0),	// VLD4DUPd32Pseudo_UPD
    UINT64_C(4104130432),	// VLD4DUPd32_UPD
    UINT64_C(4104130319),	// VLD4DUPd8
    UINT64_C(0),	// VLD4DUPd8Pseudo
    UINT64_C(0),	// VLD4DUPd8Pseudo_UPD
    UINT64_C(4104130304),	// VLD4DUPd8_UPD
    UINT64_C(4104130415),	// VLD4DUPq16
    UINT64_C(0),	// VLD4DUPq16EvenPseudo
    UINT64_C(0),	// VLD4DUPq16OddPseudo
    UINT64_C(4104130400),	// VLD4DUPq16_UPD
    UINT64_C(4104130479),	// VLD4DUPq32
    UINT64_C(0),	// VLD4DUPq32EvenPseudo
    UINT64_C(0),	// VLD4DUPq32OddPseudo
    UINT64_C(4104130464),	// VLD4DUPq32_UPD
    UINT64_C(4104130351),	// VLD4DUPq8
    UINT64_C(0),	// VLD4DUPq8EvenPseudo
    UINT64_C(0),	// VLD4DUPq8OddPseudo
    UINT64_C(4104130336),	// VLD4DUPq8_UPD
    UINT64_C(4104128271),	// VLD4LNd16
    UINT64_C(0),	// VLD4LNd16Pseudo
    UINT64_C(0),	// VLD4LNd16Pseudo_UPD
    UINT64_C(4104128256),	// VLD4LNd16_UPD
    UINT64_C(4104129295),	// VLD4LNd32
    UINT64_C(0),	// VLD4LNd32Pseudo
    UINT64_C(0),	// VLD4LNd32Pseudo_UPD
    UINT64_C(4104129280),	// VLD4LNd32_UPD
    UINT64_C(4104127247),	// VLD4LNd8
    UINT64_C(0),	// VLD4LNd8Pseudo
    UINT64_C(0),	// VLD4LNd8Pseudo_UPD
    UINT64_C(4104127232),	// VLD4LNd8_UPD
    UINT64_C(4104128303),	// VLD4LNq16
    UINT64_C(0),	// VLD4LNq16Pseudo
    UINT64_C(0),	// VLD4LNq16Pseudo_UPD
    UINT64_C(4104128288),	// VLD4LNq16_UPD
    UINT64_C(4104129359),	// VLD4LNq32
    UINT64_C(0),	// VLD4LNq32Pseudo
    UINT64_C(0),	// VLD4LNq32Pseudo_UPD
    UINT64_C(4104129344),	// VLD4LNq32_UPD
    UINT64_C(4095737935),	// VLD4d16
    UINT64_C(0),	// VLD4d16Pseudo
    UINT64_C(0),	// VLD4d16Pseudo_UPD
    UINT64_C(4095737920),	// VLD4d16_UPD
    UINT64_C(4095737999),	// VLD4d32
    UINT64_C(0),	// VLD4d32Pseudo
    UINT64_C(0),	// VLD4d32Pseudo_UPD
    UINT64_C(4095737984),	// VLD4d32_UPD
    UINT64_C(4095737871),	// VLD4d8
    UINT64_C(0),	// VLD4d8Pseudo
    UINT64_C(0),	// VLD4d8Pseudo_UPD
    UINT64_C(4095737856),	// VLD4d8_UPD
    UINT64_C(4095738191),	// VLD4q16
    UINT64_C(0),	// VLD4q16Pseudo_UPD
    UINT64_C(4095738176),	// VLD4q16_UPD
    UINT64_C(0),	// VLD4q16oddPseudo
    UINT64_C(0),	// VLD4q16oddPseudo_UPD
    UINT64_C(4095738255),	// VLD4q32
    UINT64_C(0),	// VLD4q32Pseudo_UPD
    UINT64_C(4095738240),	// VLD4q32_UPD
    UINT64_C(0),	// VLD4q32oddPseudo
    UINT64_C(0),	// VLD4q32oddPseudo_UPD
    UINT64_C(4095738127),	// VLD4q8
    UINT64_C(0),	// VLD4q8Pseudo_UPD
    UINT64_C(4095738112),	// VLD4q8_UPD
    UINT64_C(0),	// VLD4q8oddPseudo
    UINT64_C(0),	// VLD4q8oddPseudo_UPD
    UINT64_C(221252352),	// VLDMDDB_UPD
    UINT64_C(210766592),	// VLDMDIA
    UINT64_C(212863744),	// VLDMDIA_UPD
    UINT64_C(0),	// VLDMQIA
    UINT64_C(221252096),	// VLDMSDB_UPD
    UINT64_C(210766336),	// VLDMSIA
    UINT64_C(212863488),	// VLDMSIA_UPD
    UINT64_C(219155200),	// VLDRD
    UINT64_C(219154688),	// VLDRH
    UINT64_C(219154944),	// VLDRS
    UINT64_C(204474880),	// VLLDM
    UINT64_C(203426304),	// VLSTM
    UINT64_C(4269804288),	// VMAXNMD
    UINT64_C(4269803776),	// VMAXNMH
    UINT64_C(4076867344),	// VMAXNMNDf
    UINT64_C(4077915920),	// VMAXNMNDh
    UINT64_C(4076867408),	// VMAXNMNQf
    UINT64_C(4077915984),	// VMAXNMNQh
    UINT64_C(4269804032),	// VMAXNMS
    UINT64_C(4060090112),	// VMAXfd
    UINT64_C(4060090176),	// VMAXfq
    UINT64_C(4061138688),	// VMAXhd
    UINT64_C(4061138752),	// VMAXhq
    UINT64_C(4060087872),	// VMAXsv16i8
    UINT64_C(4062184960),	// VMAXsv2i32
    UINT64_C(4061136384),	// VMAXsv4i16
    UINT64_C(4062185024),	// VMAXsv4i32
    UINT64_C(4061136448),	// VMAXsv8i16
    UINT64_C(4060087808),	// VMAXsv8i8
    UINT64_C(4076865088),	// VMAXuv16i8
    UINT64_C(4078962176),	// VMAXuv2i32
    UINT64_C(4077913600),	// VMAXuv4i16
    UINT64_C(4078962240),	// VMAXuv4i32
    UINT64_C(4077913664),	// VMAXuv8i16
    UINT64_C(4076865024),	// VMAXuv8i8
    UINT64_C(4269804352),	// VMINNMD
    UINT64_C(4269803840),	// VMINNMH
    UINT64_C(4078964496),	// VMINNMNDf
    UINT64_C(4080013072),	// VMINNMNDh
    UINT64_C(4078964560),	// VMINNMNQf
    UINT64_C(4080013136),	// VMINNMNQh
    UINT64_C(4269804096),	// VMINNMS
    UINT64_C(4062187264),	// VMINfd
    UINT64_C(4062187328),	// VMINfq
    UINT64_C(4063235840),	// VMINhd
    UINT64_C(4063235904),	// VMINhq
    UINT64_C(4060087888),	// VMINsv16i8
    UINT64_C(4062184976),	// VMINsv2i32
    UINT64_C(4061136400),	// VMINsv4i16
    UINT64_C(4062185040),	// VMINsv4i32
    UINT64_C(4061136464),	// VMINsv8i16
    UINT64_C(4060087824),	// VMINsv8i8
    UINT64_C(4076865104),	// VMINuv16i8
    UINT64_C(4078962192),	// VMINuv2i32
    UINT64_C(4077913616),	// VMINuv4i16
    UINT64_C(4078962256),	// VMINuv4i32
    UINT64_C(4077913680),	// VMINuv8i16
    UINT64_C(4076865040),	// VMINuv8i8
    UINT64_C(234883840),	// VMLAD
    UINT64_C(234883328),	// VMLAH
    UINT64_C(4070572608),	// VMLALslsv2i32
    UINT64_C(4069524032),	// VMLALslsv4i16
    UINT64_C(4087349824),	// VMLALsluv2i32
    UINT64_C(4086301248),	// VMLALsluv4i16
    UINT64_C(4070574080),	// VMLALsv2i64
    UINT64_C(4069525504),	// VMLALsv4i32
    UINT64_C(4068476928),	// VMLALsv8i16
    UINT64_C(4087351296),	// VMLALuv2i64
    UINT64_C(4086302720),	// VMLALuv4i32
    UINT64_C(4085254144),	// VMLALuv8i16
    UINT64_C(234883584),	// VMLAS
    UINT64_C(4060089616),	// VMLAfd
    UINT64_C(4060089680),	// VMLAfq
    UINT64_C(4061138192),	// VMLAhd
    UINT64_C(4061138256),	// VMLAhq
    UINT64_C(4070572352),	// VMLAslfd
    UINT64_C(4087349568),	// VMLAslfq
    UINT64_C(4069523776),	// VMLAslhd
    UINT64_C(4086300992),	// VMLAslhq
    UINT64_C(4070572096),	// VMLAslv2i32
    UINT64_C(4069523520),	// VMLAslv4i16
    UINT64_C(4087349312),	// VMLAslv4i32
    UINT64_C(4086300736),	// VMLAslv8i16
    UINT64_C(4060088640),	// VMLAv16i8
    UINT64_C(4062185728),	// VMLAv2i32
    UINT64_C(4061137152),	// VMLAv4i16
    UINT64_C(4062185792),	// VMLAv4i32
    UINT64_C(4061137216),	// VMLAv8i16
    UINT64_C(4060088576),	// VMLAv8i8
    UINT64_C(234883904),	// VMLSD
    UINT64_C(234883392),	// VMLSH
    UINT64_C(4070573632),	// VMLSLslsv2i32
    UINT64_C(4069525056),	// VMLSLslsv4i16
    UINT64_C(4087350848),	// VMLSLsluv2i32
    UINT64_C(4086302272),	// VMLSLsluv4i16
    UINT64_C(4070574592),	// VMLSLsv2i64
    UINT64_C(4069526016),	// VMLSLsv4i32
    UINT64_C(4068477440),	// VMLSLsv8i16
    UINT64_C(4087351808),	// VMLSLuv2i64
    UINT64_C(4086303232),	// VMLSLuv4i32
    UINT64_C(4085254656),	// VMLSLuv8i16
    UINT64_C(234883648),	// VMLSS
    UINT64_C(4062186768),	// VMLSfd
    UINT64_C(4062186832),	// VMLSfq
    UINT64_C(4063235344),	// VMLShd
    UINT64_C(4063235408),	// VMLShq
    UINT64_C(4070573376),	// VMLSslfd
    UINT64_C(4087350592),	// VMLSslfq
    UINT64_C(4069524800),	// VMLSslhd
    UINT64_C(4086302016),	// VMLSslhq
    UINT64_C(4070573120),	// VMLSslv2i32
    UINT64_C(4069524544),	// VMLSslv4i16
    UINT64_C(4087350336),	// VMLSslv4i32
    UINT64_C(4086301760),	// VMLSslv8i16
    UINT64_C(4076865856),	// VMLSv16i8
    UINT64_C(4078962944),	// VMLSv2i32
    UINT64_C(4077914368),	// VMLSv4i16
    UINT64_C(4078963008),	// VMLSv4i32
    UINT64_C(4077914432),	// VMLSv8i16
    UINT64_C(4076865792),	// VMLSv8i8
    UINT64_C(246418240),	// VMOVD
    UINT64_C(205523728),	// VMOVDRR
    UINT64_C(4272949824),	// VMOVH
    UINT64_C(234883344),	// VMOVHR
    UINT64_C(4070574608),	// VMOVLsv2i64
    UINT64_C(4069526032),	// VMOVLsv4i32
    UINT64_C(4069001744),	// VMOVLsv8i16
    UINT64_C(4087351824),	// VMOVLuv2i64
    UINT64_C(4086303248),	// VMOVLuv4i32
    UINT64_C(4085778960),	// VMOVLuv8i16
    UINT64_C(4089053696),	// VMOVNv2i32
    UINT64_C(4088791552),	// VMOVNv4i16
    UINT64_C(4088529408),	// VMOVNv8i8
    UINT64_C(235931920),	// VMOVRH
    UINT64_C(206572304),	// VMOVRRD
    UINT64_C(206572048),	// VMOVRRS
    UINT64_C(235932176),	// VMOVRS
    UINT64_C(246417984),	// VMOVS
    UINT64_C(234883600),	// VMOVSR
    UINT64_C(205523472),	// VMOVSRR
    UINT64_C(4068478544),	// VMOVv16i8
    UINT64_C(4068478512),	// VMOVv1i64
    UINT64_C(4068478736),	// VMOVv2f32
    UINT64_C(4068474896),	// VMOVv2i32
    UINT64_C(4068478576),	// VMOVv2i64
    UINT64_C(4068478800),	// VMOVv4f32
    UINT64_C(4068476944),	// VMOVv4i16
    UINT64_C(4068474960),	// VMOVv4i32
    UINT64_C(4068477008),	// VMOVv8i16
    UINT64_C(4068478480),	// VMOVv8i8
    UINT64_C(250677776),	// VMRS
    UINT64_C(251136528),	// VMRS_FPEXC
    UINT64_C(251202064),	// VMRS_FPINST
    UINT64_C(251267600),	// VMRS_FPINST2
    UINT64_C(250612240),	// VMRS_FPSID
    UINT64_C(251070992),	// VMRS_MVFR0
    UINT64_C(251005456),	// VMRS_MVFR1
    UINT64_C(250939920),	// VMRS_MVFR2
    UINT64_C(249629200),	// VMSR
    UINT64_C(250087952),	// VMSR_FPEXC
    UINT64_C(250153488),	// VMSR_FPINST
    UINT64_C(250219024),	// VMSR_FPINST2
    UINT64_C(249563664),	// VMSR_FPSID
    UINT64_C(236980992),	// VMULD
    UINT64_C(236980480),	// VMULH
    UINT64_C(4070575616),	// VMULLp64
    UINT64_C(4068478464),	// VMULLp8
    UINT64_C(4070574656),	// VMULLslsv2i32
    UINT64_C(4069526080),	// VMULLslsv4i16
    UINT64_C(4087351872),	// VMULLsluv2i32
    UINT64_C(4086303296),	// VMULLsluv4i16
    UINT64_C(4070575104),	// VMULLsv2i64
    UINT64_C(4069526528),	// VMULLsv4i32
    UINT64_C(4068477952),	// VMULLsv8i16
    UINT64_C(4087352320),	// VMULLuv2i64
    UINT64_C(4086303744),	// VMULLuv4i32
    UINT64_C(4085255168),	// VMULLuv8i16
    UINT64_C(236980736),	// VMULS
    UINT64_C(4076866832),	// VMULfd
    UINT64_C(4076866896),	// VMULfq
    UINT64_C(4077915408),	// VMULhd
    UINT64_C(4077915472),	// VMULhq
    UINT64_C(4076865808),	// VMULpd
    UINT64_C(4076865872),	// VMULpq
    UINT64_C(4070574400),	// VMULslfd
    UINT64_C(4087351616),	// VMULslfq
    UINT64_C(4069525824),	// VMULslhd
    UINT64_C(4086303040),	// VMULslhq
    UINT64_C(4070574144),	// VMULslv2i32
    UINT64_C(4069525568),	// VMULslv4i16
    UINT64_C(4087351360),	// VMULslv4i32
    UINT64_C(4086302784),	// VMULslv8i16
    UINT64_C(4060088656),	// VMULv16i8
    UINT64_C(4062185744),	// VMULv2i32
    UINT64_C(4061137168),	// VMULv4i16
    UINT64_C(4062185808),	// VMULv4i32
    UINT64_C(4061137232),	// VMULv8i16
    UINT64_C(4060088592),	// VMULv8i8
    UINT64_C(4088399232),	// VMVNd
    UINT64_C(4088399296),	// VMVNq
    UINT64_C(4068474928),	// VMVNv2i32
    UINT64_C(4068476976),	// VMVNv4i16
    UINT64_C(4068474992),	// VMVNv4i32
    UINT64_C(4068477040),	// VMVNv8i16
    UINT64_C(246483776),	// VNEGD
    UINT64_C(246483264),	// VNEGH
    UINT64_C(246483520),	// VNEGS
    UINT64_C(4088989632),	// VNEGf32q
    UINT64_C(4088989568),	// VNEGfd
    UINT64_C(4088727424),	// VNEGhd
    UINT64_C(4088727488),	// VNEGhq
    UINT64_C(4088726400),	// VNEGs16d
    UINT64_C(4088726464),	// VNEGs16q
    UINT64_C(4088988544),	// VNEGs32d
    UINT64_C(4088988608),	// VNEGs32q
    UINT64_C(4088464256),	// VNEGs8d
    UINT64_C(4088464320),	// VNEGs8q
    UINT64_C(235932480),	// VNMLAD
    UINT64_C(235931968),	// VNMLAH
    UINT64_C(235932224),	// VNMLAS
    UINT64_C(235932416),	// VNMLSD
    UINT64_C(235931904),	// VNMLSH
    UINT64_C(235932160),	// VNMLSS
    UINT64_C(236981056),	// VNMULD
    UINT64_C(236980544),	// VNMULH
    UINT64_C(236980800),	// VNMULS
    UINT64_C(4063232272),	// VORNd
    UINT64_C(4063232336),	// VORNq
    UINT64_C(4062183696),	// VORRd
    UINT64_C(4068475152),	// VORRiv2i32
    UINT64_C(4068477200),	// VORRiv4i16
    UINT64_C(4068475216),	// VORRiv4i32
    UINT64_C(4068477264),	// VORRiv8i16
    UINT64_C(4062183760),	// VORRq
    UINT64_C(4088399424),	// VPADALsv16i8
    UINT64_C(4088923648),	// VPADALsv2i32
    UINT64_C(4088661504),	// VPADALsv4i16
    UINT64_C(4088923712),	// VPADALsv4i32
    UINT64_C(4088661568),	// VPADALsv8i16
    UINT64_C(4088399360),	// VPADALsv8i8
    UINT64_C(4088399552),	// VPADALuv16i8
    UINT64_C(4088923776),	// VPADALuv2i32
    UINT64_C(4088661632),	// VPADALuv4i16
    UINT64_C(4088923840),	// VPADALuv4i32
    UINT64_C(4088661696),	// VPADALuv8i16
    UINT64_C(4088399488),	// VPADALuv8i8
    UINT64_C(4088398400),	// VPADDLsv16i8
    UINT64_C(4088922624),	// VPADDLsv2i32
    UINT64_C(4088660480),	// VPADDLsv4i16
    UINT64_C(4088922688),	// VPADDLsv4i32
    UINT64_C(4088660544),	// VPADDLsv8i16
    UINT64_C(4088398336),	// VPADDLsv8i8
    UINT64_C(4088398528),	// VPADDLuv16i8
    UINT64_C(4088922752),	// VPADDLuv2i32
    UINT64_C(4088660608),	// VPADDLuv4i16
    UINT64_C(4088922816),	// VPADDLuv4i32
    UINT64_C(4088660672),	// VPADDLuv8i16
    UINT64_C(4088398464),	// VPADDLuv8i8
    UINT64_C(4076866816),	// VPADDf
    UINT64_C(4077915392),	// VPADDh
    UINT64_C(4061137680),	// VPADDi16
    UINT64_C(4062186256),	// VPADDi32
    UINT64_C(4060089104),	// VPADDi8
    UINT64_C(4076867328),	// VPMAXf
    UINT64_C(4077915904),	// VPMAXh
    UINT64_C(4061137408),	// VPMAXs16
    UINT64_C(4062185984),	// VPMAXs32
    UINT64_C(4060088832),	// VPMAXs8
    UINT64_C(4077914624),	// VPMAXu16
    UINT64_C(4078963200),	// VPMAXu32
    UINT64_C(4076866048),	// VPMAXu8
    UINT64_C(4078964480),	// VPMINf
    UINT64_C(4080013056),	// VPMINh
    UINT64_C(4061137424),	// VPMINs16
    UINT64_C(4062186000),	// VPMINs32
    UINT64_C(4060088848),	// VPMINs8
    UINT64_C(4077914640),	// VPMINu16
    UINT64_C(4078963216),	// VPMINu32
    UINT64_C(4076866064),	// VPMINu8
    UINT64_C(4088399680),	// VQABSv16i8
    UINT64_C(4088923904),	// VQABSv2i32
    UINT64_C(4088661760),	// VQABSv4i16
    UINT64_C(4088923968),	// VQABSv4i32
    UINT64_C(4088661824),	// VQABSv8i16
    UINT64_C(4088399616),	// VQABSv8i8
    UINT64_C(4060086352),	// VQADDsv16i8
    UINT64_C(4063232016),	// VQADDsv1i64
    UINT64_C(4062183440),	// VQADDsv2i32
    UINT64_C(4063232080),	// VQADDsv2i64
    UINT64_C(4061134864),	// VQADDsv4i16
    UINT64_C(4062183504),	// VQADDsv4i32
    UINT64_C(4061134928),	// VQADDsv8i16
    UINT64_C(4060086288),	// VQADDsv8i8
    UINT64_C(4076863568),	// VQADDuv16i8
    UINT64_C(4080009232),	// VQADDuv1i64
    UINT64_C(4078960656),	// VQADDuv2i32
    UINT64_C(4080009296),	// VQADDuv2i64
    UINT64_C(4077912080),	// VQADDuv4i16
    UINT64_C(4078960720),	// VQADDuv4i32
    UINT64_C(4077912144),	// VQADDuv8i16
    UINT64_C(4076863504),	// VQADDuv8i8
    UINT64_C(4070572864),	// VQDMLALslv2i32
    UINT64_C(4069524288),	// VQDMLALslv4i16
    UINT64_C(4070574336),	// VQDMLALv2i64
    UINT64_C(4069525760),	// VQDMLALv4i32
    UINT64_C(4070573888),	// VQDMLSLslv2i32
    UINT64_C(4069525312),	// VQDMLSLslv4i16
    UINT64_C(4070574848),	// VQDMLSLv2i64
    UINT64_C(4069526272),	// VQDMLSLv4i32
    UINT64_C(4070575168),	// VQDMULHslv2i32
    UINT64_C(4069526592),	// VQDMULHslv4i16
    UINT64_C(4087352384),	// VQDMULHslv4i32
    UINT64_C(4086303808),	// VQDMULHslv8i16
    UINT64_C(4062186240),	// VQDMULHv2i32
    UINT64_C(4061137664),	// VQDMULHv4i16
    UINT64_C(4062186304),	// VQDMULHv4i32
    UINT64_C(4061137728),	// VQDMULHv8i16
    UINT64_C(4070574912),	// VQDMULLslv2i32
    UINT64_C(4069526336),	// VQDMULLslv4i16
    UINT64_C(4070575360),	// VQDMULLv2i64
    UINT64_C(4069526784),	// VQDMULLv4i32
    UINT64_C(4089053760),	// VQMOVNsuv2i32
    UINT64_C(4088791616),	// VQMOVNsuv4i16
    UINT64_C(4088529472),	// VQMOVNsuv8i8
    UINT64_C(4089053824),	// VQMOVNsv2i32
    UINT64_C(4088791680),	// VQMOVNsv4i16
    UINT64_C(4088529536),	// VQMOVNsv8i8
    UINT64_C(4089053888),	// VQMOVNuv2i32
    UINT64_C(4088791744),	// VQMOVNuv4i16
    UINT64_C(4088529600),	// VQMOVNuv8i8
    UINT64_C(4088399808),	// VQNEGv16i8
    UINT64_C(4088924032),	// VQNEGv2i32
    UINT64_C(4088661888),	// VQNEGv4i16
    UINT64_C(4088924096),	// VQNEGv4i32
    UINT64_C(4088661952),	// VQNEGv8i16
    UINT64_C(4088399744),	// VQNEGv8i8
    UINT64_C(4070575680),	// VQRDMLAHslv2i32
    UINT64_C(4069527104),	// VQRDMLAHslv4i16
    UINT64_C(4087352896),	// VQRDMLAHslv4i32
    UINT64_C(4086304320),	// VQRDMLAHslv8i16
    UINT64_C(4078963472),	// VQRDMLAHv2i32
    UINT64_C(4077914896),	// VQRDMLAHv4i16
    UINT64_C(4078963536),	// VQRDMLAHv4i32
    UINT64_C(4077914960),	// VQRDMLAHv8i16
    UINT64_C(4070575936),	// VQRDMLSHslv2i32
    UINT64_C(4069527360),	// VQRDMLSHslv4i16
    UINT64_C(4087353152),	// VQRDMLSHslv4i32
    UINT64_C(4086304576),	// VQRDMLSHslv8i16
    UINT64_C(4078963728),	// VQRDMLSHv2i32
    UINT64_C(4077915152),	// VQRDMLSHv4i16
    UINT64_C(4078963792),	// VQRDMLSHv4i32
    UINT64_C(4077915216),	// VQRDMLSHv8i16
    UINT64_C(4070575424),	// VQRDMULHslv2i32
    UINT64_C(4069526848),	// VQRDMULHslv4i16
    UINT64_C(4087352640),	// VQRDMULHslv4i32
    UINT64_C(4086304064),	// VQRDMULHslv8i16
    UINT64_C(4078963456),	// VQRDMULHv2i32
    UINT64_C(4077914880),	// VQRDMULHv4i16
    UINT64_C(4078963520),	// VQRDMULHv4i32
    UINT64_C(4077914944),	// VQRDMULHv8i16
    UINT64_C(4060087632),	// VQRSHLsv16i8
    UINT64_C(4063233296),	// VQRSHLsv1i64
    UINT64_C(4062184720),	// VQRSHLsv2i32
    UINT64_C(4063233360),	// VQRSHLsv2i64
    UINT64_C(4061136144),	// VQRSHLsv4i16
    UINT64_C(4062184784),	// VQRSHLsv4i32
    UINT64_C(4061136208),	// VQRSHLsv8i16
    UINT64_C(4060087568),	// VQRSHLsv8i8
    UINT64_C(4076864848),	// VQRSHLuv16i8
    UINT64_C(4080010512),	// VQRSHLuv1i64
    UINT64_C(4078961936),	// VQRSHLuv2i32
    UINT64_C(4080010576),	// VQRSHLuv2i64
    UINT64_C(4077913360),	// VQRSHLuv4i16
    UINT64_C(4078962000),	// VQRSHLuv4i32
    UINT64_C(4077913424),	// VQRSHLuv8i16
    UINT64_C(4076864784),	// VQRSHLuv8i8
    UINT64_C(4070574416),	// VQRSHRNsv2i32
    UINT64_C(4069525840),	// VQRSHRNsv4i16
    UINT64_C(4069001552),	// VQRSHRNsv8i8
    UINT64_C(4087351632),	// VQRSHRNuv2i32
    UINT64_C(4086303056),	// VQRSHRNuv4i16
    UINT64_C(4085778768),	// VQRSHRNuv8i8
    UINT64_C(4087351376),	// VQRSHRUNv2i32
    UINT64_C(4086302800),	// VQRSHRUNv4i16
    UINT64_C(4085778512),	// VQRSHRUNv8i8
    UINT64_C(4069001040),	// VQSHLsiv16i8
    UINT64_C(4068476816),	// VQSHLsiv1i64
    UINT64_C(4070573840),	// VQSHLsiv2i32
    UINT64_C(4068476880),	// VQSHLsiv2i64
    UINT64_C(4069525264),	// VQSHLsiv4i16
    UINT64_C(4070573904),	// VQSHLsiv4i32
    UINT64_C(4069525328),	// VQSHLsiv8i16
    UINT64_C(4069000976),	// VQSHLsiv8i8
    UINT64_C(4085778000),	// VQSHLsuv16i8
    UINT64_C(4085253776),	// VQSHLsuv1i64
    UINT64_C(4087350800),	// VQSHLsuv2i32
    UINT64_C(4085253840),	// VQSHLsuv2i64
    UINT64_C(4086302224),	// VQSHLsuv4i16
    UINT64_C(4087350864),	// VQSHLsuv4i32
    UINT64_C(4086302288),	// VQSHLsuv8i16
    UINT64_C(4085777936),	// VQSHLsuv8i8
    UINT64_C(4060087376),	// VQSHLsv16i8
    UINT64_C(4063233040),	// VQSHLsv1i64
    UINT64_C(4062184464),	// VQSHLsv2i32
    UINT64_C(4063233104),	// VQSHLsv2i64
    UINT64_C(4061135888),	// VQSHLsv4i16
    UINT64_C(4062184528),	// VQSHLsv4i32
    UINT64_C(4061135952),	// VQSHLsv8i16
    UINT64_C(4060087312),	// VQSHLsv8i8
    UINT64_C(4085778256),	// VQSHLuiv16i8
    UINT64_C(4085254032),	// VQSHLuiv1i64
    UINT64_C(4087351056),	// VQSHLuiv2i32
    UINT64_C(4085254096),	// VQSHLuiv2i64
    UINT64_C(4086302480),	// VQSHLuiv4i16
    UINT64_C(4087351120),	// VQSHLuiv4i32
    UINT64_C(4086302544),	// VQSHLuiv8i16
    UINT64_C(4085778192),	// VQSHLuiv8i8
    UINT64_C(4076864592),	// VQSHLuv16i8
    UINT64_C(4080010256),	// VQSHLuv1i64
    UINT64_C(4078961680),	// VQSHLuv2i32
    UINT64_C(4080010320),	// VQSHLuv2i64
    UINT64_C(4077913104),	// VQSHLuv4i16
    UINT64_C(4078961744),	// VQSHLuv4i32
    UINT64_C(4077913168),	// VQSHLuv8i16
    UINT64_C(4076864528),	// VQSHLuv8i8
    UINT64_C(4070574352),	// VQSHRNsv2i32
    UINT64_C(4069525776),	// VQSHRNsv4i16
    UINT64_C(4069001488),	// VQSHRNsv8i8
    UINT64_C(4087351568),	// VQSHRNuv2i32
    UINT64_C(4086302992),	// VQSHRNuv4i16
    UINT64_C(4085778704),	// VQSHRNuv8i8
    UINT64_C(4087351312),	// VQSHRUNv2i32
    UINT64_C(4086302736),	// VQSHRUNv4i16
    UINT64_C(4085778448),	// VQSHRUNv8i8
    UINT64_C(4060086864),	// VQSUBsv16i8
    UINT64_C(4063232528),	// VQSUBsv1i64
    UINT64_C(4062183952),	// VQSUBsv2i32
    UINT64_C(4063232592),	// VQSUBsv2i64
    UINT64_C(4061135376),	// VQSUBsv4i16
    UINT64_C(4062184016),	// VQSUBsv4i32
    UINT64_C(4061135440),	// VQSUBsv8i16
    UINT64_C(4060086800),	// VQSUBsv8i8
    UINT64_C(4076864080),	// VQSUBuv16i8
    UINT64_C(4080009744),	// VQSUBuv1i64
    UINT64_C(4078961168),	// VQSUBuv2i32
    UINT64_C(4080009808),	// VQSUBuv2i64
    UINT64_C(4077912592),	// VQSUBuv4i16
    UINT64_C(4078961232),	// VQSUBuv4i32
    UINT64_C(4077912656),	// VQSUBuv8i16
    UINT64_C(4076864016),	// VQSUBuv8i8
    UINT64_C(4087350272),	// VRADDHNv2i32
    UINT64_C(4086301696),	// VRADDHNv4i16
    UINT64_C(4085253120),	// VRADDHNv8i8
    UINT64_C(4089119744),	// VRECPEd
    UINT64_C(4089120000),	// VRECPEfd
    UINT64_C(4089120064),	// VRECPEfq
    UINT64_C(4088857856),	// VRECPEhd
    UINT64_C(4088857920),	// VRECPEhq
    UINT64_C(4089119808),	// VRECPEq
    UINT64_C(4060090128),	// VRECPSfd
    UINT64_C(4060090192),	// VRECPSfq
    UINT64_C(4061138704),	// VRECPShd
    UINT64_C(4061138768),	// VRECPShq
    UINT64_C(4088398080),	// VREV16d8
    UINT64_C(4088398144),	// VREV16q8
    UINT64_C(4088660096),	// VREV32d16
    UINT64_C(4088397952),	// VREV32d8
    UINT64_C(4088660160),	// VREV32q16
    UINT64_C(4088398016),	// VREV32q8
    UINT64_C(4088659968),	// VREV64d16
    UINT64_C(4088922112),	// VREV64d32
    UINT64_C(4088397824),	// VREV64d8
    UINT64_C(4088660032),	// VREV64q16
    UINT64_C(4088922176),	// VREV64q32
    UINT64_C(4088397888),	// VREV64q8
    UINT64_C(4060086592),	// VRHADDsv16i8
    UINT64_C(4062183680),	// VRHADDsv2i32
    UINT64_C(4061135104),	// VRHADDsv4i16
    UINT64_C(4062183744),	// VRHADDsv4i32
    UINT64_C(4061135168),	// VRHADDsv8i16
    UINT64_C(4060086528),	// VRHADDsv8i8
    UINT64_C(4076863808),	// VRHADDuv16i8
    UINT64_C(4078960896),	// VRHADDuv2i32
    UINT64_C(4077912320),	// VRHADDuv4i16
    UINT64_C(4078960960),	// VRHADDuv4i32
    UINT64_C(4077912384),	// VRHADDuv8i16
    UINT64_C(4076863744),	// VRHADDuv8i8
    UINT64_C(4273474368),	// VRINTAD
    UINT64_C(4273473856),	// VRINTAH
    UINT64_C(4089054464),	// VRINTANDf
    UINT64_C(4088792320),	// VRINTANDh
    UINT64_C(4089054528),	// VRINTANQf
    UINT64_C(4088792384),	// VRINTANQh
    UINT64_C(4273474112),	// VRINTAS
    UINT64_C(4273670976),	// VRINTMD
    UINT64_C(4273670464),	// VRINTMH
    UINT64_C(4089054848),	// VRINTMNDf
    UINT64_C(4088792704),	// VRINTMNDh
    UINT64_C(4089054912),	// VRINTMNQf
    UINT64_C(4088792768),	// VRINTMNQh
    UINT64_C(4273670720),	// VRINTMS
    UINT64_C(4273539904),	// VRINTND
    UINT64_C(4273539392),	// VRINTNH
    UINT64_C(4089054208),	// VRINTNNDf
    UINT64_C(4088792064),	// VRINTNNDh
    UINT64_C(4089054272),	// VRINTNNQf
    UINT64_C(4088792128),	// VRINTNNQh
    UINT64_C(4273539648),	// VRINTNS
    UINT64_C(4273605440),	// VRINTPD
    UINT64_C(4273604928),	// VRINTPH
    UINT64_C(4089055104),	// VRINTPNDf
    UINT64_C(4088792960),	// VRINTPNDh
    UINT64_C(4089055168),	// VRINTPNQf
    UINT64_C(4088793024),	// VRINTPNQh
    UINT64_C(4273605184),	// VRINTPS
    UINT64_C(246811456),	// VRINTRD
    UINT64_C(246810944),	// VRINTRH
    UINT64_C(246811200),	// VRINTRS
    UINT64_C(246876992),	// VRINTXD
    UINT64_C(246876480),	// VRINTXH
    UINT64_C(4089054336),	// VRINTXNDf
    UINT64_C(4088792192),	// VRINTXNDh
    UINT64_C(4089054400),	// VRINTXNQf
    UINT64_C(4088792256),	// VRINTXNQh
    UINT64_C(246876736),	// VRINTXS
    UINT64_C(246811584),	// VRINTZD
    UINT64_C(246811072),	// VRINTZH
    UINT64_C(4089054592),	// VRINTZNDf
    UINT64_C(4088792448),	// VRINTZNDh
    UINT64_C(4089054656),	// VRINTZNQf
    UINT64_C(4088792512),	// VRINTZNQh
    UINT64_C(246811328),	// VRINTZS
    UINT64_C(4060087616),	// VRSHLsv16i8
    UINT64_C(4063233280),	// VRSHLsv1i64
    UINT64_C(4062184704),	// VRSHLsv2i32
    UINT64_C(4063233344),	// VRSHLsv2i64
    UINT64_C(4061136128),	// VRSHLsv4i16
    UINT64_C(4062184768),	// VRSHLsv4i32
    UINT64_C(4061136192),	// VRSHLsv8i16
    UINT64_C(4060087552),	// VRSHLsv8i8
    UINT64_C(4076864832),	// VRSHLuv16i8
    UINT64_C(4080010496),	// VRSHLuv1i64
    UINT64_C(4078961920),	// VRSHLuv2i32
    UINT64_C(4080010560),	// VRSHLuv2i64
    UINT64_C(4077913344),	// VRSHLuv4i16
    UINT64_C(4078961984),	// VRSHLuv4i32
    UINT64_C(4077913408),	// VRSHLuv8i16
    UINT64_C(4076864768),	// VRSHLuv8i8
    UINT64_C(4070574160),	// VRSHRNv2i32
    UINT64_C(4069525584),	// VRSHRNv4i16
    UINT64_C(4069001296),	// VRSHRNv8i8
    UINT64_C(4068999760),	// VRSHRsv16i8
    UINT64_C(4068475536),	// VRSHRsv1i64
    UINT64_C(4070572560),	// VRSHRsv2i32
    UINT64_C(4068475600),	// VRSHRsv2i64
    UINT64_C(4069523984),	// VRSHRsv4i16
    UINT64_C(4070572624),	// VRSHRsv4i32
    UINT64_C(4069524048),	// VRSHRsv8i16
    UINT64_C(4068999696),	// VRSHRsv8i8
    UINT64_C(4085776976),	// VRSHRuv16i8
    UINT64_C(4085252752),	// VRSHRuv1i64
    UINT64_C(4087349776),	// VRSHRuv2i32
    UINT64_C(4085252816),	// VRSHRuv2i64
    UINT64_C(4086301200),	// VRSHRuv4i16
    UINT64_C(4087349840),	// VRSHRuv4i32
    UINT64_C(4086301264),	// VRSHRuv8i16
    UINT64_C(4085776912),	// VRSHRuv8i8
    UINT64_C(4089119872),	// VRSQRTEd
    UINT64_C(4089120128),	// VRSQRTEfd
    UINT64_C(4089120192),	// VRSQRTEfq
    UINT64_C(4088857984),	// VRSQRTEhd
    UINT64_C(4088858048),	// VRSQRTEhq
    UINT64_C(4089119936),	// VRSQRTEq
    UINT64_C(4062187280),	// VRSQRTSfd
    UINT64_C(4062187344),	// VRSQRTSfq
    UINT64_C(4063235856),	// VRSQRTShd
    UINT64_C(4063235920),	// VRSQRTShq
    UINT64_C(4069000016),	// VRSRAsv16i8
    UINT64_C(4068475792),	// VRSRAsv1i64
    UINT64_C(4070572816),	// VRSRAsv2i32
    UINT64_C(4068475856),	// VRSRAsv2i64
    UINT64_C(4069524240),	// VRSRAsv4i16
    UINT64_C(4070572880),	// VRSRAsv4i32
    UINT64_C(4069524304),	// VRSRAsv8i16
    UINT64_C(4068999952),	// VRSRAsv8i8
    UINT64_C(4085777232),	// VRSRAuv16i8
    UINT64_C(4085253008),	// VRSRAuv1i64
    UINT64_C(4087350032),	// VRSRAuv2i32
    UINT64_C(4085253072),	// VRSRAuv2i64
    UINT64_C(4086301456),	// VRSRAuv4i16
    UINT64_C(4087350096),	// VRSRAuv4i32
    UINT64_C(4086301520),	// VRSRAuv8i16
    UINT64_C(4085777168),	// VRSRAuv8i8
    UINT64_C(4087350784),	// VRSUBHNv2i32
    UINT64_C(4086302208),	// VRSUBHNv4i16
    UINT64_C(4085253632),	// VRSUBHNv8i8
    UINT64_C(4229958912),	// VSDOTD
    UINT64_C(4263513344),	// VSDOTDI
    UINT64_C(4229958976),	// VSDOTQ
    UINT64_C(4263513408),	// VSDOTQI
    UINT64_C(4261415680),	// VSELEQD
    UINT64_C(4261415168),	// VSELEQH
    UINT64_C(4261415424),	// VSELEQS
    UINT64_C(4263512832),	// VSELGED
    UINT64_C(4263512320),	// VSELGEH
    UINT64_C(4263512576),	// VSELGES
    UINT64_C(4264561408),	// VSELGTD
    UINT64_C(4264560896),	// VSELGTH
    UINT64_C(4264561152),	// VSELGTS
    UINT64_C(4262464256),	// VSELVSD
    UINT64_C(4262463744),	// VSELVSH
    UINT64_C(4262464000),	// VSELVSS
    UINT64_C(234883888),	// VSETLNi16
    UINT64_C(234883856),	// VSETLNi32
    UINT64_C(239078160),	// VSETLNi8
    UINT64_C(4088791808),	// VSHLLi16
    UINT64_C(4089053952),	// VSHLLi32
    UINT64_C(4088529664),	// VSHLLi8
    UINT64_C(4070574608),	// VSHLLsv2i64
    UINT64_C(4069526032),	// VSHLLsv4i32
    UINT64_C(4069001744),	// VSHLLsv8i16
    UINT64_C(4087351824),	// VSHLLuv2i64
    UINT64_C(4086303248),	// VSHLLuv4i32
    UINT64_C(4085778960),	// VSHLLuv8i16
    UINT64_C(4069000528),	// VSHLiv16i8
    UINT64_C(4068476304),	// VSHLiv1i64
    UINT64_C(4070573328),	// VSHLiv2i32
    UINT64_C(4068476368),	// VSHLiv2i64
    UINT64_C(4069524752),	// VSHLiv4i16
    UINT64_C(4070573392),	// VSHLiv4i32
    UINT64_C(4069524816),	// VSHLiv8i16
    UINT64_C(4069000464),	// VSHLiv8i8
    UINT64_C(4060087360),	// VSHLsv16i8
    UINT64_C(4063233024),	// VSHLsv1i64
    UINT64_C(4062184448),	// VSHLsv2i32
    UINT64_C(4063233088),	// VSHLsv2i64
    UINT64_C(4061135872),	// VSHLsv4i16
    UINT64_C(4062184512),	// VSHLsv4i32
    UINT64_C(4061135936),	// VSHLsv8i16
    UINT64_C(4060087296),	// VSHLsv8i8
    UINT64_C(4076864576),	// VSHLuv16i8
    UINT64_C(4080010240),	// VSHLuv1i64
    UINT64_C(4078961664),	// VSHLuv2i32
    UINT64_C(4080010304),	// VSHLuv2i64
    UINT64_C(4077913088),	// VSHLuv4i16
    UINT64_C(4078961728),	// VSHLuv4i32
    UINT64_C(4077913152),	// VSHLuv8i16
    UINT64_C(4076864512),	// VSHLuv8i8
    UINT64_C(4070574096),	// VSHRNv2i32
    UINT64_C(4069525520),	// VSHRNv4i16
    UINT64_C(4069001232),	// VSHRNv8i8
    UINT64_C(4068999248),	// VSHRsv16i8
    UINT64_C(4068475024),	// VSHRsv1i64
    UINT64_C(4070572048),	// VSHRsv2i32
    UINT64_C(4068475088),	// VSHRsv2i64
    UINT64_C(4069523472),	// VSHRsv4i16
    UINT64_C(4070572112),	// VSHRsv4i32
    UINT64_C(4069523536),	// VSHRsv8i16
    UINT64_C(4068999184),	// VSHRsv8i8
    UINT64_C(4085776464),	// VSHRuv16i8
    UINT64_C(4085252240),	// VSHRuv1i64
    UINT64_C(4087349264),	// VSHRuv2i32
    UINT64_C(4085252304),	// VSHRuv2i64
    UINT64_C(4086300688),	// VSHRuv4i16
    UINT64_C(4087349328),	// VSHRuv4i32
    UINT64_C(4086300752),	// VSHRuv8i16
    UINT64_C(4085776400),	// VSHRuv8i8
    UINT64_C(247073600),	// VSHTOD
    UINT64_C(247073088),	// VSHTOH
    UINT64_C(247073344),	// VSHTOS
    UINT64_C(246942656),	// VSITOD
    UINT64_C(246942144),	// VSITOH
    UINT64_C(246942400),	// VSITOS
    UINT64_C(4085777744),	// VSLIv16i8
    UINT64_C(4085253520),	// VSLIv1i64
    UINT64_C(4087350544),	// VSLIv2i32
    UINT64_C(4085253584),	// VSLIv2i64
    UINT64_C(4086301968),	// VSLIv4i16
    UINT64_C(4087350608),	// VSLIv4i32
    UINT64_C(4086302032),	// VSLIv8i16
    UINT64_C(4085777680),	// VSLIv8i8
    UINT64_C(247073728),	// VSLTOD
    UINT64_C(247073216),	// VSLTOH
    UINT64_C(247073472),	// VSLTOS
    UINT64_C(246483904),	// VSQRTD
    UINT64_C(246483392),	// VSQRTH
    UINT64_C(246483648),	// VSQRTS
    UINT64_C(4068999504),	// VSRAsv16i8
    UINT64_C(4068475280),	// VSRAsv1i64
    UINT64_C(4070572304),	// VSRAsv2i32
    UINT64_C(4068475344),	// VSRAsv2i64
    UINT64_C(4069523728),	// VSRAsv4i16
    UINT64_C(4070572368),	// VSRAsv4i32
    UINT64_C(4069523792),	// VSRAsv8i16
    UINT64_C(4068999440),	// VSRAsv8i8
    UINT64_C(4085776720),	// VSRAuv16i8
    UINT64_C(4085252496),	// VSRAuv1i64
    UINT64_C(4087349520),	// VSRAuv2i32
    UINT64_C(4085252560),	// VSRAuv2i64
    UINT64_C(4086300944),	// VSRAuv4i16
    UINT64_C(4087349584),	// VSRAuv4i32
    UINT64_C(4086301008),	// VSRAuv8i16
    UINT64_C(4085776656),	// VSRAuv8i8
    UINT64_C(4085777488),	// VSRIv16i8
    UINT64_C(4085253264),	// VSRIv1i64
    UINT64_C(4087350288),	// VSRIv2i32
    UINT64_C(4085253328),	// VSRIv2i64
    UINT64_C(4086301712),	// VSRIv4i16
    UINT64_C(4087350352),	// VSRIv4i32
    UINT64_C(4086301776),	// VSRIv8i16
    UINT64_C(4085777424),	// VSRIv8i8
    UINT64_C(4102030351),	// VST1LNd16
    UINT64_C(4102030336),	// VST1LNd16_UPD
    UINT64_C(4102031375),	// VST1LNd32
    UINT64_C(4102031360),	// VST1LNd32_UPD
    UINT64_C(4102029327),	// VST1LNd8
    UINT64_C(4102029312),	// VST1LNd8_UPD
    UINT64_C(0),	// VST1LNq16Pseudo
    UINT64_C(0),	// VST1LNq16Pseudo_UPD
    UINT64_C(0),	// VST1LNq32Pseudo
    UINT64_C(0),	// VST1LNq32Pseudo_UPD
    UINT64_C(0),	// VST1LNq8Pseudo
    UINT64_C(0),	// VST1LNq8Pseudo_UPD
    UINT64_C(4093642575),	// VST1d16
    UINT64_C(4093641295),	// VST1d16Q
    UINT64_C(0),	// VST1d16QPseudo
    UINT64_C(4093641293),	// VST1d16Qwb_fixed
    UINT64_C(4093641280),	// VST1d16Qwb_register
    UINT64_C(4093642319),	// VST1d16T
    UINT64_C(0),	// VST1d16TPseudo
    UINT64_C(4093642317),	// VST1d16Twb_fixed
    UINT64_C(4093642304),	// VST1d16Twb_register
    UINT64_C(4093642573),	// VST1d16wb_fixed
    UINT64_C(4093642560),	// VST1d16wb_register
    UINT64_C(4093642639),	// VST1d32
    UINT64_C(4093641359),	// VST1d32Q
    UINT64_C(0),	// VST1d32QPseudo
    UINT64_C(4093641357),	// VST1d32Qwb_fixed
    UINT64_C(4093641344),	// VST1d32Qwb_register
    UINT64_C(4093642383),	// VST1d32T
    UINT64_C(0),	// VST1d32TPseudo
    UINT64_C(4093642381),	// VST1d32Twb_fixed
    UINT64_C(4093642368),	// VST1d32Twb_register
    UINT64_C(4093642637),	// VST1d32wb_fixed
    UINT64_C(4093642624),	// VST1d32wb_register
    UINT64_C(4093642703),	// VST1d64
    UINT64_C(4093641423),	// VST1d64Q
    UINT64_C(0),	// VST1d64QPseudo
    UINT64_C(0),	// VST1d64QPseudoWB_fixed
    UINT64_C(0),	// VST1d64QPseudoWB_register
    UINT64_C(4093641421),	// VST1d64Qwb_fixed
    UINT64_C(4093641408),	// VST1d64Qwb_register
    UINT64_C(4093642447),	// VST1d64T
    UINT64_C(0),	// VST1d64TPseudo
    UINT64_C(0),	// VST1d64TPseudoWB_fixed
    UINT64_C(0),	// VST1d64TPseudoWB_register
    UINT64_C(4093642445),	// VST1d64Twb_fixed
    UINT64_C(4093642432),	// VST1d64Twb_register
    UINT64_C(4093642701),	// VST1d64wb_fixed
    UINT64_C(4093642688),	// VST1d64wb_register
    UINT64_C(4093642511),	// VST1d8
    UINT64_C(4093641231),	// VST1d8Q
    UINT64_C(0),	// VST1d8QPseudo
    UINT64_C(4093641229),	// VST1d8Qwb_fixed
    UINT64_C(4093641216),	// VST1d8Qwb_register
    UINT64_C(4093642255),	// VST1d8T
    UINT64_C(0),	// VST1d8TPseudo
    UINT64_C(4093642253),	// VST1d8Twb_fixed
    UINT64_C(4093642240),	// VST1d8Twb_register
    UINT64_C(4093642509),	// VST1d8wb_fixed
    UINT64_C(4093642496),	// VST1d8wb_register
    UINT64_C(4093643343),	// VST1q16
    UINT64_C(0),	// VST1q16HighQPseudo
    UINT64_C(0),	// VST1q16HighTPseudo
    UINT64_C(0),	// VST1q16LowQPseudo_UPD
    UINT64_C(0),	// VST1q16LowTPseudo_UPD
    UINT64_C(4093643341),	// VST1q16wb_fixed
    UINT64_C(4093643328),	// VST1q16wb_register
    UINT64_C(4093643407),	// VST1q32
    UINT64_C(0),	// VST1q32HighQPseudo
    UINT64_C(0),	// VST1q32HighTPseudo
    UINT64_C(0),	// VST1q32LowQPseudo_UPD
    UINT64_C(0),	// VST1q32LowTPseudo_UPD
    UINT64_C(4093643405),	// VST1q32wb_fixed
    UINT64_C(4093643392),	// VST1q32wb_register
    UINT64_C(4093643471),	// VST1q64
    UINT64_C(0),	// VST1q64HighQPseudo
    UINT64_C(0),	// VST1q64HighTPseudo
    UINT64_C(0),	// VST1q64LowQPseudo_UPD
    UINT64_C(0),	// VST1q64LowTPseudo_UPD
    UINT64_C(4093643469),	// VST1q64wb_fixed
    UINT64_C(4093643456),	// VST1q64wb_register
    UINT64_C(4093643279),	// VST1q8
    UINT64_C(0),	// VST1q8HighQPseudo
    UINT64_C(0),	// VST1q8HighTPseudo
    UINT64_C(0),	// VST1q8LowQPseudo_UPD
    UINT64_C(0),	// VST1q8LowTPseudo_UPD
    UINT64_C(4093643277),	// VST1q8wb_fixed
    UINT64_C(4093643264),	// VST1q8wb_register
    UINT64_C(4102030607),	// VST2LNd16
    UINT64_C(0),	// VST2LNd16Pseudo
    UINT64_C(0),	// VST2LNd16Pseudo_UPD
    UINT64_C(4102030592),	// VST2LNd16_UPD
    UINT64_C(4102031631),	// VST2LNd32
    UINT64_C(0),	// VST2LNd32Pseudo
    UINT64_C(0),	// VST2LNd32Pseudo_UPD
    UINT64_C(4102031616),	// VST2LNd32_UPD
    UINT64_C(4102029583),	// VST2LNd8
    UINT64_C(0),	// VST2LNd8Pseudo
    UINT64_C(0),	// VST2LNd8Pseudo_UPD
    UINT64_C(4102029568),	// VST2LNd8_UPD
    UINT64_C(4102030639),	// VST2LNq16
    UINT64_C(0),	// VST2LNq16Pseudo
    UINT64_C(0),	// VST2LNq16Pseudo_UPD
    UINT64_C(4102030624),	// VST2LNq16_UPD
    UINT64_C(4102031695),	// VST2LNq32
    UINT64_C(0),	// VST2LNq32Pseudo
    UINT64_C(0),	// VST2LNq32Pseudo_UPD
    UINT64_C(4102031680),	// VST2LNq32_UPD
    UINT64_C(4093643087),	// VST2b16
    UINT64_C(4093643085),	// VST2b16wb_fixed
    UINT64_C(4093643072),	// VST2b16wb_register
    UINT64_C(4093643151),	// VST2b32
    UINT64_C(4093643149),	// VST2b32wb_fixed
    UINT64_C(4093643136),	// VST2b32wb_register
    UINT64_C(4093643023),	// VST2b8
    UINT64_C(4093643021),	// VST2b8wb_fixed
    UINT64_C(4093643008),	// VST2b8wb_register
    UINT64_C(4093642831),	// VST2d16
    UINT64_C(4093642829),	// VST2d16wb_fixed
    UINT64_C(4093642816),	// VST2d16wb_register
    UINT64_C(4093642895),	// VST2d32
    UINT64_C(4093642893),	// VST2d32wb_fixed
    UINT64_C(4093642880),	// VST2d32wb_register
    UINT64_C(4093642767),	// VST2d8
    UINT64_C(4093642765),	// VST2d8wb_fixed
    UINT64_C(4093642752),	// VST2d8wb_register
    UINT64_C(4093641551),	// VST2q16
    UINT64_C(0),	// VST2q16Pseudo
    UINT64_C(0),	// VST2q16PseudoWB_fixed
    UINT64_C(0),	// VST2q16PseudoWB_register
    UINT64_C(4093641549),	// VST2q16wb_fixed
    UINT64_C(4093641536),	// VST2q16wb_register
    UINT64_C(4093641615),	// VST2q32
    UINT64_C(0),	// VST2q32Pseudo
    UINT64_C(0),	// VST2q32PseudoWB_fixed
    UINT64_C(0),	// VST2q32PseudoWB_register
    UINT64_C(4093641613),	// VST2q32wb_fixed
    UINT64_C(4093641600),	// VST2q32wb_register
    UINT64_C(4093641487),	// VST2q8
    UINT64_C(0),	// VST2q8Pseudo
    UINT64_C(0),	// VST2q8PseudoWB_fixed
    UINT64_C(0),	// VST2q8PseudoWB_register
    UINT64_C(4093641485),	// VST2q8wb_fixed
    UINT64_C(4093641472),	// VST2q8wb_register
    UINT64_C(4102030863),	// VST3LNd16
    UINT64_C(0),	// VST3LNd16Pseudo
    UINT64_C(0),	// VST3LNd16Pseudo_UPD
    UINT64_C(4102030848),	// VST3LNd16_UPD
    UINT64_C(4102031887),	// VST3LNd32
    UINT64_C(0),	// VST3LNd32Pseudo
    UINT64_C(0),	// VST3LNd32Pseudo_UPD
    UINT64_C(4102031872),	// VST3LNd32_UPD
    UINT64_C(4102029839),	// VST3LNd8
    UINT64_C(0),	// VST3LNd8Pseudo
    UINT64_C(0),	// VST3LNd8Pseudo_UPD
    UINT64_C(4102029824),	// VST3LNd8_UPD
    UINT64_C(4102030895),	// VST3LNq16
    UINT64_C(0),	// VST3LNq16Pseudo
    UINT64_C(0),	// VST3LNq16Pseudo_UPD
    UINT64_C(4102030880),	// VST3LNq16_UPD
    UINT64_C(4102031951),	// VST3LNq32
    UINT64_C(0),	// VST3LNq32Pseudo
    UINT64_C(0),	// VST3LNq32Pseudo_UPD
    UINT64_C(4102031936),	// VST3LNq32_UPD
    UINT64_C(4093641807),	// VST3d16
    UINT64_C(0),	// VST3d16Pseudo
    UINT64_C(0),	// VST3d16Pseudo_UPD
    UINT64_C(4093641792),	// VST3d16_UPD
    UINT64_C(4093641871),	// VST3d32
    UINT64_C(0),	// VST3d32Pseudo
    UINT64_C(0),	// VST3d32Pseudo_UPD
    UINT64_C(4093641856),	// VST3d32_UPD
    UINT64_C(4093641743),	// VST3d8
    UINT64_C(0),	// VST3d8Pseudo
    UINT64_C(0),	// VST3d8Pseudo_UPD
    UINT64_C(4093641728),	// VST3d8_UPD
    UINT64_C(4093642063),	// VST3q16
    UINT64_C(0),	// VST3q16Pseudo_UPD
    UINT64_C(4093642048),	// VST3q16_UPD
    UINT64_C(0),	// VST3q16oddPseudo
    UINT64_C(0),	// VST3q16oddPseudo_UPD
    UINT64_C(4093642127),	// VST3q32
    UINT64_C(0),	// VST3q32Pseudo_UPD
    UINT64_C(4093642112),	// VST3q32_UPD
    UINT64_C(0),	// VST3q32oddPseudo
    UINT64_C(0),	// VST3q32oddPseudo_UPD
    UINT64_C(4093641999),	// VST3q8
    UINT64_C(0),	// VST3q8Pseudo_UPD
    UINT64_C(4093641984),	// VST3q8_UPD
    UINT64_C(0),	// VST3q8oddPseudo
    UINT64_C(0),	// VST3q8oddPseudo_UPD
    UINT64_C(4102031119),	// VST4LNd16
    UINT64_C(0),	// VST4LNd16Pseudo
    UINT64_C(0),	// VST4LNd16Pseudo_UPD
    UINT64_C(4102031104),	// VST4LNd16_UPD
    UINT64_C(4102032143),	// VST4LNd32
    UINT64_C(0),	// VST4LNd32Pseudo
    UINT64_C(0),	// VST4LNd32Pseudo_UPD
    UINT64_C(4102032128),	// VST4LNd32_UPD
    UINT64_C(4102030095),	// VST4LNd8
    UINT64_C(0),	// VST4LNd8Pseudo
    UINT64_C(0),	// VST4LNd8Pseudo_UPD
    UINT64_C(4102030080),	// VST4LNd8_UPD
    UINT64_C(4102031151),	// VST4LNq16
    UINT64_C(0),	// VST4LNq16Pseudo
    UINT64_C(0),	// VST4LNq16Pseudo_UPD
    UINT64_C(4102031136),	// VST4LNq16_UPD
    UINT64_C(4102032207),	// VST4LNq32
    UINT64_C(0),	// VST4LNq32Pseudo
    UINT64_C(0),	// VST4LNq32Pseudo_UPD
    UINT64_C(4102032192),	// VST4LNq32_UPD
    UINT64_C(4093640783),	// VST4d16
    UINT64_C(0),	// VST4d16Pseudo
    UINT64_C(0),	// VST4d16Pseudo_UPD
    UINT64_C(4093640768),	// VST4d16_UPD
    UINT64_C(4093640847),	// VST4d32
    UINT64_C(0),	// VST4d32Pseudo
    UINT64_C(0),	// VST4d32Pseudo_UPD
    UINT64_C(4093640832),	// VST4d32_UPD
    UINT64_C(4093640719),	// VST4d8
    UINT64_C(0),	// VST4d8Pseudo
    UINT64_C(0),	// VST4d8Pseudo_UPD
    UINT64_C(4093640704),	// VST4d8_UPD
    UINT64_C(4093641039),	// VST4q16
    UINT64_C(0),	// VST4q16Pseudo_UPD
    UINT64_C(4093641024),	// VST4q16_UPD
    UINT64_C(0),	// VST4q16oddPseudo
    UINT64_C(0),	// VST4q16oddPseudo_UPD
    UINT64_C(4093641103),	// VST4q32
    UINT64_C(0),	// VST4q32Pseudo_UPD
    UINT64_C(4093641088),	// VST4q32_UPD
    UINT64_C(0),	// VST4q32oddPseudo
    UINT64_C(0),	// VST4q32oddPseudo_UPD
    UINT64_C(4093640975),	// VST4q8
    UINT64_C(0),	// VST4q8Pseudo_UPD
    UINT64_C(4093640960),	// VST4q8_UPD
    UINT64_C(0),	// VST4q8oddPseudo
    UINT64_C(0),	// VST4q8oddPseudo_UPD
    UINT64_C(220203776),	// VSTMDDB_UPD
    UINT64_C(209718016),	// VSTMDIA
    UINT64_C(211815168),	// VSTMDIA_UPD
    UINT64_C(0),	// VSTMQIA
    UINT64_C(220203520),	// VSTMSDB_UPD
    UINT64_C(209717760),	// VSTMSIA
    UINT64_C(211814912),	// VSTMSIA_UPD
    UINT64_C(218106624),	// VSTRD
    UINT64_C(218106112),	// VSTRH
    UINT64_C(218106368),	// VSTRS
    UINT64_C(238029632),	// VSUBD
    UINT64_C(238029120),	// VSUBH
    UINT64_C(4070573568),	// VSUBHNv2i32
    UINT64_C(4069524992),	// VSUBHNv4i16
    UINT64_C(4068476416),	// VSUBHNv8i8
    UINT64_C(4070572544),	// VSUBLsv2i64
    UINT64_C(4069523968),	// VSUBLsv4i32
    UINT64_C(4068475392),	// VSUBLsv8i16
    UINT64_C(4087349760),	// VSUBLuv2i64
    UINT64_C(4086301184),	// VSUBLuv4i32
    UINT64_C(4085252608),	// VSUBLuv8i16
    UINT64_C(238029376),	// VSUBS
    UINT64_C(4070572800),	// VSUBWsv2i64
    UINT64_C(4069524224),	// VSUBWsv4i32
    UINT64_C(4068475648),	// VSUBWsv8i16
    UINT64_C(4087350016),	// VSUBWuv2i64
    UINT64_C(4086301440),	// VSUBWuv4i32
    UINT64_C(4085252864),	// VSUBWuv8i16
    UINT64_C(4062186752),	// VSUBfd
    UINT64_C(4062186816),	// VSUBfq
    UINT64_C(4063235328),	// VSUBhd
    UINT64_C(4063235392),	// VSUBhq
    UINT64_C(4076865600),	// VSUBv16i8
    UINT64_C(4080011264),	// VSUBv1i64
    UINT64_C(4078962688),	// VSUBv2i32
    UINT64_C(4080011328),	// VSUBv2i64
    UINT64_C(4077914112),	// VSUBv4i16
    UINT64_C(4078962752),	// VSUBv4i32
    UINT64_C(4077914176),	// VSUBv8i16
    UINT64_C(4076865536),	// VSUBv8i8
    UINT64_C(4088528896),	// VSWPd
    UINT64_C(4088528960),	// VSWPq
    UINT64_C(4088399872),	// VTBL1
    UINT64_C(4088400128),	// VTBL2
    UINT64_C(4088400384),	// VTBL3
    UINT64_C(0),	// VTBL3Pseudo
    UINT64_C(4088400640),	// VTBL4
    UINT64_C(0),	// VTBL4Pseudo
    UINT64_C(4088399936),	// VTBX1
    UINT64_C(4088400192),	// VTBX2
    UINT64_C(4088400448),	// VTBX3
    UINT64_C(0),	// VTBX3Pseudo
    UINT64_C(4088400704),	// VTBX4
    UINT64_C(0),	// VTBX4Pseudo
    UINT64_C(247335744),	// VTOSHD
    UINT64_C(247335232),	// VTOSHH
    UINT64_C(247335488),	// VTOSHS
    UINT64_C(247270208),	// VTOSIRD
    UINT64_C(247269696),	// VTOSIRH
    UINT64_C(247269952),	// VTOSIRS
    UINT64_C(247270336),	// VTOSIZD
    UINT64_C(247269824),	// VTOSIZH
    UINT64_C(247270080),	// VTOSIZS
    UINT64_C(247335872),	// VTOSLD
    UINT64_C(247335360),	// VTOSLH
    UINT64_C(247335616),	// VTOSLS
    UINT64_C(247401280),	// VTOUHD
    UINT64_C(247400768),	// VTOUHH
    UINT64_C(247401024),	// VTOUHS
    UINT64_C(247204672),	// VTOUIRD
    UINT64_C(247204160),	// VTOUIRH
    UINT64_C(247204416),	// VTOUIRS
    UINT64_C(247204800),	// VTOUIZD
    UINT64_C(247204288),	// VTOUIZH
    UINT64_C(247204544),	// VTOUIZS
    UINT64_C(247401408),	// VTOULD
    UINT64_C(247400896),	// VTOULH
    UINT64_C(247401152),	// VTOULS
    UINT64_C(4088791168),	// VTRNd16
    UINT64_C(4089053312),	// VTRNd32
    UINT64_C(4088529024),	// VTRNd8
    UINT64_C(4088791232),	// VTRNq16
    UINT64_C(4089053376),	// VTRNq32
    UINT64_C(4088529088),	// VTRNq8
    UINT64_C(4060088400),	// VTSTv16i8
    UINT64_C(4062185488),	// VTSTv2i32
    UINT64_C(4061136912),	// VTSTv4i16
    UINT64_C(4062185552),	// VTSTv4i32
    UINT64_C(4061136976),	// VTSTv8i16
    UINT64_C(4060088336),	// VTSTv8i8
    UINT64_C(4229958928),	// VUDOTD
    UINT64_C(4263513360),	// VUDOTDI
    UINT64_C(4229958992),	// VUDOTQ
    UINT64_C(4263513424),	// VUDOTQI
    UINT64_C(247139136),	// VUHTOD
    UINT64_C(247138624),	// VUHTOH
    UINT64_C(247138880),	// VUHTOS
    UINT64_C(246942528),	// VUITOD
    UINT64_C(246942016),	// VUITOH
    UINT64_C(246942272),	// VUITOS
    UINT64_C(247139264),	// VULTOD
    UINT64_C(247138752),	// VULTOH
    UINT64_C(247139008),	// VULTOS
    UINT64_C(4088791296),	// VUZPd16
    UINT64_C(4088529152),	// VUZPd8
    UINT64_C(4088791360),	// VUZPq16
    UINT64_C(4089053504),	// VUZPq32
    UINT64_C(4088529216),	// VUZPq8
    UINT64_C(4088791424),	// VZIPd16
    UINT64_C(4088529280),	// VZIPd8
    UINT64_C(4088791488),	// VZIPq16
    UINT64_C(4089053632),	// VZIPq32
    UINT64_C(4088529344),	// VZIPq8
    UINT64_C(139460608),	// sysLDMDA
    UINT64_C(141557760),	// sysLDMDA_UPD
    UINT64_C(156237824),	// sysLDMDB
    UINT64_C(158334976),	// sysLDMDB_UPD
    UINT64_C(147849216),	// sysLDMIA
    UINT64_C(149946368),	// sysLDMIA_UPD
    UINT64_C(164626432),	// sysLDMIB
    UINT64_C(166723584),	// sysLDMIB_UPD
    UINT64_C(138412032),	// sysSTMDA
    UINT64_C(140509184),	// sysSTMDA_UPD
    UINT64_C(155189248),	// sysSTMDB
    UINT64_C(157286400),	// sysSTMDB_UPD
    UINT64_C(146800640),	// sysSTMIA
    UINT64_C(148897792),	// sysSTMIA_UPD
    UINT64_C(163577856),	// sysSTMIB
    UINT64_C(165675008),	// sysSTMIB_UPD
    UINT64_C(4047503360),	// t2ADCri
    UINT64_C(3946840064),	// t2ADCrr
    UINT64_C(3946840064),	// t2ADCrs
    UINT64_C(4043309056),	// t2ADDri
    UINT64_C(4060086272),	// t2ADDri12
    UINT64_C(3942645760),	// t2ADDrr
    UINT64_C(3942645760),	// t2ADDrs
    UINT64_C(4061069312),	// t2ADR
    UINT64_C(4026531840),	// t2ANDri
    UINT64_C(3925868544),	// t2ANDrr
    UINT64_C(3925868544),	// t2ANDrs
    UINT64_C(3931045920),	// t2ASRri
    UINT64_C(4198559744),	// t2ASRrr
    UINT64_C(4026568704),	// t2B
    UINT64_C(4084137984),	// t2BFC
    UINT64_C(4083154944),	// t2BFI
    UINT64_C(4028628992),	// t2BICri
    UINT64_C(3927965696),	// t2BICrr
    UINT64_C(3927965696),	// t2BICrs
    UINT64_C(4089483008),	// t2BXJ
    UINT64_C(4026564608),	// t2Bcc
    UINT64_C(3992977408),	// t2CDP
    UINT64_C(4261412864),	// t2CDP2
    UINT64_C(4089417519),	// t2CLREX
    UINT64_C(4205899904),	// t2CLZ
    UINT64_C(4044361472),	// t2CMNri
    UINT64_C(3943698176),	// t2CMNzrr
    UINT64_C(3943698176),	// t2CMNzrs
    UINT64_C(4054847232),	// t2CMPri
    UINT64_C(3954183936),	// t2CMPrr
    UINT64_C(3954183936),	// t2CMPrs
    UINT64_C(4088365312),	// t2CPS1p
    UINT64_C(4088365056),	// t2CPS2p
    UINT64_C(4088365312),	// t2CPS3p
    UINT64_C(4206948480),	// t2CRC32B
    UINT64_C(4207997056),	// t2CRC32CB
    UINT64_C(4207997072),	// t2CRC32CH
    UINT64_C(4207997088),	// t2CRC32CW
    UINT64_C(4206948496),	// t2CRC32H
    UINT64_C(4206948512),	// t2CRC32W
    UINT64_C(4088365296),	// t2DBG
    UINT64_C(4153376769),	// t2DCPS1
    UINT64_C(4153376770),	// t2DCPS2
    UINT64_C(4153376771),	// t2DCPS3
    UINT64_C(4089417552),	// t2DMB
    UINT64_C(4089417536),	// t2DSB
    UINT64_C(4034920448),	// t2EORri
    UINT64_C(3934257152),	// t2EORrr
    UINT64_C(3934257152),	// t2EORrs
    UINT64_C(4088365056),	// t2HINT
    UINT64_C(4158685184),	// t2HVC
    UINT64_C(4089417568),	// t2ISB
    UINT64_C(48896),	// t2IT
    UINT64_C(0),	// t2Int_eh_sjlj_setjmp
    UINT64_C(0),	// t2Int_eh_sjlj_setjmp_nofp
    UINT64_C(3905949615),	// t2LDA
    UINT64_C(3905949583),	// t2LDAB
    UINT64_C(3905949679),	// t2LDAEX
    UINT64_C(3905949647),	// t2LDAEXB
    UINT64_C(3905945855),	// t2LDAEXD
    UINT64_C(3905949663),	// t2LDAEXH
    UINT64_C(3905949599),	// t2LDAH
    UINT64_C(4249878528),	// t2LDC2L_OFFSET
    UINT64_C(4241489920),	// t2LDC2L_OPTION
    UINT64_C(4235198464),	// t2LDC2L_POST
    UINT64_C(4251975680),	// t2LDC2L_PRE
    UINT64_C(4245684224),	// t2LDC2_OFFSET
    UINT64_C(4237295616),	// t2LDC2_OPTION
    UINT64_C(4231004160),	// t2LDC2_POST
    UINT64_C(4247781376),	// t2LDC2_PRE
    UINT64_C(3981443072),	// t2LDCL_OFFSET
    UINT64_C(3973054464),	// t2LDCL_OPTION
    UINT64_C(3966763008),	// t2LDCL_POST
    UINT64_C(3983540224),	// t2LDCL_PRE
    UINT64_C(3977248768),	// t2LDC_OFFSET
    UINT64_C(3968860160),	// t2LDC_OPTION
    UINT64_C(3962568704),	// t2LDC_POST
    UINT64_C(3979345920),	// t2LDC_PRE
    UINT64_C(3910139904),	// t2LDMDB
    UINT64_C(3912237056),	// t2LDMDB_UPD
    UINT64_C(3901751296),	// t2LDMIA
    UINT64_C(3903848448),	// t2LDMIA_UPD
    UINT64_C(4161801728),	// t2LDRBT
    UINT64_C(4161800448),	// t2LDRB_POST
    UINT64_C(4161801472),	// t2LDRB_PRE
    UINT64_C(4170186752),	// t2LDRBi12
    UINT64_C(4161801216),	// t2LDRBi8
    UINT64_C(4162781184),	// t2LDRBpci
    UINT64_C(4161798144),	// t2LDRBs
    UINT64_C(3899654144),	// t2LDRD_POST
    UINT64_C(3916431360),	// t2LDRD_PRE
    UINT64_C(3914334208),	// t2LDRDi8
    UINT64_C(3897560832),	// t2LDREX
    UINT64_C(3905949519),	// t2LDREXB
    UINT64_C(3905945727),	// t2LDREXD
    UINT64_C(3905949535),	// t2LDREXH
    UINT64_C(4163898880),	// t2LDRHT
    UINT64_C(4163897600),	// t2LDRH_POST
    UINT64_C(4163898624),	// t2LDRH_PRE
    UINT64_C(4172283904),	// t2LDRHi12
    UINT64_C(4163898368),	// t2LDRHi8
    UINT64_C(4164878336),	// t2LDRHpci
    UINT64_C(4163895296),	// t2LDRHs
    UINT64_C(4178578944),	// t2LDRSBT
    UINT64_C(4178577664),	// t2LDRSB_POST
    UINT64_C(4178578688),	// t2LDRSB_PRE
    UINT64_C(4186963968),	// t2LDRSBi12
    UINT64_C(4178578432),	// t2LDRSBi8
    UINT64_C(4179558400),	// t2LDRSBpci
    UINT64_C(4178575360),	// t2LDRSBs
    UINT64_C(4180676096),	// t2LDRSHT
    UINT64_C(4180674816),	// t2LDRSH_POST
    UINT64_C(4180675840),	// t2LDRSH_PRE
    UINT64_C(4189061120),	// t2LDRSHi12
    UINT64_C(4180675584),	// t2LDRSHi8
    UINT64_C(4181655552),	// t2LDRSHpci
    UINT64_C(4180672512),	// t2LDRSHs
    UINT64_C(4165996032),	// t2LDRT
    UINT64_C(4165994752),	// t2LDR_POST
    UINT64_C(4165995776),	// t2LDR_PRE
    UINT64_C(4174381056),	// t2LDRi12
    UINT64_C(4165995520),	// t2LDRi8
    UINT64_C(4166975488),	// t2LDRpci
    UINT64_C(4165992448),	// t2LDRs
    UINT64_C(3931045888),	// t2LSLri
    UINT64_C(4194365440),	// t2LSLrr
    UINT64_C(3931045904),	// t2LSRri
    UINT64_C(4196462592),	// t2LSRrr
    UINT64_C(3992977424),	// t2MCR
    UINT64_C(4261412880),	// t2MCR2
    UINT64_C(3963617280),	// t2MCRR
    UINT64_C(4232052736),	// t2MCRR2
    UINT64_C(4211081216),	// t2MLA
    UINT64_C(4211081232),	// t2MLS
    UINT64_C(4072669184),	// t2MOVTi16
    UINT64_C(4031709184),	// t2MOVi
    UINT64_C(4064280576),	// t2MOVi16
    UINT64_C(3931045888),	// t2MOVr
    UINT64_C(3932094560),	// t2MOVsra_flag
    UINT64_C(3932094544),	// t2MOVsrl_flag
    UINT64_C(3994026000),	// t2MRC
    UINT64_C(4262461456),	// t2MRC2
    UINT64_C(3964665856),	// t2MRRC
    UINT64_C(4233101312),	// t2MRRC2
    UINT64_C(4092559360),	// t2MRS_AR
    UINT64_C(4092559360),	// t2MRS_M
    UINT64_C(4091576352),	// t2MRSbanked
    UINT64_C(4093607936),	// t2MRSsys_AR
    UINT64_C(4085284864),	// t2MSR_AR
    UINT64_C(4085284864),	// t2MSR_M
    UINT64_C(4085284896),	// t2MSRbanked
    UINT64_C(4211142656),	// t2MUL
    UINT64_C(4033806336),	// t2MVNi
    UINT64_C(3933143040),	// t2MVNr
    UINT64_C(3933143040),	// t2MVNs
    UINT64_C(4032823296),	// t2ORNri
    UINT64_C(3932160000),	// t2ORNrr
    UINT64_C(3932160000),	// t2ORNrs
    UINT64_C(4030726144),	// t2ORRri
    UINT64_C(3930062848),	// t2ORRrr
    UINT64_C(3930062848),	// t2ORRrs
    UINT64_C(3938451456),	// t2PKHBT
    UINT64_C(3938451488),	// t2PKHTB
    UINT64_C(4172345344),	// t2PLDWi12
    UINT64_C(4163959808),	// t2PLDWi8
    UINT64_C(4163956736),	// t2PLDWs
    UINT64_C(4170248192),	// t2PLDi12
    UINT64_C(4161862656),	// t2PLDi8
    UINT64_C(4162842624),	// t2PLDpci
    UINT64_C(4161859584),	// t2PLDs
    UINT64_C(4187025408),	// t2PLIi12
    UINT64_C(4178639872),	// t2PLIi8
    UINT64_C(4179619840),	// t2PLIpci
    UINT64_C(4178636800),	// t2PLIs
    UINT64_C(4202754176),	// t2QADD
    UINT64_C(4203802640),	// t2QADD16
    UINT64_C(4202754064),	// t2QADD8
    UINT64_C(4204851216),	// t2QASX
    UINT64_C(4202754192),	// t2QDADD
    UINT64_C(4202754224),	// t2QDSUB
    UINT64_C(4209045520),	// t2QSAX
    UINT64_C(4202754208),	// t2QSUB
    UINT64_C(4207996944),	// t2QSUB16
    UINT64_C(4206948368),	// t2QSUB8
    UINT64_C(4203802784),	// t2RBIT
    UINT64_C(4203802752),	// t2REV
    UINT64_C(4203802768),	// t2REV16
    UINT64_C(4203802800),	// t2REVSH
    UINT64_C(3893411840),	// t2RFEDB
    UINT64_C(3895508992),	// t2RFEDBW
    UINT64_C(3918577664),	// t2RFEIA
    UINT64_C(3920674816),	// t2RFEIAW
    UINT64_C(3931045936),	// t2RORri
    UINT64_C(4200656896),	// t2RORrr
    UINT64_C(3931045936),	// t2RRX
    UINT64_C(4055891968),	// t2RSBri
    UINT64_C(3955228672),	// t2RSBrr
    UINT64_C(3955228672),	// t2RSBrs
    UINT64_C(4203802624),	// t2SADD16
    UINT64_C(4202754048),	// t2SADD8
    UINT64_C(4204851200),	// t2SASX
    UINT64_C(4049600512),	// t2SBCri
    UINT64_C(3948937216),	// t2SBCrr
    UINT64_C(3948937216),	// t2SBCrs
    UINT64_C(4081057792),	// t2SBFX
    UINT64_C(4220580080),	// t2SDIV
    UINT64_C(4204851328),	// t2SEL
    UINT64_C(46608),	// t2SETPAN
    UINT64_C(3917474175),	// t2SG
    UINT64_C(4203802656),	// t2SHADD16
    UINT64_C(4202754080),	// t2SHADD8
    UINT64_C(4204851232),	// t2SHASX
    UINT64_C(4209045536),	// t2SHSAX
    UINT64_C(4207996960),	// t2SHSUB16
    UINT64_C(4206948384),	// t2SHSUB8
    UINT64_C(4159733760),	// t2SMC
    UINT64_C(4212129792),	// t2SMLABB
    UINT64_C(4212129808),	// t2SMLABT
    UINT64_C(4213178368),	// t2SMLAD
    UINT64_C(4213178384),	// t2SMLADX
    UINT64_C(4223664128),	// t2SMLAL
    UINT64_C(4223664256),	// t2SMLALBB
    UINT64_C(4223664272),	// t2SMLALBT
    UINT64_C(4223664320),	// t2SMLALD
    UINT64_C(4223664336),	// t2SMLALDX
    UINT64_C(4223664288),	// t2SMLALTB
    UINT64_C(4223664304),	// t2SMLALTT
    UINT64_C(4212129824),	// t2SMLATB
    UINT64_C(4212129840),	// t2SMLATT
    UINT64_C(4214226944),	// t2SMLAWB
    UINT64_C(4214226960),	// t2SMLAWT
    UINT64_C(4215275520),	// t2SMLSD
    UINT64_C(4215275536),	// t2SMLSDX
    UINT64_C(4224712896),	// t2SMLSLD
    UINT64_C(4224712912),	// t2SMLSLDX
    UINT64_C(4216324096),	// t2SMMLA
    UINT64_C(4216324112),	// t2SMMLAR
    UINT64_C(4217372672),	// t2SMMLS
    UINT64_C(4217372688),	// t2SMMLSR
    UINT64_C(4216385536),	// t2SMMUL
    UINT64_C(4216385552),	// t2SMMULR
    UINT64_C(4213239808),	// t2SMUAD
    UINT64_C(4213239824),	// t2SMUADX
    UINT64_C(4212191232),	// t2SMULBB
    UINT64_C(4212191248),	// t2SMULBT
    UINT64_C(4219469824),	// t2SMULL
    UINT64_C(4212191264),	// t2SMULTB
    UINT64_C(4212191280),	// t2SMULTT
    UINT64_C(4214288384),	// t2SMULWB
    UINT64_C(4214288400),	// t2SMULWT
    UINT64_C(4215336960),	// t2SMUSD
    UINT64_C(4215336976),	// t2SMUSDX
    UINT64_C(3893215232),	// t2SRSDB
    UINT64_C(3895312384),	// t2SRSDB_UPD
    UINT64_C(3918381056),	// t2SRSIA
    UINT64_C(3920478208),	// t2SRSIA_UPD
    UINT64_C(4076863488),	// t2SSAT
    UINT64_C(4078960640),	// t2SSAT16
    UINT64_C(4209045504),	// t2SSAX
    UINT64_C(4207996928),	// t2SSUB16
    UINT64_C(4206948352),	// t2SSUB8
    UINT64_C(4248829952),	// t2STC2L_OFFSET
    UINT64_C(4240441344),	// t2STC2L_OPTION
    UINT64_C(4234149888),	// t2STC2L_POST
    UINT64_C(4250927104),	// t2STC2L_PRE
    UINT64_C(4244635648),	// t2STC2_OFFSET
    UINT64_C(4236247040),	// t2STC2_OPTION
    UINT64_C(4229955584),	// t2STC2_POST
    UINT64_C(4246732800),	// t2STC2_PRE
    UINT64_C(3980394496),	// t2STCL_OFFSET
    UINT64_C(3972005888),	// t2STCL_OPTION
    UINT64_C(3965714432),	// t2STCL_POST
    UINT64_C(3982491648),	// t2STCL_PRE
    UINT64_C(3976200192),	// t2STC_OFFSET
    UINT64_C(3967811584),	// t2STC_OPTION
    UINT64_C(3961520128),	// t2STC_POST
    UINT64_C(3978297344),	// t2STC_PRE
    UINT64_C(3904901039),	// t2STL
    UINT64_C(3904901007),	// t2STLB
    UINT64_C(3904901088),	// t2STLEX
    UINT64_C(3904901056),	// t2STLEXB
    UINT64_C(3904897264),	// t2STLEXD
    UINT64_C(3904901072),	// t2STLEXH
    UINT64_C(3904901023),	// t2STLH
    UINT64_C(3909091328),	// t2STMDB
    UINT64_C(3911188480),	// t2STMDB_UPD
    UINT64_C(3900702720),	// t2STMIA
    UINT64_C(3902799872),	// t2STMIA_UPD
    UINT64_C(4160753152),	// t2STRBT
    UINT64_C(4160751872),	// t2STRB_POST
    UINT64_C(4160752896),	// t2STRB_PRE
    UINT64_C(4169138176),	// t2STRBi12
    UINT64_C(4160752640),	// t2STRBi8
    UINT64_C(4160749568),	// t2STRBs
    UINT64_C(3898605568),	// t2STRD_POST
    UINT64_C(3915382784),	// t2STRD_PRE
    UINT64_C(3913285632),	// t2STRDi8
    UINT64_C(3896508416),	// t2STREX
    UINT64_C(3904900928),	// t2STREXB
    UINT64_C(3904897136),	// t2STREXD
    UINT64_C(3904900944),	// t2STREXH
    UINT64_C(4162850304),	// t2STRHT
    UINT64_C(4162849024),	// t2STRH_POST
    UINT64_C(4162850048),	// t2STRH_PRE
    UINT64_C(4171235328),	// t2STRHi12
    UINT64_C(4162849792),	// t2STRHi8
    UINT64_C(4162846720),	// t2STRHs
    UINT64_C(4164947456),	// t2STRT
    UINT64_C(4164946176),	// t2STR_POST
    UINT64_C(4164947200),	// t2STR_PRE
    UINT64_C(4173332480),	// t2STRi12
    UINT64_C(4164946944),	// t2STRi8
    UINT64_C(4164943872),	// t2STRs
    UINT64_C(4091449088),	// t2SUBS_PC_LR
    UINT64_C(4053794816),	// t2SUBri
    UINT64_C(4070572032),	// t2SUBri12
    UINT64_C(3953131520),	// t2SUBrr
    UINT64_C(3953131520),	// t2SUBrs
    UINT64_C(4198559872),	// t2SXTAB
    UINT64_C(4196462720),	// t2SXTAB16
    UINT64_C(4194365568),	// t2SXTAH
    UINT64_C(4199542912),	// t2SXTB
    UINT64_C(4197445760),	// t2SXTB16
    UINT64_C(4195348608),	// t2SXTH
    UINT64_C(3906007040),	// t2TBB
    UINT64_C(3906007056),	// t2TBH
    UINT64_C(4035972864),	// t2TEQri
    UINT64_C(3935309568),	// t2TEQrr
    UINT64_C(3935309568),	// t2TEQrs
    UINT64_C(4088365074),	// t2TSB
    UINT64_C(4027584256),	// t2TSTri
    UINT64_C(3926920960),	// t2TSTrr
    UINT64_C(3926920960),	// t2TSTrs
    UINT64_C(3896569856),	// t2TT
    UINT64_C(3896569984),	// t2TTA
    UINT64_C(3896570048),	// t2TTAT
    UINT64_C(3896569920),	// t2TTT
    UINT64_C(4203802688),	// t2UADD16
    UINT64_C(4202754112),	// t2UADD8
    UINT64_C(4204851264),	// t2UASX
    UINT64_C(4089446400),	// t2UBFX
    UINT64_C(4159741952),	// t2UDF
    UINT64_C(4222677232),	// t2UDIV
    UINT64_C(4203802720),	// t2UHADD16
    UINT64_C(4202754144),	// t2UHADD8
    UINT64_C(4204851296),	// t2UHASX
    UINT64_C(4209045600),	// t2UHSAX
    UINT64_C(4207997024),	// t2UHSUB16
    UINT64_C(4206948448),	// t2UHSUB8
    UINT64_C(4225761376),	// t2UMAAL
    UINT64_C(4225761280),	// t2UMLAL
    UINT64_C(4221566976),	// t2UMULL
    UINT64_C(4203802704),	// t2UQADD16
    UINT64_C(4202754128),	// t2UQADD8
    UINT64_C(4204851280),	// t2UQASX
    UINT64_C(4209045584),	// t2UQSAX
    UINT64_C(4207997008),	// t2UQSUB16
    UINT64_C(4206948432),	// t2UQSUB8
    UINT64_C(4218482688),	// t2USAD8
    UINT64_C(4218421248),	// t2USADA8
    UINT64_C(4085252096),	// t2USAT
    UINT64_C(4087349248),	// t2USAT16
    UINT64_C(4209045568),	// t2USAX
    UINT64_C(4207996992),	// t2USUB16
    UINT64_C(4206948416),	// t2USUB8
    UINT64_C(4199608448),	// t2UXTAB
    UINT64_C(4197511296),	// t2UXTAB16
    UINT64_C(4195414144),	// t2UXTAH
    UINT64_C(4200591488),	// t2UXTB
    UINT64_C(4198494336),	// t2UXTB16
    UINT64_C(4196397184),	// t2UXTH
    UINT64_C(16704),	// tADC
    UINT64_C(17408),	// tADDhirr
    UINT64_C(7168),	// tADDi3
    UINT64_C(12288),	// tADDi8
    UINT64_C(17512),	// tADDrSP
    UINT64_C(43008),	// tADDrSPi
    UINT64_C(6144),	// tADDrr
    UINT64_C(45056),	// tADDspi
    UINT64_C(17541),	// tADDspr
    UINT64_C(40960),	// tADR
    UINT64_C(16384),	// tAND
    UINT64_C(4096),	// tASRri
    UINT64_C(16640),	// tASRrr
    UINT64_C(57344),	// tB
    UINT64_C(17280),	// tBIC
    UINT64_C(48640),	// tBKPT
    UINT64_C(4026585088),	// tBL
    UINT64_C(18308),	// tBLXNSr
    UINT64_C(4026580992),	// tBLXi
    UINT64_C(18304),	// tBLXr
    UINT64_C(18176),	// tBX
    UINT64_C(18180),	// tBXNS
    UINT64_C(53248),	// tBcc
    UINT64_C(47360),	// tCBNZ
    UINT64_C(45312),	// tCBZ
    UINT64_C(17088),	// tCMNz
    UINT64_C(17664),	// tCMPhir
    UINT64_C(10240),	// tCMPi8
    UINT64_C(17024),	// tCMPr
    UINT64_C(46688),	// tCPS
    UINT64_C(16448),	// tEOR
    UINT64_C(48896),	// tHINT
    UINT64_C(47744),	// tHLT
    UINT64_C(0),	// tInt_WIN_eh_sjlj_longjmp
    UINT64_C(0),	// tInt_eh_sjlj_longjmp
    UINT64_C(0),	// tInt_eh_sjlj_setjmp
    UINT64_C(51200),	// tLDMIA
    UINT64_C(30720),	// tLDRBi
    UINT64_C(23552),	// tLDRBr
    UINT64_C(34816),	// tLDRHi
    UINT64_C(23040),	// tLDRHr
    UINT64_C(22016),	// tLDRSB
    UINT64_C(24064),	// tLDRSH
    UINT64_C(26624),	// tLDRi
    UINT64_C(18432),	// tLDRpci
    UINT64_C(22528),	// tLDRr
    UINT64_C(38912),	// tLDRspi
    UINT64_C(0),	// tLSLri
    UINT64_C(16512),	// tLSLrr
    UINT64_C(2048),	// tLSRri
    UINT64_C(16576),	// tLSRrr
    UINT64_C(0),	// tMOVSr
    UINT64_C(8192),	// tMOVi8
    UINT64_C(17920),	// tMOVr
    UINT64_C(17216),	// tMUL
    UINT64_C(17344),	// tMVN
    UINT64_C(17152),	// tORR
    UINT64_C(17528),	// tPICADD
    UINT64_C(48128),	// tPOP
    UINT64_C(46080),	// tPUSH
    UINT64_C(47616),	// tREV
    UINT64_C(47680),	// tREV16
    UINT64_C(47808),	// tREVSH
    UINT64_C(16832),	// tROR
    UINT64_C(16960),	// tRSB
    UINT64_C(16768),	// tSBC
    UINT64_C(46672),	// tSETEND
    UINT64_C(49152),	// tSTMIA_UPD
    UINT64_C(28672),	// tSTRBi
    UINT64_C(21504),	// tSTRBr
    UINT64_C(32768),	// tSTRHi
    UINT64_C(20992),	// tSTRHr
    UINT64_C(24576),	// tSTRi
    UINT64_C(20480),	// tSTRr
    UINT64_C(36864),	// tSTRspi
    UINT64_C(7680),	// tSUBi3
    UINT64_C(14336),	// tSUBi8
    UINT64_C(6656),	// tSUBrr
    UINT64_C(45184),	// tSUBspi
    UINT64_C(57088),	// tSVC
    UINT64_C(45632),	// tSXTB
    UINT64_C(45568),	// tSXTH
    UINT64_C(57086),	// tTRAP
    UINT64_C(16896),	// tTST
    UINT64_C(56832),	// tUDF
    UINT64_C(45760),	// tUXTB
    UINT64_C(45696),	// tUXTH
    UINT64_C(57081),	// t__brkdiv0
    UINT64_C(0)
  };
  const unsigned opcode = MI.getOpcode();
  uint64_t Value = InstBits[opcode];
  uint64_t op = 0;
  (void)op;  // suppress warning
  switch (opcode) {
    case ARM::CLREX:
    case ARM::TRAP:
    case ARM::TRAPNaCl:
    case ARM::TSB:
    case ARM::VLD1LNq16Pseudo:
    case ARM::VLD1LNq16Pseudo_UPD:
    case ARM::VLD1LNq32Pseudo:
    case ARM::VLD1LNq32Pseudo_UPD:
    case ARM::VLD1LNq8Pseudo:
    case ARM::VLD1LNq8Pseudo_UPD:
    case ARM::VLD1d16QPseudo:
    case ARM::VLD1d16TPseudo:
    case ARM::VLD1d32QPseudo:
    case ARM::VLD1d32TPseudo:
    case ARM::VLD1d64QPseudo:
    case ARM::VLD1d64QPseudoWB_fixed:
    case ARM::VLD1d64QPseudoWB_register:
    case ARM::VLD1d64TPseudo:
    case ARM::VLD1d64TPseudoWB_fixed:
    case ARM::VLD1d64TPseudoWB_register:
    case ARM::VLD1d8QPseudo:
    case ARM::VLD1d8TPseudo:
    case ARM::VLD1q16HighQPseudo:
    case ARM::VLD1q16HighTPseudo:
    case ARM::VLD1q16LowQPseudo_UPD:
    case ARM::VLD1q16LowTPseudo_UPD:
    case ARM::VLD1q32HighQPseudo:
    case ARM::VLD1q32HighTPseudo:
    case ARM::VLD1q32LowQPseudo_UPD:
    case ARM::VLD1q32LowTPseudo_UPD:
    case ARM::VLD1q64HighQPseudo:
    case ARM::VLD1q64HighTPseudo:
    case ARM::VLD1q64LowQPseudo_UPD:
    case ARM::VLD1q64LowTPseudo_UPD:
    case ARM::VLD1q8HighQPseudo:
    case ARM::VLD1q8HighTPseudo:
    case ARM::VLD1q8LowQPseudo_UPD:
    case ARM::VLD1q8LowTPseudo_UPD:
    case ARM::VLD2DUPq16EvenPseudo:
    case ARM::VLD2DUPq16OddPseudo:
    case ARM::VLD2DUPq32EvenPseudo:
    case ARM::VLD2DUPq32OddPseudo:
    case ARM::VLD2DUPq8EvenPseudo:
    case ARM::VLD2DUPq8OddPseudo:
    case ARM::VLD2LNd16Pseudo:
    case ARM::VLD2LNd16Pseudo_UPD:
    case ARM::VLD2LNd32Pseudo:
    case ARM::VLD2LNd32Pseudo_UPD:
    case ARM::VLD2LNd8Pseudo:
    case ARM::VLD2LNd8Pseudo_UPD:
    case ARM::VLD2LNq16Pseudo:
    case ARM::VLD2LNq16Pseudo_UPD:
    case ARM::VLD2LNq32Pseudo:
    case ARM::VLD2LNq32Pseudo_UPD:
    case ARM::VLD2q16Pseudo:
    case ARM::VLD2q16PseudoWB_fixed:
    case ARM::VLD2q16PseudoWB_register:
    case ARM::VLD2q32Pseudo:
    case ARM::VLD2q32PseudoWB_fixed:
    case ARM::VLD2q32PseudoWB_register:
    case ARM::VLD2q8Pseudo:
    case ARM::VLD2q8PseudoWB_fixed:
    case ARM::VLD2q8PseudoWB_register:
    case ARM::VLD3DUPd16Pseudo:
    case ARM::VLD3DUPd16Pseudo_UPD:
    case ARM::VLD3DUPd32Pseudo:
    case ARM::VLD3DUPd32Pseudo_UPD:
    case ARM::VLD3DUPd8Pseudo:
    case ARM::VLD3DUPd8Pseudo_UPD:
    case ARM::VLD3DUPq16EvenPseudo:
    case ARM::VLD3DUPq16OddPseudo:
    case ARM::VLD3DUPq32EvenPseudo:
    case ARM::VLD3DUPq32OddPseudo:
    case ARM::VLD3DUPq8EvenPseudo:
    case ARM::VLD3DUPq8OddPseudo:
    case ARM::VLD3LNd16Pseudo:
    case ARM::VLD3LNd16Pseudo_UPD:
    case ARM::VLD3LNd32Pseudo:
    case ARM::VLD3LNd32Pseudo_UPD:
    case ARM::VLD3LNd8Pseudo:
    case ARM::VLD3LNd8Pseudo_UPD:
    case ARM::VLD3LNq16Pseudo:
    case ARM::VLD3LNq16Pseudo_UPD:
    case ARM::VLD3LNq32Pseudo:
    case ARM::VLD3LNq32Pseudo_UPD:
    case ARM::VLD3d16Pseudo:
    case ARM::VLD3d16Pseudo_UPD:
    case ARM::VLD3d32Pseudo:
    case ARM::VLD3d32Pseudo_UPD:
    case ARM::VLD3d8Pseudo:
    case ARM::VLD3d8Pseudo_UPD:
    case ARM::VLD3q16Pseudo_UPD:
    case ARM::VLD3q16oddPseudo:
    case ARM::VLD3q16oddPseudo_UPD:
    case ARM::VLD3q32Pseudo_UPD:
    case ARM::VLD3q32oddPseudo:
    case ARM::VLD3q32oddPseudo_UPD:
    case ARM::VLD3q8Pseudo_UPD:
    case ARM::VLD3q8oddPseudo:
    case ARM::VLD3q8oddPseudo_UPD:
    case ARM::VLD4DUPd16Pseudo:
    case ARM::VLD4DUPd16Pseudo_UPD:
    case ARM::VLD4DUPd32Pseudo:
    case ARM::VLD4DUPd32Pseudo_UPD:
    case ARM::VLD4DUPd8Pseudo:
    case ARM::VLD4DUPd8Pseudo_UPD:
    case ARM::VLD4DUPq16EvenPseudo:
    case ARM::VLD4DUPq16OddPseudo:
    case ARM::VLD4DUPq32EvenPseudo:
    case ARM::VLD4DUPq32OddPseudo:
    case ARM::VLD4DUPq8EvenPseudo:
    case ARM::VLD4DUPq8OddPseudo:
    case ARM::VLD4LNd16Pseudo:
    case ARM::VLD4LNd16Pseudo_UPD:
    case ARM::VLD4LNd32Pseudo:
    case ARM::VLD4LNd32Pseudo_UPD:
    case ARM::VLD4LNd8Pseudo:
    case ARM::VLD4LNd8Pseudo_UPD:
    case ARM::VLD4LNq16Pseudo:
    case ARM::VLD4LNq16Pseudo_UPD:
    case ARM::VLD4LNq32Pseudo:
    case ARM::VLD4LNq32Pseudo_UPD:
    case ARM::VLD4d16Pseudo:
    case ARM::VLD4d16Pseudo_UPD:
    case ARM::VLD4d32Pseudo:
    case ARM::VLD4d32Pseudo_UPD:
    case ARM::VLD4d8Pseudo:
    case ARM::VLD4d8Pseudo_UPD:
    case ARM::VLD4q16Pseudo_UPD:
    case ARM::VLD4q16oddPseudo:
    case ARM::VLD4q16oddPseudo_UPD:
    case ARM::VLD4q32Pseudo_UPD:
    case ARM::VLD4q32oddPseudo:
    case ARM::VLD4q32oddPseudo_UPD:
    case ARM::VLD4q8Pseudo_UPD:
    case ARM::VLD4q8oddPseudo:
    case ARM::VLD4q8oddPseudo_UPD:
    case ARM::VLDMQIA:
    case ARM::VST1LNq16Pseudo:
    case ARM::VST1LNq16Pseudo_UPD:
    case ARM::VST1LNq32Pseudo:
    case ARM::VST1LNq32Pseudo_UPD:
    case ARM::VST1LNq8Pseudo:
    case ARM::VST1LNq8Pseudo_UPD:
    case ARM::VST1d16QPseudo:
    case ARM::VST1d16TPseudo:
    case ARM::VST1d32QPseudo:
    case ARM::VST1d32TPseudo:
    case ARM::VST1d64QPseudo:
    case ARM::VST1d64QPseudoWB_fixed:
    case ARM::VST1d64QPseudoWB_register:
    case ARM::VST1d64TPseudo:
    case ARM::VST1d64TPseudoWB_fixed:
    case ARM::VST1d64TPseudoWB_register:
    case ARM::VST1d8QPseudo:
    case ARM::VST1d8TPseudo:
    case ARM::VST1q16HighQPseudo:
    case ARM::VST1q16HighTPseudo:
    case ARM::VST1q16LowQPseudo_UPD:
    case ARM::VST1q16LowTPseudo_UPD:
    case ARM::VST1q32HighQPseudo:
    case ARM::VST1q32HighTPseudo:
    case ARM::VST1q32LowQPseudo_UPD:
    case ARM::VST1q32LowTPseudo_UPD:
    case ARM::VST1q64HighQPseudo:
    case ARM::VST1q64HighTPseudo:
    case ARM::VST1q64LowQPseudo_UPD:
    case ARM::VST1q64LowTPseudo_UPD:
    case ARM::VST1q8HighQPseudo:
    case ARM::VST1q8HighTPseudo:
    case ARM::VST1q8LowQPseudo_UPD:
    case ARM::VST1q8LowTPseudo_UPD:
    case ARM::VST2LNd16Pseudo:
    case ARM::VST2LNd16Pseudo_UPD:
    case ARM::VST2LNd32Pseudo:
    case ARM::VST2LNd32Pseudo_UPD:
    case ARM::VST2LNd8Pseudo:
    case ARM::VST2LNd8Pseudo_UPD:
    case ARM::VST2LNq16Pseudo:
    case ARM::VST2LNq16Pseudo_UPD:
    case ARM::VST2LNq32Pseudo:
    case ARM::VST2LNq32Pseudo_UPD:
    case ARM::VST2q16Pseudo:
    case ARM::VST2q16PseudoWB_fixed:
    case ARM::VST2q16PseudoWB_register:
    case ARM::VST2q32Pseudo:
    case ARM::VST2q32PseudoWB_fixed:
    case ARM::VST2q32PseudoWB_register:
    case ARM::VST2q8Pseudo:
    case ARM::VST2q8PseudoWB_fixed:
    case ARM::VST2q8PseudoWB_register:
    case ARM::VST3LNd16Pseudo:
    case ARM::VST3LNd16Pseudo_UPD:
    case ARM::VST3LNd32Pseudo:
    case ARM::VST3LNd32Pseudo_UPD:
    case ARM::VST3LNd8Pseudo:
    case ARM::VST3LNd8Pseudo_UPD:
    case ARM::VST3LNq16Pseudo:
    case ARM::VST3LNq16Pseudo_UPD:
    case ARM::VST3LNq32Pseudo:
    case ARM::VST3LNq32Pseudo_UPD:
    case ARM::VST3d16Pseudo:
    case ARM::VST3d16Pseudo_UPD:
    case ARM::VST3d32Pseudo:
    case ARM::VST3d32Pseudo_UPD:
    case ARM::VST3d8Pseudo:
    case ARM::VST3d8Pseudo_UPD:
    case ARM::VST3q16Pseudo_UPD:
    case ARM::VST3q16oddPseudo:
    case ARM::VST3q16oddPseudo_UPD:
    case ARM::VST3q32Pseudo_UPD:
    case ARM::VST3q32oddPseudo:
    case ARM::VST3q32oddPseudo_UPD:
    case ARM::VST3q8Pseudo_UPD:
    case ARM::VST3q8oddPseudo:
    case ARM::VST3q8oddPseudo_UPD:
    case ARM::VST4LNd16Pseudo:
    case ARM::VST4LNd16Pseudo_UPD:
    case ARM::VST4LNd32Pseudo:
    case ARM::VST4LNd32Pseudo_UPD:
    case ARM::VST4LNd8Pseudo:
    case ARM::VST4LNd8Pseudo_UPD:
    case ARM::VST4LNq16Pseudo:
    case ARM::VST4LNq16Pseudo_UPD:
    case ARM::VST4LNq32Pseudo:
    case ARM::VST4LNq32Pseudo_UPD:
    case ARM::VST4d16Pseudo:
    case ARM::VST4d16Pseudo_UPD:
    case ARM::VST4d32Pseudo:
    case ARM::VST4d32Pseudo_UPD:
    case ARM::VST4d8Pseudo:
    case ARM::VST4d8Pseudo_UPD:
    case ARM::VST4q16Pseudo_UPD:
    case ARM::VST4q16oddPseudo:
    case ARM::VST4q16oddPseudo_UPD:
    case ARM::VST4q32Pseudo_UPD:
    case ARM::VST4q32oddPseudo:
    case ARM::VST4q32oddPseudo_UPD:
    case ARM::VST4q8Pseudo_UPD:
    case ARM::VST4q8oddPseudo:
    case ARM::VST4q8oddPseudo_UPD:
    case ARM::VSTMQIA:
    case ARM::VTBL3Pseudo:
    case ARM::VTBL4Pseudo:
    case ARM::VTBX3Pseudo:
    case ARM::VTBX4Pseudo:
    case ARM::t2CLREX:
    case ARM::t2DCPS1:
    case ARM::t2DCPS2:
    case ARM::t2DCPS3:
    case ARM::t2Int_eh_sjlj_setjmp:
    case ARM::t2Int_eh_sjlj_setjmp_nofp:
    case ARM::t2SG:
    case ARM::t2TSB:
    case ARM::tInt_WIN_eh_sjlj_longjmp:
    case ARM::tInt_eh_sjlj_longjmp:
    case ARM::tInt_eh_sjlj_setjmp:
    case ARM::tTRAP:
    case ARM::t__brkdiv0: {
      break;
    }
    case ARM::VRINTAD:
    case ARM::VRINTMD:
    case ARM::VRINTND:
    case ARM::VRINTPD: {
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VMAXNMD:
    case ARM::VMINNMD:
    case ARM::VSELEQD:
    case ARM::VSELGED:
    case ARM::VSELGTD:
    case ARM::VSELVSD: {
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Dn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::CRC32B:
    case ARM::CRC32CB:
    case ARM::CRC32CH:
    case ARM::CRC32CW:
    case ARM::CRC32H:
    case ARM::CRC32W: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2MRS_AR:
    case ARM::t2MRSsys_AR: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::t2CLZ:
    case ARM::t2RBIT:
    case ARM::t2REV:
    case ARM::t2REV16:
    case ARM::t2REVSH: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2MOVsra_flag:
    case ARM::t2MOVsrl_flag: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2SXTB:
    case ARM::t2SXTB16:
    case ARM::t2SXTH:
    case ARM::t2UXTB:
    case ARM::t2UXTB16:
    case ARM::t2UXTH: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 4;
      break;
    }
    case ARM::t2CRC32B:
    case ARM::t2CRC32CB:
    case ARM::t2CRC32CH:
    case ARM::t2CRC32CW:
    case ARM::t2CRC32H:
    case ARM::t2CRC32W:
    case ARM::t2MUL:
    case ARM::t2QADD16:
    case ARM::t2QADD8:
    case ARM::t2QASX:
    case ARM::t2QSAX:
    case ARM::t2QSUB16:
    case ARM::t2QSUB8:
    case ARM::t2SADD16:
    case ARM::t2SADD8:
    case ARM::t2SASX:
    case ARM::t2SDIV:
    case ARM::t2SEL:
    case ARM::t2SHADD16:
    case ARM::t2SHADD8:
    case ARM::t2SHASX:
    case ARM::t2SHSAX:
    case ARM::t2SHSUB16:
    case ARM::t2SHSUB8:
    case ARM::t2SMMUL:
    case ARM::t2SMMULR:
    case ARM::t2SMUAD:
    case ARM::t2SMUADX:
    case ARM::t2SMULBB:
    case ARM::t2SMULBT:
    case ARM::t2SMULTB:
    case ARM::t2SMULTT:
    case ARM::t2SMULWB:
    case ARM::t2SMULWT:
    case ARM::t2SMUSD:
    case ARM::t2SMUSDX:
    case ARM::t2SSAX:
    case ARM::t2SSUB16:
    case ARM::t2SSUB8:
    case ARM::t2UADD16:
    case ARM::t2UADD8:
    case ARM::t2UASX:
    case ARM::t2UDIV:
    case ARM::t2UHADD16:
    case ARM::t2UHADD8:
    case ARM::t2UHASX:
    case ARM::t2UHSAX:
    case ARM::t2UHSUB16:
    case ARM::t2UHSUB8:
    case ARM::t2UQADD16:
    case ARM::t2UQADD8:
    case ARM::t2UQASX:
    case ARM::t2UQSAX:
    case ARM::t2UQSUB16:
    case ARM::t2UQSUB8:
    case ARM::t2USAD8:
    case ARM::t2USAX:
    case ARM::t2USUB16:
    case ARM::t2USUB8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2MLA:
    case ARM::t2MLS:
    case ARM::t2SMLABB:
    case ARM::t2SMLABT:
    case ARM::t2SMLAD:
    case ARM::t2SMLADX:
    case ARM::t2SMLATB:
    case ARM::t2SMLATT:
    case ARM::t2SMLAWB:
    case ARM::t2SMLAWT:
    case ARM::t2SMLSD:
    case ARM::t2SMLSDX:
    case ARM::t2SMMLA:
    case ARM::t2SMMLAR:
    case ARM::t2SMMLS:
    case ARM::t2SMMLSR:
    case ARM::t2USADA8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::t2SXTAB:
    case ARM::t2SXTAB16:
    case ARM::t2SXTAH:
    case ARM::t2UXTAB:
    case ARM::t2UXTAB16:
    case ARM::t2UXTAH: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 4;
      break;
    }
    case ARM::t2PKHBT:
    case ARM::t2PKHTB: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: sh
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      break;
    }
    case ARM::t2ADDri12:
    case ARM::t2SUBri12: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2QADD:
    case ARM::t2QDADD:
    case ARM::t2QDSUB:
    case ARM::t2QSUB: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2BFI: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      Value |= (op & UINT64_C(992)) >> 5;
      break;
    }
    case ARM::t2SSAT16:
    case ARM::t2USAT16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: sat_imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2SSAT:
    case ARM::t2USAT: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: sat_imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(31);
      // op: sh
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(32)) << 16;
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      break;
    }
    case ARM::t2STREX: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(3840)) << 8;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2MRS_M: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: SYSm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2ADR: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getT2AdrLabelOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(4096)) << 9;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2BFC: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: imm
      op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      Value |= (op & UINT64_C(992)) >> 5;
      break;
    }
    case ARM::t2MOVi16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: imm
      op = getHiLo16ImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2MOVTi16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: imm
      op = getHiLo16ImmOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2SBFX:
    case ARM::t2UBFX: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: msb
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(31);
      // op: lsb
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::tADR: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: addr
      op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tMOVi8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tMOVr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(8)) << 4;
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      break;
    }
    case ARM::t2STLEX: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::t2STLEXB:
    case ARM::t2STLEXH:
    case ARM::t2STREXB:
    case ARM::t2STREXH: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::t2STLEXD:
    case ARM::t2STREXD: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::tMOVSr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      break;
    }
    case ARM::tADDi3:
    case ARM::tSUBi3: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 6;
      break;
    }
    case ARM::tASRri:
    case ARM::tLSLri:
    case ARM::tLSRri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 6;
      break;
    }
    case ARM::tMUL:
    case ARM::tMVN:
    case ARM::tRSB: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      break;
    }
    case ARM::t2SMLALD:
    case ARM::t2SMLALDX:
    case ARM::t2SMLSLD:
    case ARM::t2SMLSLDX: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::t2SMLAL:
    case ARM::t2SMLALBB:
    case ARM::t2SMLALBT:
    case ARM::t2SMLALTB:
    case ARM::t2SMLALTT:
    case ARM::t2SMULL:
    case ARM::t2UMAAL:
    case ARM::t2UMLAL:
    case ARM::t2UMULL: {
      // op: RdLo
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: RdHi
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tADDi8:
    case ARM::tSUBi8: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tADDrSP: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(8)) << 4;
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::tADDhirr: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(8)) << 4;
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      break;
    }
    case ARM::tADC:
    case ARM::tAND:
    case ARM::tASRrr:
    case ARM::tBIC:
    case ARM::tEOR:
    case ARM::tLSLrr:
    case ARM::tLSRrr:
    case ARM::tORR:
    case ARM::tROR:
    case ARM::tSBC: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      break;
    }
    case ARM::tBX:
    case ARM::tBXNS: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      break;
    }
    case ARM::tCMPhir: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(8)) << 4;
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::tREV:
    case ARM::tREV16:
    case ARM::tREVSH:
    case ARM::tSXTB:
    case ARM::tSXTH:
    case ARM::tUXTB:
    case ARM::tUXTH: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::tCMNz:
    case ARM::tCMPr:
    case ARM::tTST: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::tADDspr: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      break;
    }
    case ARM::tADDrr:
    case ARM::tSUBrr: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 6;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 3;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::RFEDA:
    case ARM::RFEDA_UPD:
    case ARM::RFEDB:
    case ARM::RFEDB_UPD:
    case ARM::RFEIA:
    case ARM::RFEIA_UPD:
    case ARM::RFEIB:
    case ARM::RFEIB_UPD:
    case ARM::t2RFEDB:
    case ARM::t2RFEDBW:
    case ARM::t2RFEIA:
    case ARM::t2RFEIAW: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::t2CMNzrr:
    case ARM::t2CMPrr:
    case ARM::t2TBB:
    case ARM::t2TBH:
    case ARM::t2TEQrr:
    case ARM::t2TSTrr: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2CMNzrs:
    case ARM::t2CMPrs:
    case ARM::t2TEQrs:
    case ARM::t2TSTrs: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: ShiftedRm
      op = getT2SORegOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(3584)) << 3;
      Value |= (op & UINT64_C(480)) >> 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2CMNri:
    case ARM::t2CMPri:
    case ARM::t2TEQri:
    case ARM::t2TSTri: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getT2SOImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2STMDB:
    case ARM::t2STMIA: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(16384);
      Value |= op & UINT64_C(8191);
      break;
    }
    case ARM::t2LDMDB:
    case ARM::t2LDMIA: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(65535);
      break;
    }
    case ARM::tCMPi8: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tLDMIA: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2TT:
    case ARM::t2TTA:
    case ARM::t2TTAT:
    case ARM::t2TTT: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::t2STMDB_UPD:
    case ARM::t2STMIA_UPD: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(16384);
      Value |= op & UINT64_C(8191);
      break;
    }
    case ARM::t2LDMDB_UPD:
    case ARM::t2LDMIA_UPD: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(65535);
      break;
    }
    case ARM::tSTMIA_UPD: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRB_POST:
    case ARM::t2LDRH_POST:
    case ARM::t2LDRSB_POST:
    case ARM::t2LDRSH_POST:
    case ARM::t2LDR_POST: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: offset
      op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 1;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::MRRC2:
    case ARM::t2MRRC:
    case ARM::t2MRRC2: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2LDRD_POST: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getT2Imm8s4OpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRDi8:
    case ARM::t2STRDi8: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRD_PRE: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRBi12:
    case ARM::t2LDRHi12:
    case ARM::t2LDRSBi12:
    case ARM::t2LDRSHi12:
    case ARM::t2LDRi12:
    case ARM::t2STRBi12:
    case ARM::t2STRHi12:
    case ARM::t2STRi12: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::t2LDRBpci:
    case ARM::t2LDRHpci:
    case ARM::t2LDRSBpci:
    case ARM::t2LDRSHpci:
    case ARM::t2LDRpci: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::t2LDA:
    case ARM::t2LDAB:
    case ARM::t2LDAEX:
    case ARM::t2LDAH:
    case ARM::t2STL:
    case ARM::t2STLB:
    case ARM::t2STLH: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::t2LDREX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(3840)) << 8;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRBi8:
    case ARM::t2LDRHi8:
    case ARM::t2LDRSBi8:
    case ARM::t2LDRSHi8:
    case ARM::t2LDRi8:
    case ARM::t2STRBi8:
    case ARM::t2STRHi8:
    case ARM::t2STRi8: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(256)) << 1;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRBT:
    case ARM::t2LDRHT:
    case ARM::t2LDRSBT:
    case ARM::t2LDRSHT:
    case ARM::t2LDRT:
    case ARM::t2STRBT:
    case ARM::t2STRHT:
    case ARM::t2STRT: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRB_PRE:
    case ARM::t2LDRH_PRE:
    case ARM::t2LDRSB_PRE:
    case ARM::t2LDRSH_PRE:
    case ARM::t2LDR_PRE: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(256)) << 1;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2LDRBs:
    case ARM::t2LDRHs:
    case ARM::t2LDRSBs:
    case ARM::t2LDRSHs:
    case ARM::t2LDRs:
    case ARM::t2STRBs:
    case ARM::t2STRHs:
    case ARM::t2STRs: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(960)) << 10;
      Value |= (op & UINT64_C(3)) << 4;
      Value |= (op & UINT64_C(60)) >> 2;
      break;
    }
    case ARM::MRC2:
    case ARM::t2MRC:
    case ARM::t2MRC2: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 21;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::tLDRpci: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: addr
      op = getAddrModePCOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tLDRspi:
    case ARM::tSTRspi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: addr
      op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tLDRBi:
    case ARM::tLDRHi:
    case ARM::tLDRi:
    case ARM::tSTRBi:
    case ARM::tSTRHi:
    case ARM::tSTRi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: addr
      op = getAddrModeISOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(255)) << 3;
      break;
    }
    case ARM::tLDRBr:
    case ARM::tLDRHr:
    case ARM::tLDRSB:
    case ARM::tLDRSH:
    case ARM::tLDRr:
    case ARM::tSTRBr:
    case ARM::tSTRHr:
    case ARM::tSTRr: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: addr
      op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(63)) << 3;
      break;
    }
    case ARM::t2STRB_POST:
    case ARM::t2STRH_POST:
    case ARM::t2STR_POST: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: offset
      op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 1;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2STRD_POST: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getT2Imm8s4OpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2STRD_PRE: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: addr
      op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2STRB_PRE:
    case ARM::t2STRH_PRE:
    case ARM::t2STR_PRE: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(256)) << 1;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::MCRR2:
    case ARM::t2MCRR:
    case ARM::t2MCRR2: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MCR2:
    case ARM::t2MCR:
    case ARM::t2MCR2: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 21;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::t2MSR_M: {
      // op: SYSm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(3072);
      Value |= op & UINT64_C(255);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::VCVTASD:
    case ARM::VCVTAUD:
    case ARM::VCVTMSD:
    case ARM::VCVTMUD:
    case ARM::VCVTNSD:
    case ARM::VCVTNUD:
    case ARM::VCVTPSD:
    case ARM::VCVTPUD: {
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VCVTASH:
    case ARM::VCVTASS:
    case ARM::VCVTAUH:
    case ARM::VCVTAUS:
    case ARM::VCVTMSH:
    case ARM::VCVTMSS:
    case ARM::VCVTMUH:
    case ARM::VCVTMUS:
    case ARM::VCVTNSH:
    case ARM::VCVTNSS:
    case ARM::VCVTNUH:
    case ARM::VCVTNUS:
    case ARM::VCVTPSH:
    case ARM::VCVTPSS:
    case ARM::VCVTPUH:
    case ARM::VCVTPUS:
    case ARM::VINSH:
    case ARM::VMOVH:
    case ARM::VRINTAH:
    case ARM::VRINTAS:
    case ARM::VRINTMH:
    case ARM::VRINTMS:
    case ARM::VRINTNH:
    case ARM::VRINTNS:
    case ARM::VRINTPH:
    case ARM::VRINTPS: {
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      break;
    }
    case ARM::VMAXNMH:
    case ARM::VMAXNMS:
    case ARM::VMINNMH:
    case ARM::VMINNMS:
    case ARM::VSELEQH:
    case ARM::VSELEQS:
    case ARM::VSELGEH:
    case ARM::VSELGES:
    case ARM::VSELGTH:
    case ARM::VSELGTS:
    case ARM::VSELVSH:
    case ARM::VSELVSS: {
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Sn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(30)) << 15;
      Value |= (op & UINT64_C(1)) << 7;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      break;
    }
    case ARM::VDUP16d:
    case ARM::VDUP16q:
    case ARM::VDUP32d:
    case ARM::VDUP32q:
    case ARM::VDUP8d:
    case ARM::VDUP8q: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSETLNi32: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 21;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSETLNi16: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(2)) << 20;
      Value |= (op & UINT64_C(1)) << 6;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSETLNi8: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(4)) << 19;
      Value |= (op & UINT64_C(3)) << 5;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VGETLNi32: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 21;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VGETLNs16:
    case ARM::VGETLNu16: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(2)) << 20;
      Value |= (op & UINT64_C(1)) << 6;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VGETLNs8:
    case ARM::VGETLNu8: {
      // op: V
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: R
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(4)) << 19;
      Value |= (op & UINT64_C(3)) << 5;
      Value = NEONThumb2DupPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16:
    case ARM::VLD1d16T:
    case ARM::VLD1d32:
    case ARM::VLD1d32T:
    case ARM::VLD1d64:
    case ARM::VLD1d64T:
    case ARM::VLD1d8:
    case ARM::VLD1d8T: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16Q:
    case ARM::VLD1d32Q:
    case ARM::VLD1d64Q:
    case ARM::VLD1d8Q:
    case ARM::VLD1q16:
    case ARM::VLD1q32:
    case ARM::VLD1q64:
    case ARM::VLD1q8:
    case ARM::VLD2b16:
    case ARM::VLD2b32:
    case ARM::VLD2b8:
    case ARM::VLD2d16:
    case ARM::VLD2d32:
    case ARM::VLD2d8:
    case ARM::VLD2q16:
    case ARM::VLD2q32:
    case ARM::VLD2q8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16Twb_register:
    case ARM::VLD1d16wb_register:
    case ARM::VLD1d32Twb_register:
    case ARM::VLD1d32wb_register:
    case ARM::VLD1d64Twb_register:
    case ARM::VLD1d64wb_register:
    case ARM::VLD1d8Twb_register:
    case ARM::VLD1d8wb_register: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd32:
    case ARM::VLD2LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd16:
    case ARM::VLD2LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16Twb_fixed:
    case ARM::VLD1d16wb_fixed:
    case ARM::VLD1d32Twb_fixed:
    case ARM::VLD1d32wb_fixed:
    case ARM::VLD1d64Twb_fixed:
    case ARM::VLD1d64wb_fixed:
    case ARM::VLD1d8Twb_fixed:
    case ARM::VLD1d8wb_fixed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16Qwb_register:
    case ARM::VLD1d32Qwb_register:
    case ARM::VLD1d64Qwb_register:
    case ARM::VLD1d8Qwb_register:
    case ARM::VLD1q16wb_register:
    case ARM::VLD1q32wb_register:
    case ARM::VLD1q64wb_register:
    case ARM::VLD1q8wb_register:
    case ARM::VLD2b16wb_register:
    case ARM::VLD2b32wb_register:
    case ARM::VLD2b8wb_register:
    case ARM::VLD2d16wb_register:
    case ARM::VLD2d32wb_register:
    case ARM::VLD2d8wb_register:
    case ARM::VLD2q16wb_register:
    case ARM::VLD2q32wb_register:
    case ARM::VLD2q8wb_register: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1d16Qwb_fixed:
    case ARM::VLD1d32Qwb_fixed:
    case ARM::VLD1d64Qwb_fixed:
    case ARM::VLD1d8Qwb_fixed:
    case ARM::VLD1q16wb_fixed:
    case ARM::VLD1q32wb_fixed:
    case ARM::VLD1q64wb_fixed:
    case ARM::VLD1q8wb_fixed:
    case ARM::VLD2b16wb_fixed:
    case ARM::VLD2b32wb_fixed:
    case ARM::VLD2b8wb_fixed:
    case ARM::VLD2d16wb_fixed:
    case ARM::VLD2d32wb_fixed:
    case ARM::VLD2d8wb_fixed:
    case ARM::VLD2q16wb_fixed:
    case ARM::VLD2q32wb_fixed:
    case ARM::VLD2q8wb_fixed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd32:
    case ARM::VLD3LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd16:
    case ARM::VLD3LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd32_UPD:
    case ARM::VLD2LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd16_UPD:
    case ARM::VLD2LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD2LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3d16:
    case ARM::VLD3d32:
    case ARM::VLD3d8:
    case ARM::VLD3q16:
    case ARM::VLD3q32:
    case ARM::VLD3q8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd32_UPD:
    case ARM::VLD3LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd16_UPD:
    case ARM::VLD3LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3d16_UPD:
    case ARM::VLD3d32_UPD:
    case ARM::VLD3d8_UPD:
    case ARM::VLD3q16_UPD:
    case ARM::VLD3q32_UPD:
    case ARM::VLD3q8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd16:
    case ARM::VLD4LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd32:
    case ARM::VLD4LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4d16:
    case ARM::VLD4d32:
    case ARM::VLD4d8:
    case ARM::VLD4q16:
    case ARM::VLD4q32:
    case ARM::VLD4q8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd16_UPD:
    case ARM::VLD4LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4LNd32_UPD:
    case ARM::VLD4LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4d16_UPD:
    case ARM::VLD4d32_UPD:
    case ARM::VLD4d8_UPD:
    case ARM::VLD4q16_UPD:
    case ARM::VLD4q32_UPD:
    case ARM::VLD4q8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1DUPd16:
    case ARM::VLD1DUPd32:
    case ARM::VLD1DUPd8:
    case ARM::VLD1DUPq16:
    case ARM::VLD1DUPq32:
    case ARM::VLD1DUPq8:
    case ARM::VLD2DUPd16:
    case ARM::VLD2DUPd16x2:
    case ARM::VLD2DUPd32:
    case ARM::VLD2DUPd32x2:
    case ARM::VLD2DUPd8:
    case ARM::VLD2DUPd8x2: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1DUPd16wb_register:
    case ARM::VLD1DUPd32wb_register:
    case ARM::VLD1DUPd8wb_register:
    case ARM::VLD1DUPq16wb_register:
    case ARM::VLD1DUPq32wb_register:
    case ARM::VLD1DUPq8wb_register:
    case ARM::VLD2DUPd16wb_register:
    case ARM::VLD2DUPd16x2wb_register:
    case ARM::VLD2DUPd32wb_register:
    case ARM::VLD2DUPd32x2wb_register:
    case ARM::VLD2DUPd8wb_register:
    case ARM::VLD2DUPd8x2wb_register: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1DUPd16wb_fixed:
    case ARM::VLD1DUPd32wb_fixed:
    case ARM::VLD1DUPd8wb_fixed:
    case ARM::VLD1DUPq16wb_fixed:
    case ARM::VLD1DUPq32wb_fixed:
    case ARM::VLD1DUPq8wb_fixed:
    case ARM::VLD2DUPd16wb_fixed:
    case ARM::VLD2DUPd16x2wb_fixed:
    case ARM::VLD2DUPd32wb_fixed:
    case ARM::VLD2DUPd32x2wb_fixed:
    case ARM::VLD2DUPd8wb_fixed:
    case ARM::VLD2DUPd8x2wb_fixed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3DUPd16:
    case ARM::VLD3DUPd32:
    case ARM::VLD3DUPd8:
    case ARM::VLD3DUPq16:
    case ARM::VLD3DUPq32:
    case ARM::VLD3DUPq8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD3DUPd16_UPD:
    case ARM::VLD3DUPd32_UPD:
    case ARM::VLD3DUPd8_UPD:
    case ARM::VLD3DUPq16_UPD:
    case ARM::VLD3DUPq32_UPD:
    case ARM::VLD3DUPq8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4DUPd32:
    case ARM::VLD4DUPq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(32)) << 1;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4DUPd16:
    case ARM::VLD4DUPd8:
    case ARM::VLD4DUPq16:
    case ARM::VLD4DUPq8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4DUPd32_UPD:
    case ARM::VLD4DUPq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(32)) << 1;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD4DUPd16_UPD:
    case ARM::VLD4DUPd8_UPD:
    case ARM::VLD4DUPq16_UPD:
    case ARM::VLD4DUPq8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLD1LNd32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVv16i8:
    case ARM::VMOVv1i64:
    case ARM::VMOVv2f32:
    case ARM::VMOVv2i64:
    case ARM::VMOVv4f32:
    case ARM::VMOVv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(128)) << 17;
      Value |= (op & UINT64_C(112)) << 12;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VBICiv2i32:
    case ARM::VBICiv4i32:
    case ARM::VORRiv2i32:
    case ARM::VORRiv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(128)) << 17;
      Value |= (op & UINT64_C(112)) << 12;
      Value |= op & UINT64_C(1536);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVv2i32:
    case ARM::VMOVv4i32:
    case ARM::VMVNv2i32:
    case ARM::VMVNv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(128)) << 17;
      Value |= (op & UINT64_C(112)) << 12;
      Value |= op & UINT64_C(3840);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VBICiv4i16:
    case ARM::VBICiv8i16:
    case ARM::VMOVv4i16:
    case ARM::VMOVv8i16:
    case ARM::VMVNv4i16:
    case ARM::VMVNv8i16:
    case ARM::VORRiv4i16:
    case ARM::VORRiv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(128)) << 17;
      Value |= (op & UINT64_C(112)) << 12;
      Value |= op & UINT64_C(512);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQSHLsiv4i16:
    case ARM::VQSHLsiv8i16:
    case ARM::VQSHLsuv4i16:
    case ARM::VQSHLsuv8i16:
    case ARM::VQSHLuiv4i16:
    case ARM::VQSHLuiv8i16:
    case ARM::VSHLLsv4i32:
    case ARM::VSHLLuv4i32:
    case ARM::VSHLiv4i16:
    case ARM::VSHLiv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQSHLsiv2i32:
    case ARM::VQSHLsiv4i32:
    case ARM::VQSHLsuv2i32:
    case ARM::VQSHLsuv4i32:
    case ARM::VQSHLuiv2i32:
    case ARM::VQSHLuiv4i32:
    case ARM::VSHLLsv2i64:
    case ARM::VSHLLuv2i64:
    case ARM::VSHLiv2i32:
    case ARM::VSHLiv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQSHLsiv1i64:
    case ARM::VQSHLsiv2i64:
    case ARM::VQSHLsuv1i64:
    case ARM::VQSHLsuv2i64:
    case ARM::VQSHLuiv1i64:
    case ARM::VQSHLuiv2i64:
    case ARM::VSHLiv1i64:
    case ARM::VSHLiv2i64: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(63)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQSHLsiv16i8:
    case ARM::VQSHLsiv8i8:
    case ARM::VQSHLsuv16i8:
    case ARM::VQSHLsuv8i8:
    case ARM::VQSHLuiv16i8:
    case ARM::VQSHLuiv8i8:
    case ARM::VSHLLsv8i16:
    case ARM::VSHLLuv8i16:
    case ARM::VSHLiv16i8:
    case ARM::VSHLiv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCVTf2xsd:
    case ARM::VCVTf2xsq:
    case ARM::VCVTf2xud:
    case ARM::VCVTf2xuq:
    case ARM::VCVTh2xsd:
    case ARM::VCVTh2xsq:
    case ARM::VCVTh2xud:
    case ARM::VCVTh2xuq:
    case ARM::VCVTxs2fd:
    case ARM::VCVTxs2fq:
    case ARM::VCVTxs2hd:
    case ARM::VCVTxs2hq:
    case ARM::VCVTxu2fd:
    case ARM::VCVTxu2fq:
    case ARM::VCVTxu2hd:
    case ARM::VCVTxu2hq: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(63)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQRSHRNsv4i16:
    case ARM::VQRSHRNuv4i16:
    case ARM::VQRSHRUNv4i16:
    case ARM::VQSHRNsv4i16:
    case ARM::VQSHRNuv4i16:
    case ARM::VQSHRUNv4i16:
    case ARM::VRSHRNv4i16:
    case ARM::VRSHRsv4i16:
    case ARM::VRSHRsv8i16:
    case ARM::VRSHRuv4i16:
    case ARM::VRSHRuv8i16:
    case ARM::VSHRNv4i16:
    case ARM::VSHRsv4i16:
    case ARM::VSHRsv8i16:
    case ARM::VSHRuv4i16:
    case ARM::VSHRuv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight16Imm(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQRSHRNsv2i32:
    case ARM::VQRSHRNuv2i32:
    case ARM::VQRSHRUNv2i32:
    case ARM::VQSHRNsv2i32:
    case ARM::VQSHRNuv2i32:
    case ARM::VQSHRUNv2i32:
    case ARM::VRSHRNv2i32:
    case ARM::VRSHRsv2i32:
    case ARM::VRSHRsv4i32:
    case ARM::VRSHRuv2i32:
    case ARM::VRSHRuv4i32:
    case ARM::VSHRNv2i32:
    case ARM::VSHRsv2i32:
    case ARM::VSHRsv4i32:
    case ARM::VSHRuv2i32:
    case ARM::VSHRuv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight32Imm(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VRSHRsv1i64:
    case ARM::VRSHRsv2i64:
    case ARM::VRSHRuv1i64:
    case ARM::VRSHRuv2i64:
    case ARM::VSHRsv1i64:
    case ARM::VSHRsv2i64:
    case ARM::VSHRuv1i64:
    case ARM::VSHRuv2i64: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight64Imm(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(63)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQRSHRNsv8i8:
    case ARM::VQRSHRNuv8i8:
    case ARM::VQRSHRUNv8i8:
    case ARM::VQSHRNsv8i8:
    case ARM::VQSHRNuv8i8:
    case ARM::VQSHRUNv8i8:
    case ARM::VRSHRNv8i8:
    case ARM::VRSHRsv16i8:
    case ARM::VRSHRsv8i8:
    case ARM::VRSHRuv16i8:
    case ARM::VRSHRuv8i8:
    case ARM::VSHRNv8i8:
    case ARM::VSHRsv16i8:
    case ARM::VSHRsv8i8:
    case ARM::VSHRuv16i8:
    case ARM::VSHRuv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight8Imm(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(7)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VDUPLN32d:
    case ARM::VDUPLN32q: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 19;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VDUPLN16d:
    case ARM::VDUPLN16q: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 18;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VDUPLN8d:
    case ARM::VDUPLN8q: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 17;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::AESIMC:
    case ARM::AESMC:
    case ARM::SHA1H:
    case ARM::VABSfd:
    case ARM::VABSfq:
    case ARM::VABShd:
    case ARM::VABShq:
    case ARM::VABSv16i8:
    case ARM::VABSv2i32:
    case ARM::VABSv4i16:
    case ARM::VABSv4i32:
    case ARM::VABSv8i16:
    case ARM::VABSv8i8:
    case ARM::VCEQzv16i8:
    case ARM::VCEQzv2f32:
    case ARM::VCEQzv2i32:
    case ARM::VCEQzv4f16:
    case ARM::VCEQzv4f32:
    case ARM::VCEQzv4i16:
    case ARM::VCEQzv4i32:
    case ARM::VCEQzv8f16:
    case ARM::VCEQzv8i16:
    case ARM::VCEQzv8i8:
    case ARM::VCGEzv16i8:
    case ARM::VCGEzv2f32:
    case ARM::VCGEzv2i32:
    case ARM::VCGEzv4f16:
    case ARM::VCGEzv4f32:
    case ARM::VCGEzv4i16:
    case ARM::VCGEzv4i32:
    case ARM::VCGEzv8f16:
    case ARM::VCGEzv8i16:
    case ARM::VCGEzv8i8:
    case ARM::VCGTzv16i8:
    case ARM::VCGTzv2f32:
    case ARM::VCGTzv2i32:
    case ARM::VCGTzv4f16:
    case ARM::VCGTzv4f32:
    case ARM::VCGTzv4i16:
    case ARM::VCGTzv4i32:
    case ARM::VCGTzv8f16:
    case ARM::VCGTzv8i16:
    case ARM::VCGTzv8i8:
    case ARM::VCLEzv16i8:
    case ARM::VCLEzv2f32:
    case ARM::VCLEzv2i32:
    case ARM::VCLEzv4f16:
    case ARM::VCLEzv4f32:
    case ARM::VCLEzv4i16:
    case ARM::VCLEzv4i32:
    case ARM::VCLEzv8f16:
    case ARM::VCLEzv8i16:
    case ARM::VCLEzv8i8:
    case ARM::VCLSv16i8:
    case ARM::VCLSv2i32:
    case ARM::VCLSv4i16:
    case ARM::VCLSv4i32:
    case ARM::VCLSv8i16:
    case ARM::VCLSv8i8:
    case ARM::VCLTzv16i8:
    case ARM::VCLTzv2f32:
    case ARM::VCLTzv2i32:
    case ARM::VCLTzv4f16:
    case ARM::VCLTzv4f32:
    case ARM::VCLTzv4i16:
    case ARM::VCLTzv4i32:
    case ARM::VCLTzv8f16:
    case ARM::VCLTzv8i16:
    case ARM::VCLTzv8i8:
    case ARM::VCLZv16i8:
    case ARM::VCLZv2i32:
    case ARM::VCLZv4i16:
    case ARM::VCLZv4i32:
    case ARM::VCLZv8i16:
    case ARM::VCLZv8i8:
    case ARM::VCNTd:
    case ARM::VCNTq:
    case ARM::VCVTf2h:
    case ARM::VCVTf2sd:
    case ARM::VCVTf2sq:
    case ARM::VCVTf2ud:
    case ARM::VCVTf2uq:
    case ARM::VCVTh2f:
    case ARM::VCVTh2sd:
    case ARM::VCVTh2sq:
    case ARM::VCVTh2ud:
    case ARM::VCVTh2uq:
    case ARM::VCVTs2fd:
    case ARM::VCVTs2fq:
    case ARM::VCVTs2hd:
    case ARM::VCVTs2hq:
    case ARM::VCVTu2fd:
    case ARM::VCVTu2fq:
    case ARM::VCVTu2hd:
    case ARM::VCVTu2hq:
    case ARM::VMOVLsv2i64:
    case ARM::VMOVLsv4i32:
    case ARM::VMOVLsv8i16:
    case ARM::VMOVLuv2i64:
    case ARM::VMOVLuv4i32:
    case ARM::VMOVLuv8i16:
    case ARM::VMOVNv2i32:
    case ARM::VMOVNv4i16:
    case ARM::VMOVNv8i8:
    case ARM::VMVNd:
    case ARM::VMVNq:
    case ARM::VNEGf32q:
    case ARM::VNEGfd:
    case ARM::VNEGhd:
    case ARM::VNEGhq:
    case ARM::VNEGs16d:
    case ARM::VNEGs16q:
    case ARM::VNEGs32d:
    case ARM::VNEGs32q:
    case ARM::VNEGs8d:
    case ARM::VNEGs8q:
    case ARM::VPADDLsv16i8:
    case ARM::VPADDLsv2i32:
    case ARM::VPADDLsv4i16:
    case ARM::VPADDLsv4i32:
    case ARM::VPADDLsv8i16:
    case ARM::VPADDLsv8i8:
    case ARM::VPADDLuv16i8:
    case ARM::VPADDLuv2i32:
    case ARM::VPADDLuv4i16:
    case ARM::VPADDLuv4i32:
    case ARM::VPADDLuv8i16:
    case ARM::VPADDLuv8i8:
    case ARM::VQABSv16i8:
    case ARM::VQABSv2i32:
    case ARM::VQABSv4i16:
    case ARM::VQABSv4i32:
    case ARM::VQABSv8i16:
    case ARM::VQABSv8i8:
    case ARM::VQMOVNsuv2i32:
    case ARM::VQMOVNsuv4i16:
    case ARM::VQMOVNsuv8i8:
    case ARM::VQMOVNsv2i32:
    case ARM::VQMOVNsv4i16:
    case ARM::VQMOVNsv8i8:
    case ARM::VQMOVNuv2i32:
    case ARM::VQMOVNuv4i16:
    case ARM::VQMOVNuv8i8:
    case ARM::VQNEGv16i8:
    case ARM::VQNEGv2i32:
    case ARM::VQNEGv4i16:
    case ARM::VQNEGv4i32:
    case ARM::VQNEGv8i16:
    case ARM::VQNEGv8i8:
    case ARM::VRECPEd:
    case ARM::VRECPEfd:
    case ARM::VRECPEfq:
    case ARM::VRECPEhd:
    case ARM::VRECPEhq:
    case ARM::VRECPEq:
    case ARM::VREV16d8:
    case ARM::VREV16q8:
    case ARM::VREV32d16:
    case ARM::VREV32d8:
    case ARM::VREV32q16:
    case ARM::VREV32q8:
    case ARM::VREV64d16:
    case ARM::VREV64d32:
    case ARM::VREV64d8:
    case ARM::VREV64q16:
    case ARM::VREV64q32:
    case ARM::VREV64q8:
    case ARM::VRSQRTEd:
    case ARM::VRSQRTEfd:
    case ARM::VRSQRTEfq:
    case ARM::VRSQRTEhd:
    case ARM::VRSQRTEhq:
    case ARM::VRSQRTEq:
    case ARM::VSHLLi16:
    case ARM::VSHLLi32:
    case ARM::VSHLLi8:
    case ARM::VSWPd:
    case ARM::VSWPq:
    case ARM::VTRNd16:
    case ARM::VTRNd32:
    case ARM::VTRNd8:
    case ARM::VTRNq16:
    case ARM::VTRNq32:
    case ARM::VTRNq8:
    case ARM::VUZPd16:
    case ARM::VUZPd8:
    case ARM::VUZPq16:
    case ARM::VUZPq32:
    case ARM::VUZPq8:
    case ARM::VZIPd16:
    case ARM::VZIPd8:
    case ARM::VZIPq16:
    case ARM::VZIPq32:
    case ARM::VZIPq8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCVTANSDf:
    case ARM::VCVTANSDh:
    case ARM::VCVTANSQf:
    case ARM::VCVTANSQh:
    case ARM::VCVTANUDf:
    case ARM::VCVTANUDh:
    case ARM::VCVTANUQf:
    case ARM::VCVTANUQh:
    case ARM::VCVTMNSDf:
    case ARM::VCVTMNSDh:
    case ARM::VCVTMNSQf:
    case ARM::VCVTMNSQh:
    case ARM::VCVTMNUDf:
    case ARM::VCVTMNUDh:
    case ARM::VCVTMNUQf:
    case ARM::VCVTMNUQh:
    case ARM::VCVTNNSDf:
    case ARM::VCVTNNSDh:
    case ARM::VCVTNNSQf:
    case ARM::VCVTNNSQh:
    case ARM::VCVTNNUDf:
    case ARM::VCVTNNUDh:
    case ARM::VCVTNNUQf:
    case ARM::VCVTNNUQh:
    case ARM::VCVTPNSDf:
    case ARM::VCVTPNSDh:
    case ARM::VCVTPNSQf:
    case ARM::VCVTPNSQh:
    case ARM::VCVTPNUDf:
    case ARM::VCVTPNUDh:
    case ARM::VCVTPNUQf:
    case ARM::VCVTPNUQh:
    case ARM::VRINTANDf:
    case ARM::VRINTANDh:
    case ARM::VRINTANQf:
    case ARM::VRINTANQh:
    case ARM::VRINTMNDf:
    case ARM::VRINTMNDh:
    case ARM::VRINTMNQf:
    case ARM::VRINTMNQh:
    case ARM::VRINTNNDf:
    case ARM::VRINTNNDh:
    case ARM::VRINTNNQf:
    case ARM::VRINTNNQh:
    case ARM::VRINTPNDf:
    case ARM::VRINTPNDh:
    case ARM::VRINTPNQf:
    case ARM::VRINTPNQh:
    case ARM::VRINTXNDf:
    case ARM::VRINTXNDh:
    case ARM::VRINTXNQf:
    case ARM::VRINTXNQh:
    case ARM::VRINTZNDf:
    case ARM::VRINTZNDh:
    case ARM::VRINTZNQf:
    case ARM::VRINTZNQh: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2V8PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSLIv4i16:
    case ARM::VSLIv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSLIv2i32:
    case ARM::VSLIv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSLIv1i64:
    case ARM::VSLIv2i64: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(63)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSLIv16i8:
    case ARM::VSLIv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VRSRAsv4i16:
    case ARM::VRSRAsv8i16:
    case ARM::VRSRAuv4i16:
    case ARM::VRSRAuv8i16:
    case ARM::VSRAsv4i16:
    case ARM::VSRAsv8i16:
    case ARM::VSRAuv4i16:
    case ARM::VSRAuv8i16:
    case ARM::VSRIv4i16:
    case ARM::VSRIv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight16Imm(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VRSRAsv2i32:
    case ARM::VRSRAsv4i32:
    case ARM::VRSRAuv2i32:
    case ARM::VRSRAuv4i32:
    case ARM::VSRAsv2i32:
    case ARM::VSRAsv4i32:
    case ARM::VSRAuv2i32:
    case ARM::VSRAuv4i32:
    case ARM::VSRIv2i32:
    case ARM::VSRIv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight32Imm(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VRSRAsv1i64:
    case ARM::VRSRAsv2i64:
    case ARM::VRSRAuv1i64:
    case ARM::VRSRAuv2i64:
    case ARM::VSRAsv1i64:
    case ARM::VSRAsv2i64:
    case ARM::VSRAuv1i64:
    case ARM::VSRAuv2i64:
    case ARM::VSRIv1i64:
    case ARM::VSRIv2i64: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight64Imm(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(63)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VRSRAsv16i8:
    case ARM::VRSRAsv8i8:
    case ARM::VRSRAuv16i8:
    case ARM::VRSRAuv8i8:
    case ARM::VSRAsv16i8:
    case ARM::VSRAsv8i8:
    case ARM::VSRAuv16i8:
    case ARM::VSRAuv8i8:
    case ARM::VSRIv16i8:
    case ARM::VSRIv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: SIMM
      op = getShiftRight8Imm(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(7)) << 16;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::AESD:
    case ARM::AESE:
    case ARM::SHA1SU1:
    case ARM::SHA256SU0:
    case ARM::VPADALsv16i8:
    case ARM::VPADALsv2i32:
    case ARM::VPADALsv4i16:
    case ARM::VPADALsv4i32:
    case ARM::VPADALsv8i16:
    case ARM::VPADALsv8i8:
    case ARM::VPADALuv16i8:
    case ARM::VPADALuv2i32:
    case ARM::VPADALuv4i16:
    case ARM::VPADALuv4i32:
    case ARM::VPADALuv8i16:
    case ARM::VPADALuv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTd32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 10;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTq64: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 11;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTq8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 10;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTd16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 9;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VEXTq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 9;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCADDv2f32:
    case ARM::VCADDv4f16:
    case ARM::VCADDv4f32:
    case ARM::VCADDv8f16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 24;
      break;
    }
    case ARM::VABDLsv2i64:
    case ARM::VABDLsv4i32:
    case ARM::VABDLsv8i16:
    case ARM::VABDLuv2i64:
    case ARM::VABDLuv4i32:
    case ARM::VABDLuv8i16:
    case ARM::VABDfd:
    case ARM::VABDfq:
    case ARM::VABDhd:
    case ARM::VABDhq:
    case ARM::VABDsv16i8:
    case ARM::VABDsv2i32:
    case ARM::VABDsv4i16:
    case ARM::VABDsv4i32:
    case ARM::VABDsv8i16:
    case ARM::VABDsv8i8:
    case ARM::VABDuv16i8:
    case ARM::VABDuv2i32:
    case ARM::VABDuv4i16:
    case ARM::VABDuv4i32:
    case ARM::VABDuv8i16:
    case ARM::VABDuv8i8:
    case ARM::VACGEfd:
    case ARM::VACGEfq:
    case ARM::VACGEhd:
    case ARM::VACGEhq:
    case ARM::VACGTfd:
    case ARM::VACGTfq:
    case ARM::VACGThd:
    case ARM::VACGThq:
    case ARM::VADDHNv2i32:
    case ARM::VADDHNv4i16:
    case ARM::VADDHNv8i8:
    case ARM::VADDLsv2i64:
    case ARM::VADDLsv4i32:
    case ARM::VADDLsv8i16:
    case ARM::VADDLuv2i64:
    case ARM::VADDLuv4i32:
    case ARM::VADDLuv8i16:
    case ARM::VADDWsv2i64:
    case ARM::VADDWsv4i32:
    case ARM::VADDWsv8i16:
    case ARM::VADDWuv2i64:
    case ARM::VADDWuv4i32:
    case ARM::VADDWuv8i16:
    case ARM::VADDfd:
    case ARM::VADDfq:
    case ARM::VADDhd:
    case ARM::VADDhq:
    case ARM::VADDv16i8:
    case ARM::VADDv1i64:
    case ARM::VADDv2i32:
    case ARM::VADDv2i64:
    case ARM::VADDv4i16:
    case ARM::VADDv4i32:
    case ARM::VADDv8i16:
    case ARM::VADDv8i8:
    case ARM::VANDd:
    case ARM::VANDq:
    case ARM::VBICd:
    case ARM::VBICq:
    case ARM::VCEQfd:
    case ARM::VCEQfq:
    case ARM::VCEQhd:
    case ARM::VCEQhq:
    case ARM::VCEQv16i8:
    case ARM::VCEQv2i32:
    case ARM::VCEQv4i16:
    case ARM::VCEQv4i32:
    case ARM::VCEQv8i16:
    case ARM::VCEQv8i8:
    case ARM::VCGEfd:
    case ARM::VCGEfq:
    case ARM::VCGEhd:
    case ARM::VCGEhq:
    case ARM::VCGEsv16i8:
    case ARM::VCGEsv2i32:
    case ARM::VCGEsv4i16:
    case ARM::VCGEsv4i32:
    case ARM::VCGEsv8i16:
    case ARM::VCGEsv8i8:
    case ARM::VCGEuv16i8:
    case ARM::VCGEuv2i32:
    case ARM::VCGEuv4i16:
    case ARM::VCGEuv4i32:
    case ARM::VCGEuv8i16:
    case ARM::VCGEuv8i8:
    case ARM::VCGTfd:
    case ARM::VCGTfq:
    case ARM::VCGThd:
    case ARM::VCGThq:
    case ARM::VCGTsv16i8:
    case ARM::VCGTsv2i32:
    case ARM::VCGTsv4i16:
    case ARM::VCGTsv4i32:
    case ARM::VCGTsv8i16:
    case ARM::VCGTsv8i8:
    case ARM::VCGTuv16i8:
    case ARM::VCGTuv2i32:
    case ARM::VCGTuv4i16:
    case ARM::VCGTuv4i32:
    case ARM::VCGTuv8i16:
    case ARM::VCGTuv8i8:
    case ARM::VEORd:
    case ARM::VEORq:
    case ARM::VHADDsv16i8:
    case ARM::VHADDsv2i32:
    case ARM::VHADDsv4i16:
    case ARM::VHADDsv4i32:
    case ARM::VHADDsv8i16:
    case ARM::VHADDsv8i8:
    case ARM::VHADDuv16i8:
    case ARM::VHADDuv2i32:
    case ARM::VHADDuv4i16:
    case ARM::VHADDuv4i32:
    case ARM::VHADDuv8i16:
    case ARM::VHADDuv8i8:
    case ARM::VHSUBsv16i8:
    case ARM::VHSUBsv2i32:
    case ARM::VHSUBsv4i16:
    case ARM::VHSUBsv4i32:
    case ARM::VHSUBsv8i16:
    case ARM::VHSUBsv8i8:
    case ARM::VHSUBuv16i8:
    case ARM::VHSUBuv2i32:
    case ARM::VHSUBuv4i16:
    case ARM::VHSUBuv4i32:
    case ARM::VHSUBuv8i16:
    case ARM::VHSUBuv8i8:
    case ARM::VMAXfd:
    case ARM::VMAXfq:
    case ARM::VMAXhd:
    case ARM::VMAXhq:
    case ARM::VMAXsv16i8:
    case ARM::VMAXsv2i32:
    case ARM::VMAXsv4i16:
    case ARM::VMAXsv4i32:
    case ARM::VMAXsv8i16:
    case ARM::VMAXsv8i8:
    case ARM::VMAXuv16i8:
    case ARM::VMAXuv2i32:
    case ARM::VMAXuv4i16:
    case ARM::VMAXuv4i32:
    case ARM::VMAXuv8i16:
    case ARM::VMAXuv8i8:
    case ARM::VMINfd:
    case ARM::VMINfq:
    case ARM::VMINhd:
    case ARM::VMINhq:
    case ARM::VMINsv16i8:
    case ARM::VMINsv2i32:
    case ARM::VMINsv4i16:
    case ARM::VMINsv4i32:
    case ARM::VMINsv8i16:
    case ARM::VMINsv8i8:
    case ARM::VMINuv16i8:
    case ARM::VMINuv2i32:
    case ARM::VMINuv4i16:
    case ARM::VMINuv4i32:
    case ARM::VMINuv8i16:
    case ARM::VMINuv8i8:
    case ARM::VMULLp64:
    case ARM::VMULLp8:
    case ARM::VMULLsv2i64:
    case ARM::VMULLsv4i32:
    case ARM::VMULLsv8i16:
    case ARM::VMULLuv2i64:
    case ARM::VMULLuv4i32:
    case ARM::VMULLuv8i16:
    case ARM::VMULfd:
    case ARM::VMULfq:
    case ARM::VMULhd:
    case ARM::VMULhq:
    case ARM::VMULpd:
    case ARM::VMULpq:
    case ARM::VMULv16i8:
    case ARM::VMULv2i32:
    case ARM::VMULv4i16:
    case ARM::VMULv4i32:
    case ARM::VMULv8i16:
    case ARM::VMULv8i8:
    case ARM::VORNd:
    case ARM::VORNq:
    case ARM::VORRd:
    case ARM::VORRq:
    case ARM::VPADDf:
    case ARM::VPADDh:
    case ARM::VPADDi16:
    case ARM::VPADDi32:
    case ARM::VPADDi8:
    case ARM::VPMAXf:
    case ARM::VPMAXh:
    case ARM::VPMAXs16:
    case ARM::VPMAXs32:
    case ARM::VPMAXs8:
    case ARM::VPMAXu16:
    case ARM::VPMAXu32:
    case ARM::VPMAXu8:
    case ARM::VPMINf:
    case ARM::VPMINh:
    case ARM::VPMINs16:
    case ARM::VPMINs32:
    case ARM::VPMINs8:
    case ARM::VPMINu16:
    case ARM::VPMINu32:
    case ARM::VPMINu8:
    case ARM::VQADDsv16i8:
    case ARM::VQADDsv1i64:
    case ARM::VQADDsv2i32:
    case ARM::VQADDsv2i64:
    case ARM::VQADDsv4i16:
    case ARM::VQADDsv4i32:
    case ARM::VQADDsv8i16:
    case ARM::VQADDsv8i8:
    case ARM::VQADDuv16i8:
    case ARM::VQADDuv1i64:
    case ARM::VQADDuv2i32:
    case ARM::VQADDuv2i64:
    case ARM::VQADDuv4i16:
    case ARM::VQADDuv4i32:
    case ARM::VQADDuv8i16:
    case ARM::VQADDuv8i8:
    case ARM::VQDMULHv2i32:
    case ARM::VQDMULHv4i16:
    case ARM::VQDMULHv4i32:
    case ARM::VQDMULHv8i16:
    case ARM::VQDMULLv2i64:
    case ARM::VQDMULLv4i32:
    case ARM::VQRDMULHv2i32:
    case ARM::VQRDMULHv4i16:
    case ARM::VQRDMULHv4i32:
    case ARM::VQRDMULHv8i16:
    case ARM::VQSUBsv16i8:
    case ARM::VQSUBsv1i64:
    case ARM::VQSUBsv2i32:
    case ARM::VQSUBsv2i64:
    case ARM::VQSUBsv4i16:
    case ARM::VQSUBsv4i32:
    case ARM::VQSUBsv8i16:
    case ARM::VQSUBsv8i8:
    case ARM::VQSUBuv16i8:
    case ARM::VQSUBuv1i64:
    case ARM::VQSUBuv2i32:
    case ARM::VQSUBuv2i64:
    case ARM::VQSUBuv4i16:
    case ARM::VQSUBuv4i32:
    case ARM::VQSUBuv8i16:
    case ARM::VQSUBuv8i8:
    case ARM::VRADDHNv2i32:
    case ARM::VRADDHNv4i16:
    case ARM::VRADDHNv8i8:
    case ARM::VRECPSfd:
    case ARM::VRECPSfq:
    case ARM::VRECPShd:
    case ARM::VRECPShq:
    case ARM::VRHADDsv16i8:
    case ARM::VRHADDsv2i32:
    case ARM::VRHADDsv4i16:
    case ARM::VRHADDsv4i32:
    case ARM::VRHADDsv8i16:
    case ARM::VRHADDsv8i8:
    case ARM::VRHADDuv16i8:
    case ARM::VRHADDuv2i32:
    case ARM::VRHADDuv4i16:
    case ARM::VRHADDuv4i32:
    case ARM::VRHADDuv8i16:
    case ARM::VRHADDuv8i8:
    case ARM::VRSQRTSfd:
    case ARM::VRSQRTSfq:
    case ARM::VRSQRTShd:
    case ARM::VRSQRTShq:
    case ARM::VRSUBHNv2i32:
    case ARM::VRSUBHNv4i16:
    case ARM::VRSUBHNv8i8:
    case ARM::VSUBHNv2i32:
    case ARM::VSUBHNv4i16:
    case ARM::VSUBHNv8i8:
    case ARM::VSUBLsv2i64:
    case ARM::VSUBLsv4i32:
    case ARM::VSUBLsv8i16:
    case ARM::VSUBLuv2i64:
    case ARM::VSUBLuv4i32:
    case ARM::VSUBLuv8i16:
    case ARM::VSUBWsv2i64:
    case ARM::VSUBWsv4i32:
    case ARM::VSUBWsv8i16:
    case ARM::VSUBWuv2i64:
    case ARM::VSUBWuv4i32:
    case ARM::VSUBWuv8i16:
    case ARM::VSUBfd:
    case ARM::VSUBfq:
    case ARM::VSUBhd:
    case ARM::VSUBhq:
    case ARM::VSUBv16i8:
    case ARM::VSUBv1i64:
    case ARM::VSUBv2i32:
    case ARM::VSUBv2i64:
    case ARM::VSUBv4i16:
    case ARM::VSUBv4i32:
    case ARM::VSUBv8i16:
    case ARM::VSUBv8i8:
    case ARM::VTBL1:
    case ARM::VTBL2:
    case ARM::VTBL3:
    case ARM::VTBL4:
    case ARM::VTSTv16i8:
    case ARM::VTSTv2i32:
    case ARM::VTSTv4i16:
    case ARM::VTSTv4i32:
    case ARM::VTSTv8i16:
    case ARM::VTSTv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMAXNMNDf:
    case ARM::VMAXNMNDh:
    case ARM::VMAXNMNQf:
    case ARM::VMAXNMNQh:
    case ARM::VMINNMNDf:
    case ARM::VMINNMNDh:
    case ARM::VMINNMNQf:
    case ARM::VMINNMNQh: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2V8PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMULLslsv2i32:
    case ARM::VMULLsluv2i32:
    case ARM::VMULslfd:
    case ARM::VMULslfq:
    case ARM::VMULslv2i32:
    case ARM::VMULslv4i32:
    case ARM::VQDMULHslv2i32:
    case ARM::VQDMULHslv4i32:
    case ARM::VQDMULLslv2i32:
    case ARM::VQRDMULHslv2i32:
    case ARM::VQRDMULHslv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMULLslsv4i16:
    case ARM::VMULLsluv4i16:
    case ARM::VMULslhd:
    case ARM::VMULslhq:
    case ARM::VMULslv4i16:
    case ARM::VMULslv8i16:
    case ARM::VQDMULHslv4i16:
    case ARM::VQDMULHslv8i16:
    case ARM::VQDMULLslv4i16:
    case ARM::VQRDMULHslv4i16:
    case ARM::VQRDMULHslv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(2)) << 4;
      Value |= (op & UINT64_C(1)) << 3;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VQRSHLsv16i8:
    case ARM::VQRSHLsv1i64:
    case ARM::VQRSHLsv2i32:
    case ARM::VQRSHLsv2i64:
    case ARM::VQRSHLsv4i16:
    case ARM::VQRSHLsv4i32:
    case ARM::VQRSHLsv8i16:
    case ARM::VQRSHLsv8i8:
    case ARM::VQRSHLuv16i8:
    case ARM::VQRSHLuv1i64:
    case ARM::VQRSHLuv2i32:
    case ARM::VQRSHLuv2i64:
    case ARM::VQRSHLuv4i16:
    case ARM::VQRSHLuv4i32:
    case ARM::VQRSHLuv8i16:
    case ARM::VQRSHLuv8i8:
    case ARM::VQSHLsv16i8:
    case ARM::VQSHLsv1i64:
    case ARM::VQSHLsv2i32:
    case ARM::VQSHLsv2i64:
    case ARM::VQSHLsv4i16:
    case ARM::VQSHLsv4i32:
    case ARM::VQSHLsv8i16:
    case ARM::VQSHLsv8i8:
    case ARM::VQSHLuv16i8:
    case ARM::VQSHLuv1i64:
    case ARM::VQSHLuv2i32:
    case ARM::VQSHLuv2i64:
    case ARM::VQSHLuv4i16:
    case ARM::VQSHLuv4i32:
    case ARM::VQSHLuv8i16:
    case ARM::VQSHLuv8i8:
    case ARM::VRSHLsv16i8:
    case ARM::VRSHLsv1i64:
    case ARM::VRSHLsv2i32:
    case ARM::VRSHLsv2i64:
    case ARM::VRSHLsv4i16:
    case ARM::VRSHLsv4i32:
    case ARM::VRSHLsv8i16:
    case ARM::VRSHLsv8i8:
    case ARM::VRSHLuv16i8:
    case ARM::VRSHLuv1i64:
    case ARM::VRSHLuv2i32:
    case ARM::VRSHLuv2i64:
    case ARM::VRSHLuv4i16:
    case ARM::VRSHLuv4i32:
    case ARM::VRSHLuv8i16:
    case ARM::VRSHLuv8i8:
    case ARM::VSHLsv16i8:
    case ARM::VSHLsv1i64:
    case ARM::VSHLsv2i32:
    case ARM::VSHLsv2i64:
    case ARM::VSHLsv4i16:
    case ARM::VSHLsv4i32:
    case ARM::VSHLsv8i16:
    case ARM::VSHLsv8i8:
    case ARM::VSHLuv16i8:
    case ARM::VSHLuv1i64:
    case ARM::VSHLuv2i32:
    case ARM::VSHLuv2i64:
    case ARM::VSHLuv4i16:
    case ARM::VSHLuv4i32:
    case ARM::VSHLuv8i16:
    case ARM::VSHLuv8i8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCMLAv2f32:
    case ARM::VCMLAv4f16:
    case ARM::VCMLAv4f32:
    case ARM::VCMLAv8f16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 23;
      break;
    }
    case ARM::VCMLAv2f32_indexed:
    case ARM::VCMLAv4f32_indexed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 20;
      break;
    }
    case ARM::SHA1C:
    case ARM::SHA1M:
    case ARM::SHA1P:
    case ARM::SHA1SU0:
    case ARM::SHA256H:
    case ARM::SHA256H2:
    case ARM::SHA256SU1:
    case ARM::VABALsv2i64:
    case ARM::VABALsv4i32:
    case ARM::VABALsv8i16:
    case ARM::VABALuv2i64:
    case ARM::VABALuv4i32:
    case ARM::VABALuv8i16:
    case ARM::VABAsv16i8:
    case ARM::VABAsv2i32:
    case ARM::VABAsv4i16:
    case ARM::VABAsv4i32:
    case ARM::VABAsv8i16:
    case ARM::VABAsv8i8:
    case ARM::VABAuv16i8:
    case ARM::VABAuv2i32:
    case ARM::VABAuv4i16:
    case ARM::VABAuv4i32:
    case ARM::VABAuv8i16:
    case ARM::VABAuv8i8:
    case ARM::VBIFd:
    case ARM::VBIFq:
    case ARM::VBITd:
    case ARM::VBITq:
    case ARM::VBSLd:
    case ARM::VBSLq:
    case ARM::VFMAfd:
    case ARM::VFMAfq:
    case ARM::VFMAhd:
    case ARM::VFMAhq:
    case ARM::VFMSfd:
    case ARM::VFMSfq:
    case ARM::VFMShd:
    case ARM::VFMShq:
    case ARM::VMLALsv2i64:
    case ARM::VMLALsv4i32:
    case ARM::VMLALsv8i16:
    case ARM::VMLALuv2i64:
    case ARM::VMLALuv4i32:
    case ARM::VMLALuv8i16:
    case ARM::VMLAfd:
    case ARM::VMLAfq:
    case ARM::VMLAhd:
    case ARM::VMLAhq:
    case ARM::VMLAv16i8:
    case ARM::VMLAv2i32:
    case ARM::VMLAv4i16:
    case ARM::VMLAv4i32:
    case ARM::VMLAv8i16:
    case ARM::VMLAv8i8:
    case ARM::VMLSLsv2i64:
    case ARM::VMLSLsv4i32:
    case ARM::VMLSLsv8i16:
    case ARM::VMLSLuv2i64:
    case ARM::VMLSLuv4i32:
    case ARM::VMLSLuv8i16:
    case ARM::VMLSfd:
    case ARM::VMLSfq:
    case ARM::VMLShd:
    case ARM::VMLShq:
    case ARM::VMLSv16i8:
    case ARM::VMLSv2i32:
    case ARM::VMLSv4i16:
    case ARM::VMLSv4i32:
    case ARM::VMLSv8i16:
    case ARM::VMLSv8i8:
    case ARM::VQDMLALv2i64:
    case ARM::VQDMLALv4i32:
    case ARM::VQDMLSLv2i64:
    case ARM::VQDMLSLv4i32:
    case ARM::VQRDMLAHv2i32:
    case ARM::VQRDMLAHv4i16:
    case ARM::VQRDMLAHv4i32:
    case ARM::VQRDMLAHv8i16:
    case ARM::VQRDMLSHv2i32:
    case ARM::VQRDMLSHv4i16:
    case ARM::VQRDMLSHv4i32:
    case ARM::VQRDMLSHv8i16:
    case ARM::VTBX1:
    case ARM::VTBX2:
    case ARM::VTBX3:
    case ARM::VTBX4: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMLALslsv2i32:
    case ARM::VMLALsluv2i32:
    case ARM::VMLAslfd:
    case ARM::VMLAslfq:
    case ARM::VMLAslv2i32:
    case ARM::VMLAslv4i32:
    case ARM::VMLSLslsv2i32:
    case ARM::VMLSLsluv2i32:
    case ARM::VMLSslfd:
    case ARM::VMLSslfq:
    case ARM::VMLSslv2i32:
    case ARM::VMLSslv4i32:
    case ARM::VQDMLALslv2i32:
    case ARM::VQDMLSLslv2i32:
    case ARM::VQRDMLAHslv2i32:
    case ARM::VQRDMLAHslv4i32:
    case ARM::VQRDMLSHslv2i32:
    case ARM::VQRDMLSHslv4i32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCMLAv4f16_indexed:
    case ARM::VCMLAv8f16_indexed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 20;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      break;
    }
    case ARM::VMLALslsv4i16:
    case ARM::VMLALsluv4i16:
    case ARM::VMLAslhd:
    case ARM::VMLAslhq:
    case ARM::VMLAslv4i16:
    case ARM::VMLAslv8i16:
    case ARM::VMLSLslsv4i16:
    case ARM::VMLSLsluv4i16:
    case ARM::VMLSslhd:
    case ARM::VMLSslhq:
    case ARM::VMLSslv4i16:
    case ARM::VMLSslv8i16:
    case ARM::VQDMLALslv4i16:
    case ARM::VQDMLSLslv4i16:
    case ARM::VQRDMLAHslv4i16:
    case ARM::VQRDMLAHslv8i16:
    case ARM::VQRDMLSHslv4i16:
    case ARM::VQRDMLSHslv8i16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(7);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(2)) << 4;
      Value |= (op & UINT64_C(1)) << 3;
      Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSDOTD:
    case ARM::VSDOTQ:
    case ARM::VUDOTD:
    case ARM::VUDOTQ: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VSDOTDI:
    case ARM::VSDOTQI:
    case ARM::VUDOTDI:
    case ARM::VUDOTQI: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      break;
    }
    case ARM::VST1LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd32:
    case ARM::VST3LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd16:
    case ARM::VST3LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1LNd16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd32:
    case ARM::VST2LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd16:
    case ARM::VST2LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd16:
    case ARM::VST4LNq16: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16:
    case ARM::VST1d16T:
    case ARM::VST1d32:
    case ARM::VST1d32T:
    case ARM::VST1d64:
    case ARM::VST1d64T:
    case ARM::VST1d8:
    case ARM::VST1d8T:
    case ARM::VST3d16:
    case ARM::VST3d32:
    case ARM::VST3d8:
    case ARM::VST3q16:
    case ARM::VST3q32:
    case ARM::VST3q8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd32:
    case ARM::VST4LNq32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16Q:
    case ARM::VST1d32Q:
    case ARM::VST1d64Q:
    case ARM::VST1d8Q:
    case ARM::VST1q16:
    case ARM::VST1q32:
    case ARM::VST1q64:
    case ARM::VST1q8:
    case ARM::VST2b16:
    case ARM::VST2b32:
    case ARM::VST2b8:
    case ARM::VST2d16:
    case ARM::VST2d32:
    case ARM::VST2d8:
    case ARM::VST2q16:
    case ARM::VST2q32:
    case ARM::VST2q8:
    case ARM::VST4d16:
    case ARM::VST4d32:
    case ARM::VST4d8:
    case ARM::VST4q16:
    case ARM::VST4q32:
    case ARM::VST4q8: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1LNd32: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16wb_fixed:
    case ARM::VST1d32wb_fixed:
    case ARM::VST1d64wb_fixed:
    case ARM::VST1d8wb_fixed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16Qwb_fixed:
    case ARM::VST1d16Twb_fixed:
    case ARM::VST1d32Qwb_fixed:
    case ARM::VST1d32Twb_fixed:
    case ARM::VST1d64Qwb_fixed:
    case ARM::VST1d64Twb_fixed:
    case ARM::VST1d8Qwb_fixed:
    case ARM::VST1d8Twb_fixed:
    case ARM::VST1q16wb_fixed:
    case ARM::VST1q32wb_fixed:
    case ARM::VST1q64wb_fixed:
    case ARM::VST1q8wb_fixed:
    case ARM::VST2b16wb_fixed:
    case ARM::VST2b32wb_fixed:
    case ARM::VST2b8wb_fixed:
    case ARM::VST2d16wb_fixed:
    case ARM::VST2d32wb_fixed:
    case ARM::VST2d8wb_fixed:
    case ARM::VST2q16wb_fixed:
    case ARM::VST2q32wb_fixed:
    case ARM::VST2q8wb_fixed: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd32_UPD:
    case ARM::VST3LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd16_UPD:
    case ARM::VST3LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1LNd16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd32_UPD:
    case ARM::VST2LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd16_UPD:
    case ARM::VST2LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST2LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd16_UPD:
    case ARM::VST4LNq16_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 6;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST3d16_UPD:
    case ARM::VST3d32_UPD:
    case ARM::VST3d8_UPD:
    case ARM::VST3q16_UPD:
    case ARM::VST3q32_UPD:
    case ARM::VST3q8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16wb_register:
    case ARM::VST1d32wb_register:
    case ARM::VST1d64wb_register:
    case ARM::VST1d8wb_register: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4LNd32_UPD:
    case ARM::VST4LNq32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST4d16_UPD:
    case ARM::VST4d32_UPD:
    case ARM::VST4d8_UPD:
    case ARM::VST4q16_UPD:
    case ARM::VST4q32_UPD:
    case ARM::VST4q8_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1d16Qwb_register:
    case ARM::VST1d16Twb_register:
    case ARM::VST1d32Qwb_register:
    case ARM::VST1d32Twb_register:
    case ARM::VST1d64Qwb_register:
    case ARM::VST1d64Twb_register:
    case ARM::VST1d8Qwb_register:
    case ARM::VST1d8Twb_register:
    case ARM::VST1q16wb_register:
    case ARM::VST1q32wb_register:
    case ARM::VST1q64wb_register:
    case ARM::VST1q8wb_register:
    case ARM::VST2b16wb_register:
    case ARM::VST2b32wb_register:
    case ARM::VST2b8wb_register:
    case ARM::VST2d16wb_register:
    case ARM::VST2d32wb_register:
    case ARM::VST2d8wb_register:
    case ARM::VST2q16wb_register:
    case ARM::VST2q32wb_register:
    case ARM::VST2q8wb_register: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(15);
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VST1LNd32_UPD: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(48);
      // op: Rm
      op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lane
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 7;
      Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
      break;
    }
    case ARM::LDC2L_OFFSET:
    case ARM::LDC2L_PRE:
    case ARM::LDC2_OFFSET:
    case ARM::LDC2_PRE:
    case ARM::STC2L_OFFSET:
    case ARM::STC2L_PRE:
    case ARM::STC2_OFFSET:
    case ARM::STC2_PRE:
    case ARM::t2LDC2L_OFFSET:
    case ARM::t2LDC2L_PRE:
    case ARM::t2LDC2_OFFSET:
    case ARM::t2LDC2_PRE:
    case ARM::t2LDCL_OFFSET:
    case ARM::t2LDCL_PRE:
    case ARM::t2LDC_OFFSET:
    case ARM::t2LDC_PRE:
    case ARM::t2STC2L_OFFSET:
    case ARM::t2STC2L_PRE:
    case ARM::t2STC2_OFFSET:
    case ARM::t2STC2_PRE:
    case ARM::t2STCL_OFFSET:
    case ARM::t2STCL_PRE:
    case ARM::t2STC_OFFSET:
    case ARM::t2STC_PRE: {
      // op: addr
      op = getAddrMode5OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::t2PLDWi12:
    case ARM::t2PLDi12:
    case ARM::t2PLIi12: {
      // op: addr
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::PLDWi12:
    case ARM::PLDi12:
    case ARM::PLIi12: {
      // op: addr
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::t2PLDpci:
    case ARM::t2PLIpci: {
      // op: addr
      op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::t2LDAEXB:
    case ARM::t2LDAEXH:
    case ARM::t2LDREXB:
    case ARM::t2LDREXH: {
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::t2LDAEXD:
    case ARM::t2LDREXD: {
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::t2PLDWi8:
    case ARM::t2PLDi8:
    case ARM::t2PLIi8: {
      // op: addr
      op = getT2AddrModeImm8OpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2PLDWs:
    case ARM::t2PLDs:
    case ARM::t2PLIs: {
      // op: addr
      op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(960)) << 10;
      Value |= (op & UINT64_C(3)) << 4;
      Value |= (op & UINT64_C(60)) >> 2;
      break;
    }
    case ARM::t2MSRbanked: {
      // op: banked
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(32)) << 15;
      Value |= (op & UINT64_C(15)) << 8;
      Value |= op & UINT64_C(16);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::t2MRSbanked: {
      // op: banked
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(32)) << 15;
      Value |= (op & UINT64_C(15)) << 16;
      Value |= op & UINT64_C(16);
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::t2IT: {
      // op: cc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tADDrSPi: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 8;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::BX: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tPICADD: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::tSETEND: {
      // op: end
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 3;
      break;
    }
    case ARM::SETEND: {
      // op: end
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 9;
      break;
    }
    case ARM::BL: {
      // op: func
      op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
      Value |= op & UINT64_C(16777215);
      break;
    }
    case ARM::t2BXJ: {
      // op: func
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::BLX: {
      // op: func
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tBLXNSr:
    case ARM::tBLXr: {
      // op: func
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 3;
      break;
    }
    case ARM::tBL: {
      // op: func
      op = getThumbBLTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(8388608)) << 3;
      Value |= (op & UINT64_C(2095104)) << 5;
      Value |= (op & UINT64_C(4194304)) >> 9;
      Value |= (op & UINT64_C(2097152)) >> 10;
      Value |= op & UINT64_C(2047);
      break;
    }
    case ARM::tBLXi: {
      // op: func
      op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(8388608)) << 3;
      Value |= (op & UINT64_C(2095104)) << 5;
      Value |= (op & UINT64_C(4194304)) >> 9;
      Value |= (op & UINT64_C(2097152)) >> 10;
      Value |= op & UINT64_C(2046);
      break;
    }
    case ARM::t2SETPAN: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 3;
      break;
    }
    case ARM::SETPAN: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 9;
      break;
    }
    case ARM::tHINT: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      break;
    }
    case ARM::HVC: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(65520)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2HINT:
    case ARM::t2SUBS_PC_LR:
    case ARM::tSVC: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tADDspi:
    case ARM::tSUBspi: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(127);
      break;
    }
    case ARM::t2HVC:
    case ARM::t2UDF: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::UDF: {
      // op: imm16
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(65520)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tUDF: {
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tCPS: {
      // op: imod
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 4;
      // op: iflags
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::CPS2p: {
      // op: imod
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 18;
      // op: iflags
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 6;
      break;
    }
    case ARM::CPS3p: {
      // op: imod
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 18;
      // op: iflags
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 6;
      // op: mode
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(31);
      break;
    }
    case ARM::t2CPS2p: {
      // op: imod
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 9;
      // op: iflags
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      break;
    }
    case ARM::t2CPS3p: {
      // op: imod
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 9;
      // op: iflags
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: mode
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(31);
      break;
    }
    case ARM::t2MSR_AR: {
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 16;
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::CPS1p:
    case ARM::SRSDA:
    case ARM::SRSDA_UPD:
    case ARM::SRSDB:
    case ARM::SRSDB_UPD:
    case ARM::SRSIA:
    case ARM::SRSIA_UPD:
    case ARM::SRSIB:
    case ARM::SRSIB_UPD:
    case ARM::t2CPS1p:
    case ARM::t2SRSDB:
    case ARM::t2SRSDB_UPD:
    case ARM::t2SRSIA:
    case ARM::t2SRSIA_UPD: {
      // op: mode
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(31);
      break;
    }
    case ARM::LDC2L_POST:
    case ARM::LDC2_POST:
    case ARM::STC2L_POST:
    case ARM::STC2_POST:
    case ARM::t2LDC2L_POST:
    case ARM::t2LDC2_POST:
    case ARM::t2LDCL_POST:
    case ARM::t2LDC_POST:
    case ARM::t2STC2L_POST:
    case ARM::t2STC2_POST:
    case ARM::t2STCL_POST:
    case ARM::t2STC_POST: {
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= op & UINT64_C(255);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::CDP2:
    case ARM::t2CDP:
    case ARM::t2CDP2: {
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2SMC: {
      // op: opt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::DMB:
    case ARM::DSB:
    case ARM::ISB:
    case ARM::t2DBG:
    case ARM::t2DMB:
    case ARM::t2DSB:
    case ARM::t2ISB: {
      // op: opt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDC2L_OPTION:
    case ARM::LDC2_OPTION:
    case ARM::STC2L_OPTION:
    case ARM::STC2_OPTION:
    case ARM::t2LDC2L_OPTION:
    case ARM::t2LDC2_OPTION:
    case ARM::t2LDCL_OPTION:
    case ARM::t2LDC_OPTION:
    case ARM::t2STC2L_OPTION:
    case ARM::t2STC2_OPTION:
    case ARM::t2STCL_OPTION:
    case ARM::t2STC_OPTION: {
      // op: option
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(255);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::BX_RET:
    case ARM::ERET:
    case ARM::MOVPCLR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      break;
    }
    case ARM::FMSTAT: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::t2Bcc: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 22;
      // op: target
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(1048576)) << 6;
      Value |= (op & UINT64_C(258048)) << 4;
      Value |= (op & UINT64_C(262144)) >> 5;
      Value |= (op & UINT64_C(524288)) >> 8;
      Value |= (op & UINT64_C(4094)) >> 1;
      break;
    }
    case ARM::VCMPEZD:
    case ARM::VCMPZD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::MRS:
    case ARM::MRSsys: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::VLDMSIA:
    case ARM::VSTMSIA: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 14;
      Value |= (op & UINT64_C(7680)) << 3;
      Value |= op & UINT64_C(255);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::FLDMXIA:
    case ARM::FSTMXIA: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(3840)) << 4;
      Value |= op & UINT64_C(254);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLDMDIA:
    case ARM::VSTMDIA: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 10;
      Value |= (op & UINT64_C(3840)) << 4;
      Value |= op & UINT64_C(254);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLLDM:
    case ARM::VLSTM: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMRS:
    case ARM::VMRS_FPEXC:
    case ARM::VMRS_FPINST:
    case ARM::VMRS_FPINST2:
    case ARM::VMRS_FPSID:
    case ARM::VMRS_MVFR0:
    case ARM::VMRS_MVFR1:
    case ARM::VMRS_MVFR2: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCMPEZH:
    case ARM::VCMPEZS:
    case ARM::VCMPZH:
    case ARM::VCMPZS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::BX_pred: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::BL_pred: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: func
      op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
      Value |= op & UINT64_C(16777215);
      break;
    }
    case ARM::BLX_pred:
    case ARM::BXJ: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: func
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::HINT: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::DBG:
    case ARM::SMC: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: opt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDMDA:
    case ARM::LDMDB:
    case ARM::LDMIA:
    case ARM::LDMIB:
    case ARM::STMDA:
    case ARM::STMDB:
    case ARM::STMIA:
    case ARM::STMIB:
    case ARM::sysLDMDA:
    case ARM::sysLDMDB:
    case ARM::sysLDMIA:
    case ARM::sysLDMIB:
    case ARM::sysSTMDA:
    case ARM::sysSTMDB:
    case ARM::sysSTMIA:
    case ARM::sysSTMIB: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: regs
      op = getRegisterListOpValue(MI, 3, Fixups, STI);
      Value |= op & UINT64_C(65535);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::VMSR:
    case ARM::VMSR_FPEXC:
    case ARM::VMSR_FPINST:
    case ARM::VMSR_FPINST2:
    case ARM::VMSR_FPSID: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::SVC: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: svc
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(16777215);
      break;
    }
    case ARM::Bcc: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: target
      op = getARMBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= op & UINT64_C(16777215);
      break;
    }
    case ARM::tBcc: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: target
      op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::VABSD:
    case ARM::VCMPD:
    case ARM::VCMPED:
    case ARM::VMOVD:
    case ARM::VNEGD:
    case ARM::VRINTRD:
    case ARM::VRINTXD:
    case ARM::VRINTZD:
    case ARM::VSQRTD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCVTBHD:
    case ARM::VCVTTHD:
    case ARM::VSITOD:
    case ARM::VUITOD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::FCONSTD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(240)) << 12;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCVTBDH:
    case ARM::VCVTTDH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::CLZ:
    case ARM::RBIT:
    case ARM::REV:
    case ARM::REV16:
    case ARM::REVSH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MOVi16: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: imm
      op = getHiLo16ImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::ADR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: label
      op = getAdrLabelOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(12288)) << 10;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::CMNzrr:
    case ARM::CMPrr:
    case ARM::TEQrr:
    case ARM::TSTrr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::CMNri:
    case ARM::CMPri:
    case ARM::TEQri:
    case ARM::TSTri: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getModImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::VLDMSDB_UPD:
    case ARM::VLDMSIA_UPD:
    case ARM::VSTMSDB_UPD:
    case ARM::VSTMSIA_UPD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 14;
      Value |= (op & UINT64_C(7680)) << 3;
      Value |= op & UINT64_C(255);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::FLDMXDB_UPD:
    case ARM::FLDMXIA_UPD:
    case ARM::FSTMXDB_UPD:
    case ARM::FSTMXIA_UPD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(3840)) << 4;
      Value |= op & UINT64_C(254);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLDMDDB_UPD:
    case ARM::VLDMDIA_UPD:
    case ARM::VSTMDDB_UPD:
    case ARM::VSTMDIA_UPD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 10;
      Value |= (op & UINT64_C(3840)) << 4;
      Value |= op & UINT64_C(254);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVRH:
    case ARM::VMOVRS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Sn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(30)) << 15;
      Value |= (op & UINT64_C(1)) << 7;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::LDA:
    case ARM::LDAB:
    case ARM::LDAEX:
    case ARM::LDAEXB:
    case ARM::LDAEXD:
    case ARM::LDAEXH:
    case ARM::LDAH:
    case ARM::LDREX:
    case ARM::LDREXB:
    case ARM::LDREXD:
    case ARM::LDREXH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::STL:
    case ARM::STLB:
    case ARM::STLH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::VCVTSD:
    case ARM::VJCVT:
    case ARM::VTOSIRD:
    case ARM::VTOSIZD:
    case ARM::VTOUIRD:
    case ARM::VTOUIZD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VABSH:
    case ARM::VABSS:
    case ARM::VCMPEH:
    case ARM::VCMPES:
    case ARM::VCMPH:
    case ARM::VCMPS:
    case ARM::VCVTBHS:
    case ARM::VCVTBSH:
    case ARM::VCVTTHS:
    case ARM::VCVTTSH:
    case ARM::VMOVS:
    case ARM::VNEGH:
    case ARM::VNEGS:
    case ARM::VRINTRH:
    case ARM::VRINTRS:
    case ARM::VRINTXH:
    case ARM::VRINTXS:
    case ARM::VRINTZH:
    case ARM::VRINTZS:
    case ARM::VSITOH:
    case ARM::VSITOS:
    case ARM::VSQRTH:
    case ARM::VSQRTS:
    case ARM::VTOSIRH:
    case ARM::VTOSIRS:
    case ARM::VTOSIZH:
    case ARM::VTOSIZS:
    case ARM::VTOUIRH:
    case ARM::VTOUIRS:
    case ARM::VTOUIZH:
    case ARM::VTOUIZS:
    case ARM::VUITOH:
    case ARM::VUITOS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::FCONSTH:
    case ARM::FCONSTS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(240)) << 12;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VCVTDS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVHR:
    case ARM::VMOVSR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(30)) << 15;
      Value |= (op & UINT64_C(1)) << 7;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::MSRbanked: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: banked
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(32)) << 17;
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 4;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MRSbanked: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: banked
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(32)) << 17;
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 4;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::MSR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MSRi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getModImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::LDMDA_UPD:
    case ARM::LDMDB_UPD:
    case ARM::LDMIA_UPD:
    case ARM::LDMIB_UPD:
    case ARM::STMDA_UPD:
    case ARM::STMDB_UPD:
    case ARM::STMIA_UPD:
    case ARM::STMIB_UPD:
    case ARM::sysLDMDA_UPD:
    case ARM::sysLDMDB_UPD:
    case ARM::sysLDMIA_UPD:
    case ARM::sysLDMIB_UPD:
    case ARM::sysSTMDA_UPD:
    case ARM::sysSTMDB_UPD:
    case ARM::sysSTMIA_UPD:
    case ARM::sysSTMIB_UPD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: regs
      op = getRegisterListOpValue(MI, 4, Fixups, STI);
      Value |= op & UINT64_C(65535);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::MOVr:
    case ARM::MOVr_TC:
    case ARM::MVNr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MOVi:
    case ARM::MVNi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: imm
      op = getModImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::VADDD:
    case ARM::VDIVD:
    case ARM::VMULD:
    case ARM::VNMULD:
    case ARM::VSUBD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Dn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLDRD:
    case ARM::VSTRD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrMode5OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVDRR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VMOVRRD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::SXTB:
    case ARM::SXTB16:
    case ARM::SXTH:
    case ARM::UXTB:
    case ARM::UXTB16:
    case ARM::UXTH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 10;
      break;
    }
    case ARM::SEL: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::BFC: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: imm
      op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(992)) << 11;
      Value |= (op & UINT64_C(31)) << 7;
      break;
    }
    case ARM::MOVTi16: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: imm
      op = getHiLo16ImmOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(61440)) << 4;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::SSAT16:
    case ARM::USAT16: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: sat_imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SDIV:
    case ARM::SMMUL:
    case ARM::SMMULR:
    case ARM::UDIV:
    case ARM::USAD8: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      break;
    }
    case ARM::CMNzrsi:
    case ARM::CMPrsi:
    case ARM::TEQrsi:
    case ARM::TSTrsi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: shift
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::QADD16:
    case ARM::QADD8:
    case ARM::QASX:
    case ARM::QSAX:
    case ARM::QSUB16:
    case ARM::QSUB8:
    case ARM::SADD16:
    case ARM::SADD8:
    case ARM::SASX:
    case ARM::SHADD16:
    case ARM::SHADD8:
    case ARM::SHASX:
    case ARM::SHSAX:
    case ARM::SHSUB16:
    case ARM::SHSUB8:
    case ARM::SSAX:
    case ARM::SSUB16:
    case ARM::SSUB8:
    case ARM::UADD16:
    case ARM::UADD8:
    case ARM::UASX:
    case ARM::UHADD16:
    case ARM::UHADD8:
    case ARM::UHASX:
    case ARM::UHSAX:
    case ARM::UHSUB16:
    case ARM::UHSUB8:
    case ARM::UQADD16:
    case ARM::UQADD8:
    case ARM::UQASX:
    case ARM::UQSAX:
    case ARM::UQSUB16:
    case ARM::UQSUB8:
    case ARM::USAX:
    case ARM::USUB16:
    case ARM::USUB8: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SMUAD:
    case ARM::SMUADX:
    case ARM::SMULBB:
    case ARM::SMULBT:
    case ARM::SMULTB:
    case ARM::SMULTT:
    case ARM::SMULWB:
    case ARM::SMULWT:
    case ARM::SMUSD:
    case ARM::SMUSDX: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::QADD:
    case ARM::QDADD:
    case ARM::QDSUB:
    case ARM::QSUB: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SWP:
    case ARM::SWPB: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::LDRBi12:
    case ARM::LDRi12:
    case ARM::STRBi12:
    case ARM::STRi12: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::LDRcp: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::STLEX:
    case ARM::STLEXB:
    case ARM::STLEXD:
    case ARM::STLEXH:
    case ARM::STREX:
    case ARM::STREXB:
    case ARM::STREXD:
    case ARM::STREXH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::VADDH:
    case ARM::VADDS:
    case ARM::VDIVH:
    case ARM::VDIVS:
    case ARM::VMULH:
    case ARM::VMULS:
    case ARM::VNMULH:
    case ARM::VNMULS:
    case ARM::VSUBH:
    case ARM::VSUBS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Sn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(30)) << 15;
      Value |= (op & UINT64_C(1)) << 7;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLDRH:
    case ARM::VSTRH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: addr
      op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VLDRS:
    case ARM::VSTRS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: addr
      op = getAddrMode5OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSHTOH:
    case ARM::VSHTOS:
    case ARM::VSLTOH:
    case ARM::VSLTOS:
    case ARM::VTOSHH:
    case ARM::VTOSHS:
    case ARM::VTOSLH:
    case ARM::VTOSLS:
    case ARM::VTOUHH:
    case ARM::VTOUHS:
    case ARM::VTOULH:
    case ARM::VTOULS:
    case ARM::VUHTOH:
    case ARM::VUHTOS:
    case ARM::VULTOH:
    case ARM::VULTOS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: fbits
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::VSHTOD:
    case ARM::VSLTOD:
    case ARM::VTOSHD:
    case ARM::VTOSLD:
    case ARM::VTOUHD:
    case ARM::VTOULD:
    case ARM::VUHTOD:
    case ARM::VULTOD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: fbits
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::ADCrr:
    case ARM::ADDrr:
    case ARM::ANDrr:
    case ARM::BICrr:
    case ARM::EORrr:
    case ARM::ORRrr:
    case ARM::RSBrr:
    case ARM::RSCrr:
    case ARM::SBCrr:
    case ARM::SUBrr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::ADCri:
    case ARM::ADDri:
    case ARM::ANDri:
    case ARM::BICri:
    case ARM::EORri:
    case ARM::ORRri:
    case ARM::RSBri:
    case ARM::RSCri:
    case ARM::SBCri:
    case ARM::SUBri: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getModImmOpValue(MI, 2, Fixups, STI);
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::MVNsi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: shift
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MOVsi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: src
      op = getSORegImmOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MUL: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VFMAD:
    case ARM::VFMSD:
    case ARM::VFNMAD:
    case ARM::VFNMSD:
    case ARM::VMLAD:
    case ARM::VMLSD:
    case ARM::VNMLAD:
    case ARM::VNMLSD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Dd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 18;
      Value |= (op & UINT64_C(15)) << 12;
      // op: Dn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value |= (op & UINT64_C(16)) << 3;
      // op: Dm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(16)) << 1;
      Value |= op & UINT64_C(15);
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::SXTAB:
    case ARM::SXTAB16:
    case ARM::SXTAH:
    case ARM::UXTAB:
    case ARM::UXTAB16:
    case ARM::UXTAH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(3)) << 10;
      break;
    }
    case ARM::PKHBT:
    case ARM::PKHTB: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: sh
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 7;
      break;
    }
    case ARM::SBFX:
    case ARM::UBFX: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: lsb
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 7;
      // op: width
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      break;
    }
    case ARM::BFI: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: imm
      op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(992)) << 11;
      Value |= (op & UINT64_C(31)) << 7;
      break;
    }
    case ARM::SSAT:
    case ARM::USAT: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: sat_imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: sh
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(31)) << 7;
      Value |= (op & UINT64_C(32)) << 1;
      break;
    }
    case ARM::MLS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::SMMLA:
    case ARM::SMMLAR:
    case ARM::SMMLS:
    case ARM::SMMLSR:
    case ARM::USADA8: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::CMNzrsr:
    case ARM::CMPrsr:
    case ARM::TEQrsr:
    case ARM::TSTrsr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: shift
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(3840);
      Value |= op & UINT64_C(96);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SMLAD:
    case ARM::SMLADX:
    case ARM::SMLSD:
    case ARM::SMLSDX: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::SMLABB:
    case ARM::SMLABT:
    case ARM::SMLATB:
    case ARM::SMLATT:
    case ARM::SMLAWB:
    case ARM::SMLAWT: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::LDRB_PRE_IMM:
    case ARM::LDR_PRE_IMM: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::LDRBrs:
    case ARM::LDRrs:
    case ARM::STRBrs:
    case ARM::STRrs: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: shift
      op = getLdStSORegOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRB_PRE_IMM:
    case ARM::STR_PRE_IMM: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4095);
      break;
    }
    case ARM::VFMAH:
    case ARM::VFMAS:
    case ARM::VFMSH:
    case ARM::VFMSS:
    case ARM::VFNMAH:
    case ARM::VFNMAS:
    case ARM::VFNMSH:
    case ARM::VFNMSS:
    case ARM::VMLAH:
    case ARM::VMLAS:
    case ARM::VMLSH:
    case ARM::VMLSS:
    case ARM::VNMLAH:
    case ARM::VNMLAS:
    case ARM::VNMLSH:
    case ARM::VNMLSS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Sd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 22;
      Value |= (op & UINT64_C(30)) << 11;
      // op: Sn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(30)) << 15;
      Value |= (op & UINT64_C(1)) << 7;
      // op: Sm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::LDRH:
    case ARM::LDRSB:
    case ARM::LDRSH:
    case ARM::STRH: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getAddrMode3OpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::LDCL_OFFSET:
    case ARM::LDCL_PRE:
    case ARM::LDC_OFFSET:
    case ARM::LDC_PRE:
    case ARM::STCL_OFFSET:
    case ARM::STCL_PRE:
    case ARM::STC_OFFSET:
    case ARM::STC_PRE: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getAddrMode5OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= op & UINT64_C(255);
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::LDRHTi:
    case ARM::LDRSBTi:
    case ARM::LDRSHTi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRHTi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VMOVSRR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: dst1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      // op: src1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: src2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::LDCL_POST:
    case ARM::LDC_POST:
    case ARM::STCL_POST:
    case ARM::STC_POST: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= op & UINT64_C(255);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::LDCL_OPTION:
    case ARM::LDC_OPTION:
    case ARM::STCL_OPTION:
    case ARM::STC_OPTION: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: option
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= op & UINT64_C(255);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::ADCrsi:
    case ARM::ADDrsi:
    case ARM::ANDrsi:
    case ARM::BICrsi:
    case ARM::EORrsi:
    case ARM::ORRrsi:
    case ARM::RSBrsi:
    case ARM::RSCrsi:
    case ARM::SBCrsi:
    case ARM::SUBrsi: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: shift
      op = getSORegImmOpValue(MI, 2, Fixups, STI);
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MVNsr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: shift
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(3840);
      Value |= op & UINT64_C(96);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MOVsr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: src
      op = getSORegRegOpValue(MI, 1, Fixups, STI);
      Value |= op & UINT64_C(3840);
      Value |= op & UINT64_C(96);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MLA: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::SMULL:
    case ARM::UMULL: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: RdLo
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: RdHi
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::VMOVRRS: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: src1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(1)) << 5;
      Value |= (op & UINT64_C(30)) >> 1;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      Value = VFPThumb2PostEncoder(MI, Value, STI);
      break;
    }
    case ARM::MRRC: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDRH_PRE:
    case ARM::LDRSB_PRE:
    case ARM::LDRSH_PRE: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDRB_PRE_REG:
    case ARM::LDR_PRE_REG: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getLdStSORegOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDRBT_POST_REG:
    case ARM::LDRB_POST_REG:
    case ARM::LDRT_POST_REG:
    case ARM::LDR_POST_REG: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::LDRBT_POST_IMM:
    case ARM::LDRB_POST_IMM:
    case ARM::LDRT_POST_IMM:
    case ARM::LDR_POST_IMM: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4095);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::LDRH_POST:
    case ARM::LDRSB_POST:
    case ARM::LDRSH_POST: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(512)) << 13;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::STRH_PRE: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRB_PRE_REG:
    case ARM::STR_PRE_REG: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getLdStSORegOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRBT_POST_REG:
    case ARM::STRB_POST_REG:
    case ARM::STRT_POST_REG:
    case ARM::STR_POST_REG: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::STRBT_POST_IMM:
    case ARM::STRB_POST_IMM:
    case ARM::STRT_POST_IMM:
    case ARM::STR_POST_IMM: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= op & UINT64_C(4095);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::STRH_POST: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(512)) << 13;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::MCRR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 4;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::LDRD:
    case ARM::STRD: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getAddrMode3OpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      break;
    }
    case ARM::LDRHTr:
    case ARM::LDRSBTr:
    case ARM::LDRSHTr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(16)) << 19;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRHTr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rm
      op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(16)) << 19;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::ADCrsr:
    case ARM::ADDrsr:
    case ARM::ANDrsr:
    case ARM::BICrsr:
    case ARM::EORrsr:
    case ARM::ORRrsr:
    case ARM::RSBrsr:
    case ARM::RSCrsr:
    case ARM::SBCrsr:
    case ARM::SUBrsr: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 7, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: shift
      op = getSORegRegOpValue(MI, 2, Fixups, STI);
      Value |= op & UINT64_C(3840);
      Value |= op & UINT64_C(96);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::UMAAL: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: RdLo
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: RdHi
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SMLALBB:
    case ARM::SMLALBT:
    case ARM::SMLALD:
    case ARM::SMLALDX:
    case ARM::SMLALTB:
    case ARM::SMLALTT:
    case ARM::SMLSLD:
    case ARM::SMLSLDX: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: RdLo
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: RdHi
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::LDRD_PRE: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrMode3OpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::MRC: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 21;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::LDRD_POST: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(512)) << 13;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::STRD_PRE: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: addr
      op = getAddrMode3OpValue(MI, 3, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(8192)) << 9;
      Value |= (op & UINT64_C(7680)) << 7;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::STRD_POST: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: offset
      op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(256)) << 15;
      Value |= (op & UINT64_C(512)) << 13;
      Value |= (op & UINT64_C(240)) << 4;
      Value |= op & UINT64_C(15);
      // op: addr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::MCR: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 21;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      break;
    }
    case ARM::CDP: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: opc1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 20;
      // op: CRn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: CRd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: cop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: opc2
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & UINT64_C(7)) << 5;
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::SMLAL:
    case ARM::UMLAL: {
      // op: p
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 28;
      // op: s
      op = getCCOutOpValue(MI, 8, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: RdLo
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 12;
      // op: RdHi
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tPUSH: {
      // op: regs
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(16384)) >> 6;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tPOP: {
      // op: regs
      op = getRegisterListOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(32768)) >> 7;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2MOVr:
    case ARM::t2MVNr:
    case ARM::t2RRX: {
      // op: s
      op = getCCOutOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2MOVi:
    case ARM::t2MVNi: {
      // op: s
      op = getCCOutOpValue(MI, 4, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: imm
      op = getT2SOImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2ASRri:
    case ARM::t2LSLri:
    case ARM::t2LSRri:
    case ARM::t2RORri: {
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= op & UINT64_C(15);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & UINT64_C(28)) << 10;
      Value |= (op & UINT64_C(3)) << 6;
      break;
    }
    case ARM::t2ADCrr:
    case ARM::t2ADDrr:
    case ARM::t2ANDrr:
    case ARM::t2ASRrr:
    case ARM::t2BICrr:
    case ARM::t2EORrr:
    case ARM::t2LSLrr:
    case ARM::t2LSRrr:
    case ARM::t2ORNrr:
    case ARM::t2ORRrr:
    case ARM::t2RORrr:
    case ARM::t2RSBrr:
    case ARM::t2SBCrr:
    case ARM::t2SUBrr: {
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2ADCri:
    case ARM::t2ADDri:
    case ARM::t2ANDri:
    case ARM::t2BICri:
    case ARM::t2EORri:
    case ARM::t2ORNri:
    case ARM::t2ORRri:
    case ARM::t2RSBri:
    case ARM::t2SBCri:
    case ARM::t2SUBri: {
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: imm
      op = getT2SOImmOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(2048)) << 15;
      Value |= (op & UINT64_C(1792)) << 4;
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::t2MVNs: {
      // op: s
      op = getCCOutOpValue(MI, 5, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: ShiftedRm
      op = getT2SORegOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(3584)) << 3;
      Value |= (op & UINT64_C(480)) >> 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::t2ADCrs:
    case ARM::t2ADDrs:
    case ARM::t2ANDrs:
    case ARM::t2BICrs:
    case ARM::t2EORrs:
    case ARM::t2ORNrs:
    case ARM::t2ORRrs:
    case ARM::t2RSBrs:
    case ARM::t2SBCrs:
    case ARM::t2SUBrs: {
      // op: s
      op = getCCOutOpValue(MI, 6, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 20;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 8;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & UINT64_C(15)) << 16;
      // op: ShiftedRm
      op = getT2SORegOpValue(MI, 2, Fixups, STI);
      Value |= (op & UINT64_C(3584)) << 3;
      Value |= (op & UINT64_C(480)) >> 1;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::PLDWrs:
    case ARM::PLDrs:
    case ARM::PLIrs: {
      // op: shift
      op = getLdStSORegOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(4096)) << 11;
      Value |= (op & UINT64_C(122880)) << 3;
      Value |= op & UINT64_C(4064);
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::BLXi: {
      // op: target
      op = getARMBLXTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(1)) << 24;
      Value |= (op & UINT64_C(33554430)) >> 1;
      break;
    }
    case ARM::tB: {
      // op: target
      op = getThumbBRTargetOpValue(MI, 0, Fixups, STI);
      Value |= op & UINT64_C(2047);
      break;
    }
    case ARM::t2B: {
      // op: target
      op = getThumbBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & UINT64_C(8388608)) << 3;
      Value |= (op & UINT64_C(2095104)) << 5;
      Value |= (op & UINT64_C(4194304)) >> 9;
      Value |= (op & UINT64_C(2097152)) >> 10;
      Value |= op & UINT64_C(2047);
      break;
    }
    case ARM::tCBNZ:
    case ARM::tCBZ: {
      // op: target
      op = getThumbCBTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & UINT64_C(32)) << 4;
      Value |= (op & UINT64_C(31)) << 3;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(7);
      break;
    }
    case ARM::BKPT:
    case ARM::HLT: {
      // op: val
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & UINT64_C(65520)) << 4;
      Value |= op & UINT64_C(15);
      break;
    }
    case ARM::tBKPT: {
      // op: val
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(255);
      break;
    }
    case ARM::tHLT: {
      // op: val
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= op & UINT64_C(63);
      break;
    }
  default:
    std::string msg;
    raw_string_ostream Msg(msg);
    Msg << "Not supported instr: " << MI;
    report_fatal_error(Msg.str());
  }
  return Value;
}

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER
#include <sstream>

// Flags for subtarget features that participate in instruction matching.
enum SubtargetFeatureFlag : uint64_t {
  Feature_HasV4T = (1ULL << 20),
  Feature_HasV5T = (1ULL << 21),
  Feature_HasV5TE = (1ULL << 22),
  Feature_HasV6 = (1ULL << 23),
  Feature_HasV6M = (1ULL << 25),
  Feature_HasV8MBaseline = (1ULL << 30),
  Feature_HasV8MMainline = (1ULL << 31),
  Feature_HasV6T2 = (1ULL << 26),
  Feature_HasV6K = (1ULL << 24),
  Feature_HasV7 = (1ULL << 27),
  Feature_HasV8 = (1ULL << 29),
  Feature_PreV8 = (1ULL << 45),
  Feature_HasV8_1a = (1ULL << 32),
  Feature_HasV8_2a = (1ULL << 33),
  Feature_HasV8_3a = (1ULL << 34),
  Feature_HasV8_4a = (1ULL << 35),
  Feature_HasVFP2 = (1ULL << 36),
  Feature_HasVFP3 = (1ULL << 37),
  Feature_HasVFP4 = (1ULL << 38),
  Feature_HasDPVFP = (1ULL << 7),
  Feature_HasFPARMv8 = (1ULL << 13),
  Feature_HasNEON = (1ULL << 16),
  Feature_HasSHA2 = (1ULL << 18),
  Feature_HasAES = (1ULL << 1),
  Feature_HasCrypto = (1ULL << 4),
  Feature_HasDotProd = (1ULL << 11),
  Feature_HasCRC = (1ULL << 3),
  Feature_HasRAS = (1ULL << 17),
  Feature_HasFP16 = (1ULL << 12),
  Feature_HasFullFP16 = (1ULL << 14),
  Feature_HasDivideInThumb = (1ULL << 10),
  Feature_HasDivideInARM = (1ULL << 9),
  Feature_HasDSP = (1ULL << 8),
  Feature_HasDB = (1ULL << 5),
  Feature_HasDFB = (1ULL << 6),
  Feature_HasV7Clrex = (1ULL << 28),
  Feature_HasAcquireRelease = (1ULL << 2),
  Feature_HasMP = (1ULL << 15),
  Feature_HasVirtualization = (1ULL << 39),
  Feature_HasTrustZone = (1ULL << 19),
  Feature_Has8MSecExt = (1ULL << 0),
  Feature_IsThumb = (1ULL << 43),
  Feature_IsThumb2 = (1ULL << 44),
  Feature_IsMClass = (1ULL << 41),
  Feature_IsNotMClass = (1ULL << 42),
  Feature_IsARM = (1ULL << 40),
  Feature_UseNaClTrap = (1ULL << 46),
  Feature_UseNegativeImmediates = (1ULL << 47),
  Feature_None = 0
};

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  "Feature_Has8MSecExt",
  "Feature_HasAES",
  "Feature_HasAcquireRelease",
  "Feature_HasCRC",
  "Feature_HasCrypto",
  "Feature_HasDB",
  "Feature_HasDFB",
  "Feature_HasDPVFP",
  "Feature_HasDSP",
  "Feature_HasDivideInARM",
  "Feature_HasDivideInThumb",
  "Feature_HasDotProd",
  "Feature_HasFP16",
  "Feature_HasFPARMv8",
  "Feature_HasFullFP16",
  "Feature_HasMP",
  "Feature_HasNEON",
  "Feature_HasRAS",
  "Feature_HasSHA2",
  "Feature_HasTrustZone",
  "Feature_HasV4T",
  "Feature_HasV5T",
  "Feature_HasV5TE",
  "Feature_HasV6",
  "Feature_HasV6K",
  "Feature_HasV6M",
  "Feature_HasV6T2",
  "Feature_HasV7",
  "Feature_HasV7Clrex",
  "Feature_HasV8",
  "Feature_HasV8MBaseline",
  "Feature_HasV8MMainline",
  "Feature_HasV8_1a",
  "Feature_HasV8_2a",
  "Feature_HasV8_3a",
  "Feature_HasV8_4a",
  "Feature_HasVFP2",
  "Feature_HasVFP3",
  "Feature_HasVFP4",
  "Feature_HasVirtualization",
  "Feature_IsARM",
  "Feature_IsMClass",
  "Feature_IsNotMClass",
  "Feature_IsThumb",
  "Feature_IsThumb2",
  "Feature_PreV8",
  "Feature_UseNaClTrap",
  "Feature_UseNegativeImmediates",
  nullptr
};

#endif // NDEBUG
uint64_t ARMMCCodeEmitter::
computeAvailableFeatures(const FeatureBitset& FB) const {
  uint64_t Features = 0;
  if ((FB[ARM::HasV4TOps]))
    Features |= Feature_HasV4T;
  if ((FB[ARM::HasV5TOps]))
    Features |= Feature_HasV5T;
  if ((FB[ARM::HasV5TEOps]))
    Features |= Feature_HasV5TE;
  if ((FB[ARM::HasV6Ops]))
    Features |= Feature_HasV6;
  if ((FB[ARM::HasV6MOps]))
    Features |= Feature_HasV6M;
  if ((FB[ARM::HasV8MBaselineOps]))
    Features |= Feature_HasV8MBaseline;
  if ((FB[ARM::HasV8MMainlineOps]))
    Features |= Feature_HasV8MMainline;
  if ((FB[ARM::HasV6T2Ops]))
    Features |= Feature_HasV6T2;
  if ((FB[ARM::HasV6KOps]))
    Features |= Feature_HasV6K;
  if ((FB[ARM::HasV7Ops]))
    Features |= Feature_HasV7;
  if ((FB[ARM::HasV8Ops]))
    Features |= Feature_HasV8;
  if ((!FB[ARM::HasV8Ops]))
    Features |= Feature_PreV8;
  if ((FB[ARM::HasV8_1aOps]))
    Features |= Feature_HasV8_1a;
  if ((FB[ARM::HasV8_2aOps]))
    Features |= Feature_HasV8_2a;
  if ((FB[ARM::HasV8_3aOps]))
    Features |= Feature_HasV8_3a;
  if ((FB[ARM::HasV8_4aOps]))
    Features |= Feature_HasV8_4a;
  if ((FB[ARM::FeatureVFP2]))
    Features |= Feature_HasVFP2;
  if ((FB[ARM::FeatureVFP3]))
    Features |= Feature_HasVFP3;
  if ((FB[ARM::FeatureVFP4]))
    Features |= Feature_HasVFP4;
  if ((!FB[ARM::FeatureVFPOnlySP]))
    Features |= Feature_HasDPVFP;
  if ((FB[ARM::FeatureFPARMv8]))
    Features |= Feature_HasFPARMv8;
  if ((FB[ARM::FeatureNEON]))
    Features |= Feature_HasNEON;
  if ((FB[ARM::FeatureSHA2]))
    Features |= Feature_HasSHA2;
  if ((FB[ARM::FeatureAES]))
    Features |= Feature_HasAES;
  if ((FB[ARM::FeatureCrypto]))
    Features |= Feature_HasCrypto;
  if ((FB[ARM::FeatureDotProd]))
    Features |= Feature_HasDotProd;
  if ((FB[ARM::FeatureCRC]))
    Features |= Feature_HasCRC;
  if ((FB[ARM::FeatureRAS]))
    Features |= Feature_HasRAS;
  if ((FB[ARM::FeatureFP16]))
    Features |= Feature_HasFP16;
  if ((FB[ARM::FeatureFullFP16]))
    Features |= Feature_HasFullFP16;
  if ((FB[ARM::FeatureHWDivThumb]))
    Features |= Feature_HasDivideInThumb;
  if ((FB[ARM::FeatureHWDivARM]))
    Features |= Feature_HasDivideInARM;
  if ((FB[ARM::FeatureDSP]))
    Features |= Feature_HasDSP;
  if ((FB[ARM::FeatureDB]))
    Features |= Feature_HasDB;
  if ((FB[ARM::FeatureDFB]))
    Features |= Feature_HasDFB;
  if ((FB[ARM::FeatureV7Clrex]))
    Features |= Feature_HasV7Clrex;
  if ((FB[ARM::FeatureAcquireRelease]))
    Features |= Feature_HasAcquireRelease;
  if ((FB[ARM::FeatureMP]))
    Features |= Feature_HasMP;
  if ((FB[ARM::FeatureVirtualization]))
    Features |= Feature_HasVirtualization;
  if ((FB[ARM::FeatureTrustZone]))
    Features |= Feature_HasTrustZone;
  if ((FB[ARM::Feature8MSecExt]))
    Features |= Feature_Has8MSecExt;
  if ((FB[ARM::ModeThumb]))
    Features |= Feature_IsThumb;
  if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2]))
    Features |= Feature_IsThumb2;
  if ((FB[ARM::FeatureMClass]))
    Features |= Feature_IsMClass;
  if ((!FB[ARM::FeatureMClass]))
    Features |= Feature_IsNotMClass;
  if ((!FB[ARM::ModeThumb]))
    Features |= Feature_IsARM;
  if ((FB[ARM::FeatureNaClTrap]))
    Features |= Feature_UseNaClTrap;
  if ((!FB[ARM::FeatureNoNegativeImmediates]))
    Features |= Feature_UseNegativeImmediates;
  return Features;
}

void ARMMCCodeEmitter::verifyInstructionPredicates(
    const MCInst &Inst, uint64_t AvailableFeatures) const {
#ifndef NDEBUG
  static uint64_t RequiredFeatures[] = {
    0, // PHI = 0
    0, // INLINEASM = 1
    0, // CFI_INSTRUCTION = 2
    0, // EH_LABEL = 3
    0, // GC_LABEL = 4
    0, // ANNOTATION_LABEL = 5
    0, // KILL = 6
    0, // EXTRACT_SUBREG = 7
    0, // INSERT_SUBREG = 8
    0, // IMPLICIT_DEF = 9
    0, // SUBREG_TO_REG = 10
    0, // COPY_TO_REGCLASS = 11
    0, // DBG_VALUE = 12
    0, // DBG_LABEL = 13
    0, // REG_SEQUENCE = 14
    0, // COPY = 15
    0, // BUNDLE = 16
    0, // LIFETIME_START = 17
    0, // LIFETIME_END = 18
    0, // STACKMAP = 19
    0, // FENTRY_CALL = 20
    0, // PATCHPOINT = 21
    0, // LOAD_STACK_GUARD = 22
    0, // STATEPOINT = 23
    0, // LOCAL_ESCAPE = 24
    0, // FAULTING_OP = 25
    0, // PATCHABLE_OP = 26
    0, // PATCHABLE_FUNCTION_ENTER = 27
    0, // PATCHABLE_RET = 28
    0, // PATCHABLE_FUNCTION_EXIT = 29
    0, // PATCHABLE_TAIL_CALL = 30
    0, // PATCHABLE_EVENT_CALL = 31
    0, // PATCHABLE_TYPED_EVENT_CALL = 32
    0, // ICALL_BRANCH_FUNNEL = 33
    0, // G_ADD = 34
    0, // G_SUB = 35
    0, // G_MUL = 36
    0, // G_SDIV = 37
    0, // G_UDIV = 38
    0, // G_SREM = 39
    0, // G_UREM = 40
    0, // G_AND = 41
    0, // G_OR = 42
    0, // G_XOR = 43
    0, // G_IMPLICIT_DEF = 44
    0, // G_PHI = 45
    0, // G_FRAME_INDEX = 46
    0, // G_GLOBAL_VALUE = 47
    0, // G_EXTRACT = 48
    0, // G_UNMERGE_VALUES = 49
    0, // G_INSERT = 50
    0, // G_MERGE_VALUES = 51
    0, // G_PTRTOINT = 52
    0, // G_INTTOPTR = 53
    0, // G_BITCAST = 54
    0, // G_LOAD = 55
    0, // G_SEXTLOAD = 56
    0, // G_ZEXTLOAD = 57
    0, // G_STORE = 58
    0, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59
    0, // G_ATOMIC_CMPXCHG = 60
    0, // G_ATOMICRMW_XCHG = 61
    0, // G_ATOMICRMW_ADD = 62
    0, // G_ATOMICRMW_SUB = 63
    0, // G_ATOMICRMW_AND = 64
    0, // G_ATOMICRMW_NAND = 65
    0, // G_ATOMICRMW_OR = 66
    0, // G_ATOMICRMW_XOR = 67
    0, // G_ATOMICRMW_MAX = 68
    0, // G_ATOMICRMW_MIN = 69
    0, // G_ATOMICRMW_UMAX = 70
    0, // G_ATOMICRMW_UMIN = 71
    0, // G_BRCOND = 72
    0, // G_BRINDIRECT = 73
    0, // G_INTRINSIC = 74
    0, // G_INTRINSIC_W_SIDE_EFFECTS = 75
    0, // G_ANYEXT = 76
    0, // G_TRUNC = 77
    0, // G_CONSTANT = 78
    0, // G_FCONSTANT = 79
    0, // G_VASTART = 80
    0, // G_VAARG = 81
    0, // G_SEXT = 82
    0, // G_ZEXT = 83
    0, // G_SHL = 84
    0, // G_LSHR = 85
    0, // G_ASHR = 86
    0, // G_ICMP = 87
    0, // G_FCMP = 88
    0, // G_SELECT = 89
    0, // G_UADDE = 90
    0, // G_USUBE = 91
    0, // G_SADDO = 92
    0, // G_SSUBO = 93
    0, // G_UMULO = 94
    0, // G_SMULO = 95
    0, // G_UMULH = 96
    0, // G_SMULH = 97
    0, // G_FADD = 98
    0, // G_FSUB = 99
    0, // G_FMUL = 100
    0, // G_FMA = 101
    0, // G_FDIV = 102
    0, // G_FREM = 103
    0, // G_FPOW = 104
    0, // G_FEXP = 105
    0, // G_FEXP2 = 106
    0, // G_FLOG = 107
    0, // G_FLOG2 = 108
    0, // G_FNEG = 109
    0, // G_FPEXT = 110
    0, // G_FPTRUNC = 111
    0, // G_FPTOSI = 112
    0, // G_FPTOUI = 113
    0, // G_SITOFP = 114
    0, // G_UITOFP = 115
    0, // G_FABS = 116
    0, // G_GEP = 117
    0, // G_PTR_MASK = 118
    0, // G_BR = 119
    0, // G_INSERT_VECTOR_ELT = 120
    0, // G_EXTRACT_VECTOR_ELT = 121
    0, // G_SHUFFLE_VECTOR = 122
    0, // G_BSWAP = 123
    0, // G_ADDRSPACE_CAST = 124
    0, // G_BLOCK_ADDR = 125
    Feature_IsARM | 0, // ABS = 126
    Feature_IsARM | 0, // ADDSri = 127
    Feature_IsARM | 0, // ADDSrr = 128
    Feature_IsARM | 0, // ADDSrsi = 129
    Feature_IsARM | 0, // ADDSrsr = 130
    0, // ADJCALLSTACKDOWN = 131
    0, // ADJCALLSTACKUP = 132
    Feature_IsARM | 0, // ASRi = 133
    Feature_IsARM | 0, // ASRr = 134
    Feature_IsARM | 0, // B = 135
    0, // BCCZi64 = 136
    0, // BCCi64 = 137
    Feature_IsARM | 0, // BMOVPCB_CALL = 138
    Feature_IsARM | 0, // BMOVPCRX_CALL = 139
    Feature_IsARM | 0, // BR_JTadd = 140
    Feature_IsARM | 0, // BR_JTm_i12 = 141
    Feature_IsARM | 0, // BR_JTm_rs = 142
    Feature_IsARM | 0, // BR_JTr = 143
    Feature_IsARM | Feature_HasV4T | 0, // BX_CALL = 144
    0, // CMP_SWAP_16 = 145
    0, // CMP_SWAP_32 = 146
    0, // CMP_SWAP_64 = 147
    0, // CMP_SWAP_8 = 148
    0, // CONSTPOOL_ENTRY = 149
    0, // COPY_STRUCT_BYVAL_I32 = 150
    0, // CompilerBarrier = 151
    Feature_IsARM | 0, // ITasm = 152
    0, // Int_eh_sjlj_dispatchsetup = 153
    Feature_IsARM | 0, // Int_eh_sjlj_longjmp = 154
    Feature_IsARM | Feature_HasVFP2 | 0, // Int_eh_sjlj_setjmp = 155
    Feature_IsARM | 0, // Int_eh_sjlj_setjmp_nofp = 156
    0, // Int_eh_sjlj_setup_dispatch = 157
    0, // JUMPTABLE_ADDRS = 158
    0, // JUMPTABLE_INSTS = 159
    0, // JUMPTABLE_TBB = 160
    0, // JUMPTABLE_TBH = 161
    Feature_IsARM | 0, // LDMIA_RET = 162
    Feature_IsARM | 0, // LDRBT_POST = 163
    Feature_IsARM | 0, // LDRConstPool = 164
    Feature_IsARM | 0, // LDRLIT_ga_abs = 165
    Feature_IsARM | 0, // LDRLIT_ga_pcrel = 166
    Feature_IsARM | 0, // LDRLIT_ga_pcrel_ldr = 167
    Feature_IsARM | 0, // LDRT_POST = 168
    Feature_IsARM | 0, // LEApcrel = 169
    Feature_IsARM | 0, // LEApcrelJT = 170
    Feature_IsARM | 0, // LSLi = 171
    Feature_IsARM | 0, // LSLr = 172
    Feature_IsARM | 0, // LSRi = 173
    Feature_IsARM | 0, // LSRr = 174
    0, // MEMCPY = 175
    Feature_IsARM | 0, // MLAv5 = 176
    Feature_IsARM | 0, // MOVCCi = 177
    Feature_IsARM | Feature_HasV6T2 | 0, // MOVCCi16 = 178
    Feature_IsARM | Feature_HasV6T2 | 0, // MOVCCi32imm = 179
    Feature_IsARM | 0, // MOVCCr = 180
    Feature_IsARM | 0, // MOVCCsi = 181
    Feature_IsARM | 0, // MOVCCsr = 182
    Feature_IsARM | 0, // MOVPCRX = 183
    0, // MOVTi16_ga_pcrel = 184
    Feature_IsARM | 0, // MOV_ga_pcrel = 185
    Feature_IsARM | 0, // MOV_ga_pcrel_ldr = 186
    0, // MOVi16_ga_pcrel = 187
    Feature_IsARM | 0, // MOVi32imm = 188
    Feature_IsARM | 0, // MOVsra_flag = 189
    Feature_IsARM | 0, // MOVsrl_flag = 190
    Feature_IsARM | 0, // MULv5 = 191
    Feature_IsARM | 0, // MVNCCi = 192
    Feature_IsARM | 0, // PICADD = 193
    Feature_IsARM | 0, // PICLDR = 194
    Feature_IsARM | 0, // PICLDRB = 195
    Feature_IsARM | 0, // PICLDRH = 196
    Feature_IsARM | 0, // PICLDRSB = 197
    Feature_IsARM | 0, // PICLDRSH = 198
    Feature_IsARM | 0, // PICSTR = 199
    Feature_IsARM | 0, // PICSTRB = 200
    Feature_IsARM | 0, // PICSTRH = 201
    Feature_IsARM | 0, // RORi = 202
    Feature_IsARM | 0, // RORr = 203
    Feature_IsARM | 0, // RRX = 204
    Feature_IsARM | 0, // RRXi = 205
    Feature_IsARM | 0, // RSBSri = 206
    Feature_IsARM | 0, // RSBSrsi = 207
    Feature_IsARM | 0, // RSBSrsr = 208
    Feature_IsARM | 0, // SMLALv5 = 209
    Feature_IsARM | 0, // SMULLv5 = 210
    0, // SPACE = 211
    Feature_IsARM | 0, // STRBT_POST = 212
    Feature_IsARM | 0, // STRBi_preidx = 213
    Feature_IsARM | 0, // STRBr_preidx = 214
    Feature_IsARM | 0, // STRH_preidx = 215
    Feature_IsARM | 0, // STRT_POST = 216
    Feature_IsARM | 0, // STRi_preidx = 217
    Feature_IsARM | 0, // STRr_preidx = 218
    Feature_IsARM | 0, // SUBS_PC_LR = 219
    Feature_IsARM | 0, // SUBSri = 220
    Feature_IsARM | 0, // SUBSrr = 221
    Feature_IsARM | 0, // SUBSrsi = 222
    Feature_IsARM | 0, // SUBSrsr = 223
    Feature_IsARM | 0, // TAILJMPd = 224
    Feature_IsARM | Feature_HasV4T | 0, // TAILJMPr = 225
    Feature_IsARM | 0, // TAILJMPr4 = 226
    0, // TCRETURNdi = 227
    0, // TCRETURNri = 228
    Feature_IsARM | 0, // TPsoft = 229
    Feature_IsARM | 0, // UMLALv5 = 230
    Feature_IsARM | 0, // UMULLv5 = 231
    Feature_HasNEON | 0, // VLD1LNdAsm_16 = 232
    Feature_HasNEON | 0, // VLD1LNdAsm_32 = 233
    Feature_HasNEON | 0, // VLD1LNdAsm_8 = 234
    Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_16 = 235
    Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_32 = 236
    Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_8 = 237
    Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_16 = 238
    Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_32 = 239
    Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_8 = 240
    Feature_HasNEON | 0, // VLD2LNdAsm_16 = 241
    Feature_HasNEON | 0, // VLD2LNdAsm_32 = 242
    Feature_HasNEON | 0, // VLD2LNdAsm_8 = 243
    Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_16 = 244
    Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_32 = 245
    Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_8 = 246
    Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_16 = 247
    Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_32 = 248
    Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_8 = 249
    Feature_HasNEON | 0, // VLD2LNqAsm_16 = 250
    Feature_HasNEON | 0, // VLD2LNqAsm_32 = 251
    Feature_HasNEON | 0, // VLD2LNqWB_fixed_Asm_16 = 252
    Feature_HasNEON | 0, // VLD2LNqWB_fixed_Asm_32 = 253
    Feature_HasNEON | 0, // VLD2LNqWB_register_Asm_16 = 254
    Feature_HasNEON | 0, // VLD2LNqWB_register_Asm_32 = 255
    Feature_HasNEON | 0, // VLD3DUPdAsm_16 = 256
    Feature_HasNEON | 0, // VLD3DUPdAsm_32 = 257
    Feature_HasNEON | 0, // VLD3DUPdAsm_8 = 258
    Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_16 = 259
    Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_32 = 260
    Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_8 = 261
    Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_16 = 262
    Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_32 = 263
    Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_8 = 264
    Feature_HasNEON | 0, // VLD3DUPqAsm_16 = 265
    Feature_HasNEON | 0, // VLD3DUPqAsm_32 = 266
    Feature_HasNEON | 0, // VLD3DUPqAsm_8 = 267
    Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_16 = 268
    Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_32 = 269
    Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_8 = 270
    Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_16 = 271
    Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_32 = 272
    Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_8 = 273
    Feature_HasNEON | 0, // VLD3LNdAsm_16 = 274
    Feature_HasNEON | 0, // VLD3LNdAsm_32 = 275
    Feature_HasNEON | 0, // VLD3LNdAsm_8 = 276
    Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_16 = 277
    Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_32 = 278
    Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_8 = 279
    Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_16 = 280
    Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_32 = 281
    Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_8 = 282
    Feature_HasNEON | 0, // VLD3LNqAsm_16 = 283
    Feature_HasNEON | 0, // VLD3LNqAsm_32 = 284
    Feature_HasNEON | 0, // VLD3LNqWB_fixed_Asm_16 = 285
    Feature_HasNEON | 0, // VLD3LNqWB_fixed_Asm_32 = 286
    Feature_HasNEON | 0, // VLD3LNqWB_register_Asm_16 = 287
    Feature_HasNEON | 0, // VLD3LNqWB_register_Asm_32 = 288
    Feature_HasNEON | 0, // VLD3dAsm_16 = 289
    Feature_HasNEON | 0, // VLD3dAsm_32 = 290
    Feature_HasNEON | 0, // VLD3dAsm_8 = 291
    Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_16 = 292
    Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_32 = 293
    Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_8 = 294
    Feature_HasNEON | 0, // VLD3dWB_register_Asm_16 = 295
    Feature_HasNEON | 0, // VLD3dWB_register_Asm_32 = 296
    Feature_HasNEON | 0, // VLD3dWB_register_Asm_8 = 297
    Feature_HasNEON | 0, // VLD3qAsm_16 = 298
    Feature_HasNEON | 0, // VLD3qAsm_32 = 299
    Feature_HasNEON | 0, // VLD3qAsm_8 = 300
    Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_16 = 301
    Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_32 = 302
    Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_8 = 303
    Feature_HasNEON | 0, // VLD3qWB_register_Asm_16 = 304
    Feature_HasNEON | 0, // VLD3qWB_register_Asm_32 = 305
    Feature_HasNEON | 0, // VLD3qWB_register_Asm_8 = 306
    Feature_HasNEON | 0, // VLD4DUPdAsm_16 = 307
    Feature_HasNEON | 0, // VLD4DUPdAsm_32 = 308
    Feature_HasNEON | 0, // VLD4DUPdAsm_8 = 309
    Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_16 = 310
    Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_32 = 311
    Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_8 = 312
    Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_16 = 313
    Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_32 = 314
    Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_8 = 315
    Feature_HasNEON | 0, // VLD4DUPqAsm_16 = 316
    Feature_HasNEON | 0, // VLD4DUPqAsm_32 = 317
    Feature_HasNEON | 0, // VLD4DUPqAsm_8 = 318
    Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_16 = 319
    Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_32 = 320
    Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_8 = 321
    Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_16 = 322
    Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_32 = 323
    Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_8 = 324
    Feature_HasNEON | 0, // VLD4LNdAsm_16 = 325
    Feature_HasNEON | 0, // VLD4LNdAsm_32 = 326
    Feature_HasNEON | 0, // VLD4LNdAsm_8 = 327
    Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_16 = 328
    Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_32 = 329
    Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_8 = 330
    Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_16 = 331
    Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_32 = 332
    Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_8 = 333
    Feature_HasNEON | 0, // VLD4LNqAsm_16 = 334
    Feature_HasNEON | 0, // VLD4LNqAsm_32 = 335
    Feature_HasNEON | 0, // VLD4LNqWB_fixed_Asm_16 = 336
    Feature_HasNEON | 0, // VLD4LNqWB_fixed_Asm_32 = 337
    Feature_HasNEON | 0, // VLD4LNqWB_register_Asm_16 = 338
    Feature_HasNEON | 0, // VLD4LNqWB_register_Asm_32 = 339
    Feature_HasNEON | 0, // VLD4dAsm_16 = 340
    Feature_HasNEON | 0, // VLD4dAsm_32 = 341
    Feature_HasNEON | 0, // VLD4dAsm_8 = 342
    Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_16 = 343
    Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_32 = 344
    Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_8 = 345
    Feature_HasNEON | 0, // VLD4dWB_register_Asm_16 = 346
    Feature_HasNEON | 0, // VLD4dWB_register_Asm_32 = 347
    Feature_HasNEON | 0, // VLD4dWB_register_Asm_8 = 348
    Feature_HasNEON | 0, // VLD4qAsm_16 = 349
    Feature_HasNEON | 0, // VLD4qAsm_32 = 350
    Feature_HasNEON | 0, // VLD4qAsm_8 = 351
    Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_16 = 352
    Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_32 = 353
    Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_8 = 354
    Feature_HasNEON | 0, // VLD4qWB_register_Asm_16 = 355
    Feature_HasNEON | 0, // VLD4qWB_register_Asm_32 = 356
    Feature_HasNEON | 0, // VLD4qWB_register_Asm_8 = 357
    0, // VMOVD0 = 358
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMOVDcc = 359
    0, // VMOVQ0 = 360
    Feature_HasVFP2 | 0, // VMOVScc = 361
    Feature_HasNEON | 0, // VST1LNdAsm_16 = 362
    Feature_HasNEON | 0, // VST1LNdAsm_32 = 363
    Feature_HasNEON | 0, // VST1LNdAsm_8 = 364
    Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_16 = 365
    Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_32 = 366
    Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_8 = 367
    Feature_HasNEON | 0, // VST1LNdWB_register_Asm_16 = 368
    Feature_HasNEON | 0, // VST1LNdWB_register_Asm_32 = 369
    Feature_HasNEON | 0, // VST1LNdWB_register_Asm_8 = 370
    Feature_HasNEON | 0, // VST2LNdAsm_16 = 371
    Feature_HasNEON | 0, // VST2LNdAsm_32 = 372
    Feature_HasNEON | 0, // VST2LNdAsm_8 = 373
    Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_16 = 374
    Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_32 = 375
    Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_8 = 376
    Feature_HasNEON | 0, // VST2LNdWB_register_Asm_16 = 377
    Feature_HasNEON | 0, // VST2LNdWB_register_Asm_32 = 378
    Feature_HasNEON | 0, // VST2LNdWB_register_Asm_8 = 379
    Feature_HasNEON | 0, // VST2LNqAsm_16 = 380
    Feature_HasNEON | 0, // VST2LNqAsm_32 = 381
    Feature_HasNEON | 0, // VST2LNqWB_fixed_Asm_16 = 382
    Feature_HasNEON | 0, // VST2LNqWB_fixed_Asm_32 = 383
    Feature_HasNEON | 0, // VST2LNqWB_register_Asm_16 = 384
    Feature_HasNEON | 0, // VST2LNqWB_register_Asm_32 = 385
    Feature_HasNEON | 0, // VST3LNdAsm_16 = 386
    Feature_HasNEON | 0, // VST3LNdAsm_32 = 387
    Feature_HasNEON | 0, // VST3LNdAsm_8 = 388
    Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_16 = 389
    Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_32 = 390
    Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_8 = 391
    Feature_HasNEON | 0, // VST3LNdWB_register_Asm_16 = 392
    Feature_HasNEON | 0, // VST3LNdWB_register_Asm_32 = 393
    Feature_HasNEON | 0, // VST3LNdWB_register_Asm_8 = 394
    Feature_HasNEON | 0, // VST3LNqAsm_16 = 395
    Feature_HasNEON | 0, // VST3LNqAsm_32 = 396
    Feature_HasNEON | 0, // VST3LNqWB_fixed_Asm_16 = 397
    Feature_HasNEON | 0, // VST3LNqWB_fixed_Asm_32 = 398
    Feature_HasNEON | 0, // VST3LNqWB_register_Asm_16 = 399
    Feature_HasNEON | 0, // VST3LNqWB_register_Asm_32 = 400
    Feature_HasNEON | 0, // VST3dAsm_16 = 401
    Feature_HasNEON | 0, // VST3dAsm_32 = 402
    Feature_HasNEON | 0, // VST3dAsm_8 = 403
    Feature_HasNEON | 0, // VST3dWB_fixed_Asm_16 = 404
    Feature_HasNEON | 0, // VST3dWB_fixed_Asm_32 = 405
    Feature_HasNEON | 0, // VST3dWB_fixed_Asm_8 = 406
    Feature_HasNEON | 0, // VST3dWB_register_Asm_16 = 407
    Feature_HasNEON | 0, // VST3dWB_register_Asm_32 = 408
    Feature_HasNEON | 0, // VST3dWB_register_Asm_8 = 409
    Feature_HasNEON | 0, // VST3qAsm_16 = 410
    Feature_HasNEON | 0, // VST3qAsm_32 = 411
    Feature_HasNEON | 0, // VST3qAsm_8 = 412
    Feature_HasNEON | 0, // VST3qWB_fixed_Asm_16 = 413
    Feature_HasNEON | 0, // VST3qWB_fixed_Asm_32 = 414
    Feature_HasNEON | 0, // VST3qWB_fixed_Asm_8 = 415
    Feature_HasNEON | 0, // VST3qWB_register_Asm_16 = 416
    Feature_HasNEON | 0, // VST3qWB_register_Asm_32 = 417
    Feature_HasNEON | 0, // VST3qWB_register_Asm_8 = 418
    Feature_HasNEON | 0, // VST4LNdAsm_16 = 419
    Feature_HasNEON | 0, // VST4LNdAsm_32 = 420
    Feature_HasNEON | 0, // VST4LNdAsm_8 = 421
    Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_16 = 422
    Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_32 = 423
    Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_8 = 424
    Feature_HasNEON | 0, // VST4LNdWB_register_Asm_16 = 425
    Feature_HasNEON | 0, // VST4LNdWB_register_Asm_32 = 426
    Feature_HasNEON | 0, // VST4LNdWB_register_Asm_8 = 427
    Feature_HasNEON | 0, // VST4LNqAsm_16 = 428
    Feature_HasNEON | 0, // VST4LNqAsm_32 = 429
    Feature_HasNEON | 0, // VST4LNqWB_fixed_Asm_16 = 430
    Feature_HasNEON | 0, // VST4LNqWB_fixed_Asm_32 = 431
    Feature_HasNEON | 0, // VST4LNqWB_register_Asm_16 = 432
    Feature_HasNEON | 0, // VST4LNqWB_register_Asm_32 = 433
    Feature_HasNEON | 0, // VST4dAsm_16 = 434
    Feature_HasNEON | 0, // VST4dAsm_32 = 435
    Feature_HasNEON | 0, // VST4dAsm_8 = 436
    Feature_HasNEON | 0, // VST4dWB_fixed_Asm_16 = 437
    Feature_HasNEON | 0, // VST4dWB_fixed_Asm_32 = 438
    Feature_HasNEON | 0, // VST4dWB_fixed_Asm_8 = 439
    Feature_HasNEON | 0, // VST4dWB_register_Asm_16 = 440
    Feature_HasNEON | 0, // VST4dWB_register_Asm_32 = 441
    Feature_HasNEON | 0, // VST4dWB_register_Asm_8 = 442
    Feature_HasNEON | 0, // VST4qAsm_16 = 443
    Feature_HasNEON | 0, // VST4qAsm_32 = 444
    Feature_HasNEON | 0, // VST4qAsm_8 = 445
    Feature_HasNEON | 0, // VST4qWB_fixed_Asm_16 = 446
    Feature_HasNEON | 0, // VST4qWB_fixed_Asm_32 = 447
    Feature_HasNEON | 0, // VST4qWB_fixed_Asm_8 = 448
    Feature_HasNEON | 0, // VST4qWB_register_Asm_16 = 449
    Feature_HasNEON | 0, // VST4qWB_register_Asm_32 = 450
    Feature_HasNEON | 0, // VST4qWB_register_Asm_8 = 451
    0, // WIN__CHKSTK = 452
    0, // WIN__DBZCHK = 453
    Feature_IsThumb2 | 0, // t2ABS = 454
    Feature_IsThumb2 | 0, // t2ADDSri = 455
    Feature_IsThumb2 | 0, // t2ADDSrr = 456
    Feature_IsThumb2 | 0, // t2ADDSrs = 457
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2BR_JT = 458
    Feature_IsThumb2 | 0, // t2LDMIA_RET = 459
    Feature_IsThumb2 | 0, // t2LDRBpcrel = 460
    Feature_IsThumb2 | 0, // t2LDRConstPool = 461
    Feature_IsThumb2 | 0, // t2LDRHpcrel = 462
    Feature_IsThumb2 | 0, // t2LDRSBpcrel = 463
    Feature_IsThumb2 | 0, // t2LDRSHpcrel = 464
    Feature_IsThumb2 | 0, // t2LDRpci_pic = 465
    Feature_IsThumb2 | 0, // t2LDRpcrel = 466
    Feature_IsThumb2 | 0, // t2LEApcrel = 467
    Feature_IsThumb2 | 0, // t2LEApcrelJT = 468
    Feature_IsThumb2 | 0, // t2MOVCCasr = 469
    Feature_IsThumb2 | 0, // t2MOVCCi = 470
    Feature_IsThumb2 | 0, // t2MOVCCi16 = 471
    Feature_IsThumb2 | 0, // t2MOVCCi32imm = 472
    Feature_IsThumb2 | 0, // t2MOVCClsl = 473
    Feature_IsThumb2 | 0, // t2MOVCClsr = 474
    Feature_IsThumb2 | 0, // t2MOVCCr = 475
    Feature_IsThumb2 | 0, // t2MOVCCror = 476
    Feature_IsThumb2 | 0, // t2MOVSsi = 477
    Feature_IsThumb2 | 0, // t2MOVSsr = 478
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVTi16_ga_pcrel = 479
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOV_ga_pcrel = 480
    0, // t2MOVi16_ga_pcrel = 481
    Feature_IsThumb | 0, // t2MOVi32imm = 482
    Feature_IsThumb2 | 0, // t2MOVsi = 483
    Feature_IsThumb2 | 0, // t2MOVsr = 484
    Feature_IsThumb2 | 0, // t2MVNCCi = 485
    Feature_IsThumb2 | 0, // t2RSBSri = 486
    Feature_IsThumb2 | 0, // t2RSBSrs = 487
    Feature_IsThumb2 | 0, // t2STRB_preidx = 488
    Feature_IsThumb2 | 0, // t2STRH_preidx = 489
    Feature_IsThumb2 | 0, // t2STR_preidx = 490
    Feature_IsThumb2 | 0, // t2SUBSri = 491
    Feature_IsThumb2 | 0, // t2SUBSrr = 492
    Feature_IsThumb2 | 0, // t2SUBSrs = 493
    Feature_IsThumb2 | 0, // t2TBB_JT = 494
    Feature_IsThumb2 | 0, // t2TBH_JT = 495
    0, // tADCS = 496
    0, // tADDSi3 = 497
    0, // tADDSi8 = 498
    0, // tADDSrr = 499
    Feature_IsThumb | 0, // tADDframe = 500
    Feature_IsThumb | 0, // tADJCALLSTACKDOWN = 501
    Feature_IsThumb | 0, // tADJCALLSTACKUP = 502
    Feature_IsThumb | 0, // tBRIND = 503
    Feature_IsThumb | 0, // tBR_JTr = 504
    Feature_IsThumb | 0, // tBX_CALL = 505
    Feature_IsThumb | 0, // tBX_RET = 506
    Feature_IsThumb | 0, // tBX_RET_vararg = 507
    Feature_IsThumb | 0, // tBfar = 508
    Feature_IsThumb | 0, // tLDMIA_UPD = 509
    Feature_IsThumb | 0, // tLDRConstPool = 510
    Feature_IsThumb | 0, // tLDRLIT_ga_abs = 511
    Feature_IsThumb | 0, // tLDRLIT_ga_pcrel = 512
    Feature_IsThumb | 0, // tLDR_postidx = 513
    Feature_IsThumb | 0, // tLDRpci_pic = 514
    Feature_IsThumb | 0, // tLEApcrel = 515
    Feature_IsThumb | 0, // tLEApcrelJT = 516
    0, // tMOVCCr_pseudo = 517
    Feature_IsThumb | 0, // tPOP_RET = 518
    0, // tSBCS = 519
    0, // tSUBSi3 = 520
    0, // tSUBSi8 = 521
    0, // tSUBSrr = 522
    Feature_IsThumb2 | 0, // tTAILJMPd = 523
    Feature_IsThumb | 0, // tTAILJMPdND = 524
    Feature_IsThumb | 0, // tTAILJMPr = 525
    Feature_IsThumb | 0, // tTBB_JT = 526
    Feature_IsThumb | 0, // tTBH_JT = 527
    Feature_IsThumb | 0, // tTPsoft = 528
    Feature_IsARM | 0, // ADCri = 529
    Feature_IsARM | 0, // ADCrr = 530
    Feature_IsARM | 0, // ADCrsi = 531
    Feature_IsARM | 0, // ADCrsr = 532
    Feature_IsARM | 0, // ADDri = 533
    Feature_IsARM | 0, // ADDrr = 534
    Feature_IsARM | 0, // ADDrsi = 535
    Feature_IsARM | 0, // ADDrsr = 536
    Feature_IsARM | 0, // ADR = 537
    Feature_HasV8 | Feature_HasCrypto | 0, // AESD = 538
    Feature_HasV8 | Feature_HasCrypto | 0, // AESE = 539
    Feature_HasV8 | Feature_HasCrypto | 0, // AESIMC = 540
    Feature_HasV8 | Feature_HasCrypto | 0, // AESMC = 541
    Feature_IsARM | 0, // ANDri = 542
    Feature_IsARM | 0, // ANDrr = 543
    Feature_IsARM | 0, // ANDrsi = 544
    Feature_IsARM | 0, // ANDrsr = 545
    Feature_IsARM | Feature_HasV6T2 | 0, // BFC = 546
    Feature_IsARM | Feature_HasV6T2 | 0, // BFI = 547
    Feature_IsARM | 0, // BICri = 548
    Feature_IsARM | 0, // BICrr = 549
    Feature_IsARM | 0, // BICrsi = 550
    Feature_IsARM | 0, // BICrsr = 551
    Feature_IsARM | 0, // BKPT = 552
    Feature_IsARM | 0, // BL = 553
    Feature_IsARM | Feature_HasV5T | 0, // BLX = 554
    Feature_IsARM | Feature_HasV5T | 0, // BLX_pred = 555
    Feature_IsARM | Feature_HasV5T | 0, // BLXi = 556
    Feature_IsARM | 0, // BL_pred = 557
    Feature_IsARM | Feature_HasV4T | 0, // BX = 558
    Feature_IsARM | 0, // BXJ = 559
    Feature_IsARM | Feature_HasV4T | 0, // BX_RET = 560
    Feature_IsARM | Feature_HasV4T | 0, // BX_pred = 561
    Feature_IsARM | 0, // Bcc = 562
    Feature_IsARM | Feature_PreV8 | 0, // CDP = 563
    Feature_IsARM | Feature_PreV8 | 0, // CDP2 = 564
    Feature_IsARM | Feature_HasV6K | 0, // CLREX = 565
    Feature_IsARM | Feature_HasV5T | 0, // CLZ = 566
    Feature_IsARM | 0, // CMNri = 567
    Feature_IsARM | 0, // CMNzrr = 568
    Feature_IsARM | 0, // CMNzrsi = 569
    Feature_IsARM | 0, // CMNzrsr = 570
    Feature_IsARM | 0, // CMPri = 571
    Feature_IsARM | 0, // CMPrr = 572
    Feature_IsARM | 0, // CMPrsi = 573
    Feature_IsARM | 0, // CMPrsr = 574
    Feature_IsARM | 0, // CPS1p = 575
    Feature_IsARM | 0, // CPS2p = 576
    Feature_IsARM | 0, // CPS3p = 577
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32B = 578
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CB = 579
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CH = 580
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CW = 581
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32H = 582
    Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32W = 583
    Feature_IsARM | Feature_HasV7 | 0, // DBG = 584
    Feature_IsARM | Feature_HasDB | 0, // DMB = 585
    Feature_IsARM | Feature_HasDB | 0, // DSB = 586
    Feature_IsARM | 0, // EORri = 587
    Feature_IsARM | 0, // EORrr = 588
    Feature_IsARM | 0, // EORrsi = 589
    Feature_IsARM | 0, // EORrsr = 590
    Feature_IsARM | Feature_HasVirtualization | 0, // ERET = 591
    Feature_HasVFP3 | Feature_HasDPVFP | 0, // FCONSTD = 592
    Feature_HasFullFP16 | 0, // FCONSTH = 593
    Feature_HasVFP3 | 0, // FCONSTS = 594
    Feature_HasVFP2 | 0, // FLDMXDB_UPD = 595
    Feature_HasVFP2 | 0, // FLDMXIA = 596
    Feature_HasVFP2 | 0, // FLDMXIA_UPD = 597
    Feature_HasVFP2 | 0, // FMSTAT = 598
    Feature_HasVFP2 | 0, // FSTMXDB_UPD = 599
    Feature_HasVFP2 | 0, // FSTMXIA = 600
    Feature_HasVFP2 | 0, // FSTMXIA_UPD = 601
    Feature_IsARM | Feature_HasV6 | 0, // HINT = 602
    Feature_IsARM | Feature_HasV8 | 0, // HLT = 603
    Feature_IsARM | Feature_HasVirtualization | 0, // HVC = 604
    Feature_IsARM | Feature_HasDB | 0, // ISB = 605
    Feature_IsARM | Feature_HasAcquireRelease | 0, // LDA = 606
    Feature_IsARM | Feature_HasAcquireRelease | 0, // LDAB = 607
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEX = 608
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXB = 609
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXD = 610
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXH = 611
    Feature_IsARM | Feature_HasAcquireRelease | 0, // LDAH = 612
    Feature_IsARM | Feature_PreV8 | 0, // LDC2L_OFFSET = 613
    Feature_IsARM | Feature_PreV8 | 0, // LDC2L_OPTION = 614
    Feature_IsARM | Feature_PreV8 | 0, // LDC2L_POST = 615
    Feature_IsARM | Feature_PreV8 | 0, // LDC2L_PRE = 616
    Feature_IsARM | Feature_PreV8 | 0, // LDC2_OFFSET = 617
    Feature_IsARM | Feature_PreV8 | 0, // LDC2_OPTION = 618
    Feature_IsARM | Feature_PreV8 | 0, // LDC2_POST = 619
    Feature_IsARM | Feature_PreV8 | 0, // LDC2_PRE = 620
    Feature_IsARM | 0, // LDCL_OFFSET = 621
    Feature_IsARM | 0, // LDCL_OPTION = 622
    Feature_IsARM | 0, // LDCL_POST = 623
    Feature_IsARM | 0, // LDCL_PRE = 624
    Feature_IsARM | 0, // LDC_OFFSET = 625
    Feature_IsARM | 0, // LDC_OPTION = 626
    Feature_IsARM | 0, // LDC_POST = 627
    Feature_IsARM | 0, // LDC_PRE = 628
    Feature_IsARM | 0, // LDMDA = 629
    Feature_IsARM | 0, // LDMDA_UPD = 630
    Feature_IsARM | 0, // LDMDB = 631
    Feature_IsARM | 0, // LDMDB_UPD = 632
    Feature_IsARM | 0, // LDMIA = 633
    Feature_IsARM | 0, // LDMIA_UPD = 634
    Feature_IsARM | 0, // LDMIB = 635
    Feature_IsARM | 0, // LDMIB_UPD = 636
    Feature_IsARM | 0, // LDRBT_POST_IMM = 637
    Feature_IsARM | 0, // LDRBT_POST_REG = 638
    Feature_IsARM | 0, // LDRB_POST_IMM = 639
    Feature_IsARM | 0, // LDRB_POST_REG = 640
    Feature_IsARM | 0, // LDRB_PRE_IMM = 641
    Feature_IsARM | 0, // LDRB_PRE_REG = 642
    Feature_IsARM | 0, // LDRBi12 = 643
    Feature_IsARM | 0, // LDRBrs = 644
    Feature_IsARM | Feature_HasV5TE | 0, // LDRD = 645
    Feature_IsARM | 0, // LDRD_POST = 646
    Feature_IsARM | 0, // LDRD_PRE = 647
    Feature_IsARM | 0, // LDREX = 648
    Feature_IsARM | 0, // LDREXB = 649
    Feature_IsARM | 0, // LDREXD = 650
    Feature_IsARM | 0, // LDREXH = 651
    Feature_IsARM | 0, // LDRH = 652
    Feature_IsARM | 0, // LDRHTi = 653
    Feature_IsARM | 0, // LDRHTr = 654
    Feature_IsARM | 0, // LDRH_POST = 655
    Feature_IsARM | 0, // LDRH_PRE = 656
    Feature_IsARM | 0, // LDRSB = 657
    Feature_IsARM | 0, // LDRSBTi = 658
    Feature_IsARM | 0, // LDRSBTr = 659
    Feature_IsARM | 0, // LDRSB_POST = 660
    Feature_IsARM | 0, // LDRSB_PRE = 661
    Feature_IsARM | 0, // LDRSH = 662
    Feature_IsARM | 0, // LDRSHTi = 663
    Feature_IsARM | 0, // LDRSHTr = 664
    Feature_IsARM | 0, // LDRSH_POST = 665
    Feature_IsARM | 0, // LDRSH_PRE = 666
    Feature_IsARM | 0, // LDRT_POST_IMM = 667
    Feature_IsARM | 0, // LDRT_POST_REG = 668
    Feature_IsARM | 0, // LDR_POST_IMM = 669
    Feature_IsARM | 0, // LDR_POST_REG = 670
    Feature_IsARM | 0, // LDR_PRE_IMM = 671
    Feature_IsARM | 0, // LDR_PRE_REG = 672
    Feature_IsARM | 0, // LDRcp = 673
    Feature_IsARM | 0, // LDRi12 = 674
    Feature_IsARM | 0, // LDRrs = 675
    Feature_IsARM | 0, // MCR = 676
    Feature_IsARM | Feature_PreV8 | 0, // MCR2 = 677
    Feature_IsARM | 0, // MCRR = 678
    Feature_IsARM | Feature_PreV8 | 0, // MCRR2 = 679
    Feature_IsARM | Feature_HasV6 | 0, // MLA = 680
    Feature_IsARM | Feature_HasV6T2 | 0, // MLS = 681
    Feature_IsARM | 0, // MOVPCLR = 682
    Feature_IsARM | Feature_HasV6T2 | 0, // MOVTi16 = 683
    Feature_IsARM | 0, // MOVi = 684
    Feature_IsARM | Feature_HasV6T2 | 0, // MOVi16 = 685
    Feature_IsARM | 0, // MOVr = 686
    Feature_IsARM | 0, // MOVr_TC = 687
    Feature_IsARM | 0, // MOVsi = 688
    Feature_IsARM | 0, // MOVsr = 689
    Feature_IsARM | 0, // MRC = 690
    Feature_IsARM | Feature_PreV8 | 0, // MRC2 = 691
    Feature_IsARM | 0, // MRRC = 692
    Feature_IsARM | Feature_PreV8 | 0, // MRRC2 = 693
    Feature_IsARM | 0, // MRS = 694
    Feature_IsARM | Feature_HasVirtualization | 0, // MRSbanked = 695
    Feature_IsARM | 0, // MRSsys = 696
    Feature_IsARM | 0, // MSR = 697
    Feature_IsARM | Feature_HasVirtualization | 0, // MSRbanked = 698
    Feature_IsARM | 0, // MSRi = 699
    Feature_IsARM | Feature_HasV6 | 0, // MUL = 700
    Feature_IsARM | 0, // MVNi = 701
    Feature_IsARM | 0, // MVNr = 702
    Feature_IsARM | 0, // MVNsi = 703
    Feature_IsARM | 0, // MVNsr = 704
    Feature_IsARM | 0, // ORRri = 705
    Feature_IsARM | 0, // ORRrr = 706
    Feature_IsARM | 0, // ORRrsi = 707
    Feature_IsARM | 0, // ORRrsr = 708
    Feature_IsARM | Feature_HasV6 | 0, // PKHBT = 709
    Feature_IsARM | Feature_HasV6 | 0, // PKHTB = 710
    Feature_IsARM | Feature_HasV7 | Feature_HasMP | 0, // PLDWi12 = 711
    Feature_IsARM | Feature_HasV7 | Feature_HasMP | 0, // PLDWrs = 712
    Feature_IsARM | 0, // PLDi12 = 713
    Feature_IsARM | 0, // PLDrs = 714
    Feature_IsARM | Feature_HasV7 | 0, // PLIi12 = 715
    Feature_IsARM | Feature_HasV7 | 0, // PLIrs = 716
    Feature_IsARM | 0, // QADD = 717
    Feature_IsARM | 0, // QADD16 = 718
    Feature_IsARM | 0, // QADD8 = 719
    Feature_IsARM | 0, // QASX = 720
    Feature_IsARM | 0, // QDADD = 721
    Feature_IsARM | 0, // QDSUB = 722
    Feature_IsARM | 0, // QSAX = 723
    Feature_IsARM | 0, // QSUB = 724
    Feature_IsARM | 0, // QSUB16 = 725
    Feature_IsARM | 0, // QSUB8 = 726
    Feature_IsARM | Feature_HasV6T2 | 0, // RBIT = 727
    Feature_IsARM | Feature_HasV6 | 0, // REV = 728
    Feature_IsARM | Feature_HasV6 | 0, // REV16 = 729
    Feature_IsARM | Feature_HasV6 | 0, // REVSH = 730
    Feature_IsARM | 0, // RFEDA = 731
    Feature_IsARM | 0, // RFEDA_UPD = 732
    Feature_IsARM | 0, // RFEDB = 733
    Feature_IsARM | 0, // RFEDB_UPD = 734
    Feature_IsARM | 0, // RFEIA = 735
    Feature_IsARM | 0, // RFEIA_UPD = 736
    Feature_IsARM | 0, // RFEIB = 737
    Feature_IsARM | 0, // RFEIB_UPD = 738
    Feature_IsARM | 0, // RSBri = 739
    Feature_IsARM | 0, // RSBrr = 740
    Feature_IsARM | 0, // RSBrsi = 741
    Feature_IsARM | 0, // RSBrsr = 742
    Feature_IsARM | 0, // RSCri = 743
    Feature_IsARM | 0, // RSCrr = 744
    Feature_IsARM | 0, // RSCrsi = 745
    Feature_IsARM | 0, // RSCrsr = 746
    Feature_IsARM | 0, // SADD16 = 747
    Feature_IsARM | 0, // SADD8 = 748
    Feature_IsARM | 0, // SASX = 749
    Feature_IsARM | 0, // SBCri = 750
    Feature_IsARM | 0, // SBCrr = 751
    Feature_IsARM | 0, // SBCrsi = 752
    Feature_IsARM | 0, // SBCrsr = 753
    Feature_IsARM | Feature_HasV6T2 | 0, // SBFX = 754
    Feature_IsARM | Feature_HasDivideInARM | 0, // SDIV = 755
    Feature_IsARM | Feature_HasV6 | 0, // SEL = 756
    Feature_IsARM | 0, // SETEND = 757
    Feature_IsARM | Feature_HasV8 | Feature_HasV8_1a | 0, // SETPAN = 758
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1C = 759
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1H = 760
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1M = 761
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1P = 762
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1SU0 = 763
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA1SU1 = 764
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA256H = 765
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA256H2 = 766
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA256SU0 = 767
    Feature_HasV8 | Feature_HasCrypto | 0, // SHA256SU1 = 768
    Feature_IsARM | 0, // SHADD16 = 769
    Feature_IsARM | 0, // SHADD8 = 770
    Feature_IsARM | 0, // SHASX = 771
    Feature_IsARM | 0, // SHSAX = 772
    Feature_IsARM | 0, // SHSUB16 = 773
    Feature_IsARM | 0, // SHSUB8 = 774
    Feature_IsARM | Feature_HasTrustZone | 0, // SMC = 775
    Feature_IsARM | Feature_HasV5TE | 0, // SMLABB = 776
    Feature_IsARM | Feature_HasV5TE | 0, // SMLABT = 777
    Feature_IsARM | Feature_HasV6 | 0, // SMLAD = 778
    Feature_IsARM | Feature_HasV6 | 0, // SMLADX = 779
    Feature_IsARM | Feature_HasV6 | 0, // SMLAL = 780
    Feature_IsARM | Feature_HasV5TE | 0, // SMLALBB = 781
    Feature_IsARM | Feature_HasV5TE | 0, // SMLALBT = 782
    Feature_IsARM | Feature_HasV6 | 0, // SMLALD = 783
    Feature_IsARM | Feature_HasV6 | 0, // SMLALDX = 784
    Feature_IsARM | Feature_HasV5TE | 0, // SMLALTB = 785
    Feature_IsARM | Feature_HasV5TE | 0, // SMLALTT = 786
    Feature_IsARM | Feature_HasV5TE | 0, // SMLATB = 787
    Feature_IsARM | Feature_HasV5TE | 0, // SMLATT = 788
    Feature_IsARM | Feature_HasV5TE | 0, // SMLAWB = 789
    Feature_IsARM | Feature_HasV5TE | 0, // SMLAWT = 790
    Feature_IsARM | Feature_HasV6 | 0, // SMLSD = 791
    Feature_IsARM | Feature_HasV6 | 0, // SMLSDX = 792
    Feature_IsARM | Feature_HasV6 | 0, // SMLSLD = 793
    Feature_IsARM | Feature_HasV6 | 0, // SMLSLDX = 794
    Feature_IsARM | Feature_HasV6 | 0, // SMMLA = 795
    Feature_IsARM | Feature_HasV6 | 0, // SMMLAR = 796
    Feature_IsARM | Feature_HasV6 | 0, // SMMLS = 797
    Feature_IsARM | Feature_HasV6 | 0, // SMMLSR = 798
    Feature_IsARM | Feature_HasV6 | 0, // SMMUL = 799
    Feature_IsARM | Feature_HasV6 | 0, // SMMULR = 800
    Feature_IsARM | Feature_HasV6 | 0, // SMUAD = 801
    Feature_IsARM | Feature_HasV6 | 0, // SMUADX = 802
    Feature_IsARM | Feature_HasV5TE | 0, // SMULBB = 803
    Feature_IsARM | Feature_HasV5TE | 0, // SMULBT = 804
    Feature_IsARM | Feature_HasV6 | 0, // SMULL = 805
    Feature_IsARM | Feature_HasV5TE | 0, // SMULTB = 806
    Feature_IsARM | Feature_HasV5TE | 0, // SMULTT = 807
    Feature_IsARM | Feature_HasV5TE | 0, // SMULWB = 808
    Feature_IsARM | Feature_HasV5TE | 0, // SMULWT = 809
    Feature_IsARM | Feature_HasV6 | 0, // SMUSD = 810
    Feature_IsARM | Feature_HasV6 | 0, // SMUSDX = 811
    Feature_IsARM | 0, // SRSDA = 812
    Feature_IsARM | 0, // SRSDA_UPD = 813
    Feature_IsARM | 0, // SRSDB = 814
    Feature_IsARM | 0, // SRSDB_UPD = 815
    Feature_IsARM | 0, // SRSIA = 816
    Feature_IsARM | 0, // SRSIA_UPD = 817
    Feature_IsARM | 0, // SRSIB = 818
    Feature_IsARM | 0, // SRSIB_UPD = 819
    Feature_IsARM | Feature_HasV6 | 0, // SSAT = 820
    Feature_IsARM | Feature_HasV6 | 0, // SSAT16 = 821
    Feature_IsARM | 0, // SSAX = 822
    Feature_IsARM | 0, // SSUB16 = 823
    Feature_IsARM | 0, // SSUB8 = 824
    Feature_IsARM | Feature_PreV8 | 0, // STC2L_OFFSET = 825
    Feature_IsARM | Feature_PreV8 | 0, // STC2L_OPTION = 826
    Feature_IsARM | Feature_PreV8 | 0, // STC2L_POST = 827
    Feature_IsARM | Feature_PreV8 | 0, // STC2L_PRE = 828
    Feature_IsARM | Feature_PreV8 | 0, // STC2_OFFSET = 829
    Feature_IsARM | Feature_PreV8 | 0, // STC2_OPTION = 830
    Feature_IsARM | Feature_PreV8 | 0, // STC2_POST = 831
    Feature_IsARM | Feature_PreV8 | 0, // STC2_PRE = 832
    Feature_IsARM | 0, // STCL_OFFSET = 833
    Feature_IsARM | 0, // STCL_OPTION = 834
    Feature_IsARM | 0, // STCL_POST = 835
    Feature_IsARM | 0, // STCL_PRE = 836
    Feature_IsARM | 0, // STC_OFFSET = 837
    Feature_IsARM | 0, // STC_OPTION = 838
    Feature_IsARM | 0, // STC_POST = 839
    Feature_IsARM | 0, // STC_PRE = 840
    Feature_IsARM | Feature_HasAcquireRelease | 0, // STL = 841
    Feature_IsARM | Feature_HasAcquireRelease | 0, // STLB = 842
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEX = 843
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXB = 844
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXD = 845
    Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXH = 846
    Feature_IsARM | Feature_HasAcquireRelease | 0, // STLH = 847
    Feature_IsARM | 0, // STMDA = 848
    Feature_IsARM | 0, // STMDA_UPD = 849
    Feature_IsARM | 0, // STMDB = 850
    Feature_IsARM | 0, // STMDB_UPD = 851
    Feature_IsARM | 0, // STMIA = 852
    Feature_IsARM | 0, // STMIA_UPD = 853
    Feature_IsARM | 0, // STMIB = 854
    Feature_IsARM | 0, // STMIB_UPD = 855
    Feature_IsARM | 0, // STRBT_POST_IMM = 856
    Feature_IsARM | 0, // STRBT_POST_REG = 857
    Feature_IsARM | 0, // STRB_POST_IMM = 858
    Feature_IsARM | 0, // STRB_POST_REG = 859
    Feature_IsARM | 0, // STRB_PRE_IMM = 860
    Feature_IsARM | 0, // STRB_PRE_REG = 861
    Feature_IsARM | 0, // STRBi12 = 862
    Feature_IsARM | 0, // STRBrs = 863
    Feature_IsARM | Feature_HasV5TE | 0, // STRD = 864
    Feature_IsARM | 0, // STRD_POST = 865
    Feature_IsARM | 0, // STRD_PRE = 866
    Feature_IsARM | 0, // STREX = 867
    Feature_IsARM | 0, // STREXB = 868
    Feature_IsARM | 0, // STREXD = 869
    Feature_IsARM | 0, // STREXH = 870
    Feature_IsARM | 0, // STRH = 871
    Feature_IsARM | 0, // STRHTi = 872
    Feature_IsARM | 0, // STRHTr = 873
    Feature_IsARM | 0, // STRH_POST = 874
    Feature_IsARM | 0, // STRH_PRE = 875
    Feature_IsARM | 0, // STRT_POST_IMM = 876
    Feature_IsARM | 0, // STRT_POST_REG = 877
    Feature_IsARM | 0, // STR_POST_IMM = 878
    Feature_IsARM | 0, // STR_POST_REG = 879
    Feature_IsARM | 0, // STR_PRE_IMM = 880
    Feature_IsARM | 0, // STR_PRE_REG = 881
    Feature_IsARM | 0, // STRi12 = 882
    Feature_IsARM | 0, // STRrs = 883
    Feature_IsARM | 0, // SUBri = 884
    Feature_IsARM | 0, // SUBrr = 885
    Feature_IsARM | 0, // SUBrsi = 886
    Feature_IsARM | 0, // SUBrsr = 887
    Feature_IsARM | 0, // SVC = 888
    Feature_IsARM | Feature_PreV8 | 0, // SWP = 889
    Feature_IsARM | Feature_PreV8 | 0, // SWPB = 890
    Feature_IsARM | Feature_HasV6 | 0, // SXTAB = 891
    Feature_IsARM | Feature_HasV6 | 0, // SXTAB16 = 892
    Feature_IsARM | Feature_HasV6 | 0, // SXTAH = 893
    Feature_IsARM | Feature_HasV6 | 0, // SXTB = 894
    Feature_IsARM | Feature_HasV6 | 0, // SXTB16 = 895
    Feature_IsARM | Feature_HasV6 | 0, // SXTH = 896
    Feature_IsARM | 0, // TEQri = 897
    Feature_IsARM | 0, // TEQrr = 898
    Feature_IsARM | 0, // TEQrsi = 899
    Feature_IsARM | 0, // TEQrsr = 900
    Feature_IsARM | 0, // TRAP = 901
    Feature_IsARM | Feature_UseNaClTrap | 0, // TRAPNaCl = 902
    Feature_IsARM | Feature_HasV8_4a | 0, // TSB = 903
    Feature_IsARM | 0, // TSTri = 904
    Feature_IsARM | 0, // TSTrr = 905
    Feature_IsARM | 0, // TSTrsi = 906
    Feature_IsARM | 0, // TSTrsr = 907
    Feature_IsARM | 0, // UADD16 = 908
    Feature_IsARM | 0, // UADD8 = 909
    Feature_IsARM | 0, // UASX = 910
    Feature_IsARM | Feature_HasV6T2 | 0, // UBFX = 911
    Feature_IsARM | 0, // UDF = 912
    Feature_IsARM | Feature_HasDivideInARM | 0, // UDIV = 913
    Feature_IsARM | 0, // UHADD16 = 914
    Feature_IsARM | 0, // UHADD8 = 915
    Feature_IsARM | 0, // UHASX = 916
    Feature_IsARM | 0, // UHSAX = 917
    Feature_IsARM | 0, // UHSUB16 = 918
    Feature_IsARM | 0, // UHSUB8 = 919
    Feature_IsARM | Feature_HasV6 | 0, // UMAAL = 920
    Feature_IsARM | Feature_HasV6 | 0, // UMLAL = 921
    Feature_IsARM | Feature_HasV6 | 0, // UMULL = 922
    Feature_IsARM | 0, // UQADD16 = 923
    Feature_IsARM | 0, // UQADD8 = 924
    Feature_IsARM | 0, // UQASX = 925
    Feature_IsARM | 0, // UQSAX = 926
    Feature_IsARM | 0, // UQSUB16 = 927
    Feature_IsARM | 0, // UQSUB8 = 928
    Feature_IsARM | Feature_HasV6 | 0, // USAD8 = 929
    Feature_IsARM | Feature_HasV6 | 0, // USADA8 = 930
    Feature_IsARM | Feature_HasV6 | 0, // USAT = 931
    Feature_IsARM | Feature_HasV6 | 0, // USAT16 = 932
    Feature_IsARM | 0, // USAX = 933
    Feature_IsARM | 0, // USUB16 = 934
    Feature_IsARM | 0, // USUB8 = 935
    Feature_IsARM | Feature_HasV6 | 0, // UXTAB = 936
    Feature_IsARM | Feature_HasV6 | 0, // UXTAB16 = 937
    Feature_IsARM | Feature_HasV6 | 0, // UXTAH = 938
    Feature_IsARM | Feature_HasV6 | 0, // UXTB = 939
    Feature_IsARM | Feature_HasV6 | 0, // UXTB16 = 940
    Feature_IsARM | Feature_HasV6 | 0, // UXTH = 941
    Feature_HasNEON | 0, // VABALsv2i64 = 942
    Feature_HasNEON | 0, // VABALsv4i32 = 943
    Feature_HasNEON | 0, // VABALsv8i16 = 944
    Feature_HasNEON | 0, // VABALuv2i64 = 945
    Feature_HasNEON | 0, // VABALuv4i32 = 946
    Feature_HasNEON | 0, // VABALuv8i16 = 947
    Feature_HasNEON | 0, // VABAsv16i8 = 948
    Feature_HasNEON | 0, // VABAsv2i32 = 949
    Feature_HasNEON | 0, // VABAsv4i16 = 950
    Feature_HasNEON | 0, // VABAsv4i32 = 951
    Feature_HasNEON | 0, // VABAsv8i16 = 952
    Feature_HasNEON | 0, // VABAsv8i8 = 953
    Feature_HasNEON | 0, // VABAuv16i8 = 954
    Feature_HasNEON | 0, // VABAuv2i32 = 955
    Feature_HasNEON | 0, // VABAuv4i16 = 956
    Feature_HasNEON | 0, // VABAuv4i32 = 957
    Feature_HasNEON | 0, // VABAuv8i16 = 958
    Feature_HasNEON | 0, // VABAuv8i8 = 959
    Feature_HasNEON | 0, // VABDLsv2i64 = 960
    Feature_HasNEON | 0, // VABDLsv4i32 = 961
    Feature_HasNEON | 0, // VABDLsv8i16 = 962
    Feature_HasNEON | 0, // VABDLuv2i64 = 963
    Feature_HasNEON | 0, // VABDLuv4i32 = 964
    Feature_HasNEON | 0, // VABDLuv8i16 = 965
    Feature_HasNEON | 0, // VABDfd = 966
    Feature_HasNEON | 0, // VABDfq = 967
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VABDhd = 968
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VABDhq = 969
    Feature_HasNEON | 0, // VABDsv16i8 = 970
    Feature_HasNEON | 0, // VABDsv2i32 = 971
    Feature_HasNEON | 0, // VABDsv4i16 = 972
    Feature_HasNEON | 0, // VABDsv4i32 = 973
    Feature_HasNEON | 0, // VABDsv8i16 = 974
    Feature_HasNEON | 0, // VABDsv8i8 = 975
    Feature_HasNEON | 0, // VABDuv16i8 = 976
    Feature_HasNEON | 0, // VABDuv2i32 = 977
    Feature_HasNEON | 0, // VABDuv4i16 = 978
    Feature_HasNEON | 0, // VABDuv4i32 = 979
    Feature_HasNEON | 0, // VABDuv8i16 = 980
    Feature_HasNEON | 0, // VABDuv8i8 = 981
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VABSD = 982
    Feature_HasFullFP16 | 0, // VABSH = 983
    Feature_HasVFP2 | 0, // VABSS = 984
    Feature_HasNEON | 0, // VABSfd = 985
    Feature_HasNEON | 0, // VABSfq = 986
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VABShd = 987
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VABShq = 988
    Feature_HasNEON | 0, // VABSv16i8 = 989
    Feature_HasNEON | 0, // VABSv2i32 = 990
    Feature_HasNEON | 0, // VABSv4i16 = 991
    Feature_HasNEON | 0, // VABSv4i32 = 992
    Feature_HasNEON | 0, // VABSv8i16 = 993
    Feature_HasNEON | 0, // VABSv8i8 = 994
    Feature_HasNEON | 0, // VACGEfd = 995
    Feature_HasNEON | 0, // VACGEfq = 996
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGEhd = 997
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGEhq = 998
    Feature_HasNEON | 0, // VACGTfd = 999
    Feature_HasNEON | 0, // VACGTfq = 1000
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGThd = 1001
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGThq = 1002
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VADDD = 1003
    Feature_HasFullFP16 | 0, // VADDH = 1004
    Feature_HasNEON | 0, // VADDHNv2i32 = 1005
    Feature_HasNEON | 0, // VADDHNv4i16 = 1006
    Feature_HasNEON | 0, // VADDHNv8i8 = 1007
    Feature_HasNEON | 0, // VADDLsv2i64 = 1008
    Feature_HasNEON | 0, // VADDLsv4i32 = 1009
    Feature_HasNEON | 0, // VADDLsv8i16 = 1010
    Feature_HasNEON | 0, // VADDLuv2i64 = 1011
    Feature_HasNEON | 0, // VADDLuv4i32 = 1012
    Feature_HasNEON | 0, // VADDLuv8i16 = 1013
    Feature_HasVFP2 | 0, // VADDS = 1014
    Feature_HasNEON | 0, // VADDWsv2i64 = 1015
    Feature_HasNEON | 0, // VADDWsv4i32 = 1016
    Feature_HasNEON | 0, // VADDWsv8i16 = 1017
    Feature_HasNEON | 0, // VADDWuv2i64 = 1018
    Feature_HasNEON | 0, // VADDWuv4i32 = 1019
    Feature_HasNEON | 0, // VADDWuv8i16 = 1020
    Feature_HasNEON | 0, // VADDfd = 1021
    Feature_HasNEON | 0, // VADDfq = 1022
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VADDhd = 1023
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VADDhq = 1024
    Feature_HasNEON | 0, // VADDv16i8 = 1025
    Feature_HasNEON | 0, // VADDv1i64 = 1026
    Feature_HasNEON | 0, // VADDv2i32 = 1027
    Feature_HasNEON | 0, // VADDv2i64 = 1028
    Feature_HasNEON | 0, // VADDv4i16 = 1029
    Feature_HasNEON | 0, // VADDv4i32 = 1030
    Feature_HasNEON | 0, // VADDv8i16 = 1031
    Feature_HasNEON | 0, // VADDv8i8 = 1032
    Feature_HasNEON | 0, // VANDd = 1033
    Feature_HasNEON | 0, // VANDq = 1034
    Feature_HasNEON | 0, // VBICd = 1035
    Feature_HasNEON | 0, // VBICiv2i32 = 1036
    Feature_HasNEON | 0, // VBICiv4i16 = 1037
    Feature_HasNEON | 0, // VBICiv4i32 = 1038
    Feature_HasNEON | 0, // VBICiv8i16 = 1039
    Feature_HasNEON | 0, // VBICq = 1040
    Feature_HasNEON | 0, // VBIFd = 1041
    Feature_HasNEON | 0, // VBIFq = 1042
    Feature_HasNEON | 0, // VBITd = 1043
    Feature_HasNEON | 0, // VBITq = 1044
    Feature_HasNEON | 0, // VBSLd = 1045
    Feature_HasNEON | 0, // VBSLq = 1046
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCADDv2f32 = 1047
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCADDv4f16 = 1048
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCADDv4f32 = 1049
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCADDv8f16 = 1050
    Feature_HasNEON | 0, // VCEQfd = 1051
    Feature_HasNEON | 0, // VCEQfq = 1052
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQhd = 1053
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQhq = 1054
    Feature_HasNEON | 0, // VCEQv16i8 = 1055
    Feature_HasNEON | 0, // VCEQv2i32 = 1056
    Feature_HasNEON | 0, // VCEQv4i16 = 1057
    Feature_HasNEON | 0, // VCEQv4i32 = 1058
    Feature_HasNEON | 0, // VCEQv8i16 = 1059
    Feature_HasNEON | 0, // VCEQv8i8 = 1060
    Feature_HasNEON | 0, // VCEQzv16i8 = 1061
    Feature_HasNEON | 0, // VCEQzv2f32 = 1062
    Feature_HasNEON | 0, // VCEQzv2i32 = 1063
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQzv4f16 = 1064
    Feature_HasNEON | 0, // VCEQzv4f32 = 1065
    Feature_HasNEON | 0, // VCEQzv4i16 = 1066
    Feature_HasNEON | 0, // VCEQzv4i32 = 1067
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQzv8f16 = 1068
    Feature_HasNEON | 0, // VCEQzv8i16 = 1069
    Feature_HasNEON | 0, // VCEQzv8i8 = 1070
    Feature_HasNEON | 0, // VCGEfd = 1071
    Feature_HasNEON | 0, // VCGEfq = 1072
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEhd = 1073
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEhq = 1074
    Feature_HasNEON | 0, // VCGEsv16i8 = 1075
    Feature_HasNEON | 0, // VCGEsv2i32 = 1076
    Feature_HasNEON | 0, // VCGEsv4i16 = 1077
    Feature_HasNEON | 0, // VCGEsv4i32 = 1078
    Feature_HasNEON | 0, // VCGEsv8i16 = 1079
    Feature_HasNEON | 0, // VCGEsv8i8 = 1080
    Feature_HasNEON | 0, // VCGEuv16i8 = 1081
    Feature_HasNEON | 0, // VCGEuv2i32 = 1082
    Feature_HasNEON | 0, // VCGEuv4i16 = 1083
    Feature_HasNEON | 0, // VCGEuv4i32 = 1084
    Feature_HasNEON | 0, // VCGEuv8i16 = 1085
    Feature_HasNEON | 0, // VCGEuv8i8 = 1086
    Feature_HasNEON | 0, // VCGEzv16i8 = 1087
    Feature_HasNEON | 0, // VCGEzv2f32 = 1088
    Feature_HasNEON | 0, // VCGEzv2i32 = 1089
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEzv4f16 = 1090
    Feature_HasNEON | 0, // VCGEzv4f32 = 1091
    Feature_HasNEON | 0, // VCGEzv4i16 = 1092
    Feature_HasNEON | 0, // VCGEzv4i32 = 1093
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEzv8f16 = 1094
    Feature_HasNEON | 0, // VCGEzv8i16 = 1095
    Feature_HasNEON | 0, // VCGEzv8i8 = 1096
    Feature_HasNEON | 0, // VCGTfd = 1097
    Feature_HasNEON | 0, // VCGTfq = 1098
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGThd = 1099
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGThq = 1100
    Feature_HasNEON | 0, // VCGTsv16i8 = 1101
    Feature_HasNEON | 0, // VCGTsv2i32 = 1102
    Feature_HasNEON | 0, // VCGTsv4i16 = 1103
    Feature_HasNEON | 0, // VCGTsv4i32 = 1104
    Feature_HasNEON | 0, // VCGTsv8i16 = 1105
    Feature_HasNEON | 0, // VCGTsv8i8 = 1106
    Feature_HasNEON | 0, // VCGTuv16i8 = 1107
    Feature_HasNEON | 0, // VCGTuv2i32 = 1108
    Feature_HasNEON | 0, // VCGTuv4i16 = 1109
    Feature_HasNEON | 0, // VCGTuv4i32 = 1110
    Feature_HasNEON | 0, // VCGTuv8i16 = 1111
    Feature_HasNEON | 0, // VCGTuv8i8 = 1112
    Feature_HasNEON | 0, // VCGTzv16i8 = 1113
    Feature_HasNEON | 0, // VCGTzv2f32 = 1114
    Feature_HasNEON | 0, // VCGTzv2i32 = 1115
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGTzv4f16 = 1116
    Feature_HasNEON | 0, // VCGTzv4f32 = 1117
    Feature_HasNEON | 0, // VCGTzv4i16 = 1118
    Feature_HasNEON | 0, // VCGTzv4i32 = 1119
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGTzv8f16 = 1120
    Feature_HasNEON | 0, // VCGTzv8i16 = 1121
    Feature_HasNEON | 0, // VCGTzv8i8 = 1122
    Feature_HasNEON | 0, // VCLEzv16i8 = 1123
    Feature_HasNEON | 0, // VCLEzv2f32 = 1124
    Feature_HasNEON | 0, // VCLEzv2i32 = 1125
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLEzv4f16 = 1126
    Feature_HasNEON | 0, // VCLEzv4f32 = 1127
    Feature_HasNEON | 0, // VCLEzv4i16 = 1128
    Feature_HasNEON | 0, // VCLEzv4i32 = 1129
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLEzv8f16 = 1130
    Feature_HasNEON | 0, // VCLEzv8i16 = 1131
    Feature_HasNEON | 0, // VCLEzv8i8 = 1132
    Feature_HasNEON | 0, // VCLSv16i8 = 1133
    Feature_HasNEON | 0, // VCLSv2i32 = 1134
    Feature_HasNEON | 0, // VCLSv4i16 = 1135
    Feature_HasNEON | 0, // VCLSv4i32 = 1136
    Feature_HasNEON | 0, // VCLSv8i16 = 1137
    Feature_HasNEON | 0, // VCLSv8i8 = 1138
    Feature_HasNEON | 0, // VCLTzv16i8 = 1139
    Feature_HasNEON | 0, // VCLTzv2f32 = 1140
    Feature_HasNEON | 0, // VCLTzv2i32 = 1141
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLTzv4f16 = 1142
    Feature_HasNEON | 0, // VCLTzv4f32 = 1143
    Feature_HasNEON | 0, // VCLTzv4i16 = 1144
    Feature_HasNEON | 0, // VCLTzv4i32 = 1145
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLTzv8f16 = 1146
    Feature_HasNEON | 0, // VCLTzv8i16 = 1147
    Feature_HasNEON | 0, // VCLTzv8i8 = 1148
    Feature_HasNEON | 0, // VCLZv16i8 = 1149
    Feature_HasNEON | 0, // VCLZv2i32 = 1150
    Feature_HasNEON | 0, // VCLZv4i16 = 1151
    Feature_HasNEON | 0, // VCLZv4i32 = 1152
    Feature_HasNEON | 0, // VCLZv8i16 = 1153
    Feature_HasNEON | 0, // VCLZv8i8 = 1154
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv2f32 = 1155
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv2f32_indexed = 1156
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv4f16 = 1157
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv4f16_indexed = 1158
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv4f32 = 1159
    Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv4f32_indexed = 1160
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv8f16 = 1161
    Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv8f16_indexed = 1162
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPD = 1163
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPED = 1164
    Feature_HasFullFP16 | 0, // VCMPEH = 1165
    Feature_HasVFP2 | 0, // VCMPES = 1166
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPEZD = 1167
    Feature_HasFullFP16 | 0, // VCMPEZH = 1168
    Feature_HasVFP2 | 0, // VCMPEZS = 1169
    Feature_HasFullFP16 | 0, // VCMPH = 1170
    Feature_HasVFP2 | 0, // VCMPS = 1171
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPZD = 1172
    Feature_HasFullFP16 | 0, // VCMPZH = 1173
    Feature_HasVFP2 | 0, // VCMPZS = 1174
    Feature_HasNEON | 0, // VCNTd = 1175
    Feature_HasNEON | 0, // VCNTq = 1176
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTANSDf = 1177
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANSDh = 1178
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTANSQf = 1179
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANSQh = 1180
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTANUDf = 1181
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANUDh = 1182
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTANUQf = 1183
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANUQh = 1184
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTASD = 1185
    Feature_HasFullFP16 | 0, // VCVTASH = 1186
    Feature_HasFPARMv8 | 0, // VCVTASS = 1187
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTAUD = 1188
    Feature_HasFullFP16 | 0, // VCVTAUH = 1189
    Feature_HasFPARMv8 | 0, // VCVTAUS = 1190
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTBDH = 1191
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTBHD = 1192
    Feature_HasFP16 | 0, // VCVTBHS = 1193
    Feature_HasFP16 | 0, // VCVTBSH = 1194
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCVTDS = 1195
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNSDf = 1196
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNSDh = 1197
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNSQf = 1198
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNSQh = 1199
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNUDf = 1200
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNUDh = 1201
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNUQf = 1202
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNUQh = 1203
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTMSD = 1204
    Feature_HasFullFP16 | 0, // VCVTMSH = 1205
    Feature_HasFPARMv8 | 0, // VCVTMSS = 1206
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTMUD = 1207
    Feature_HasFullFP16 | 0, // VCVTMUH = 1208
    Feature_HasFPARMv8 | 0, // VCVTMUS = 1209
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNSDf = 1210
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNSDh = 1211
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNSQf = 1212
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNSQh = 1213
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNUDf = 1214
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNUDh = 1215
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNUQf = 1216
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNUQh = 1217
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTNSD = 1218
    Feature_HasFullFP16 | 0, // VCVTNSH = 1219
    Feature_HasFPARMv8 | 0, // VCVTNSS = 1220
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTNUD = 1221
    Feature_HasFullFP16 | 0, // VCVTNUH = 1222
    Feature_HasFPARMv8 | 0, // VCVTNUS = 1223
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNSDf = 1224
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNSDh = 1225
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNSQf = 1226
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNSQh = 1227
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNUDf = 1228
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNUDh = 1229
    Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNUQf = 1230
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNUQh = 1231
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTPSD = 1232
    Feature_HasFullFP16 | 0, // VCVTPSH = 1233
    Feature_HasFPARMv8 | 0, // VCVTPSS = 1234
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTPUD = 1235
    Feature_HasFullFP16 | 0, // VCVTPUH = 1236
    Feature_HasFPARMv8 | 0, // VCVTPUS = 1237
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCVTSD = 1238
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTTDH = 1239
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTTHD = 1240
    Feature_HasFP16 | 0, // VCVTTHS = 1241
    Feature_HasFP16 | 0, // VCVTTSH = 1242
    Feature_HasNEON | Feature_HasFP16 | 0, // VCVTf2h = 1243
    Feature_HasNEON | 0, // VCVTf2sd = 1244
    Feature_HasNEON | 0, // VCVTf2sq = 1245
    Feature_HasNEON | 0, // VCVTf2ud = 1246
    Feature_HasNEON | 0, // VCVTf2uq = 1247
    Feature_HasNEON | 0, // VCVTf2xsd = 1248
    Feature_HasNEON | 0, // VCVTf2xsq = 1249
    Feature_HasNEON | 0, // VCVTf2xud = 1250
    Feature_HasNEON | 0, // VCVTf2xuq = 1251
    Feature_HasNEON | Feature_HasFP16 | 0, // VCVTh2f = 1252
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2sd = 1253
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2sq = 1254
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2ud = 1255
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2uq = 1256
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xsd = 1257
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xsq = 1258
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xud = 1259
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xuq = 1260
    Feature_HasNEON | 0, // VCVTs2fd = 1261
    Feature_HasNEON | 0, // VCVTs2fq = 1262
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTs2hd = 1263
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTs2hq = 1264
    Feature_HasNEON | 0, // VCVTu2fd = 1265
    Feature_HasNEON | 0, // VCVTu2fq = 1266
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTu2hd = 1267
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTu2hq = 1268
    Feature_HasNEON | 0, // VCVTxs2fd = 1269
    Feature_HasNEON | 0, // VCVTxs2fq = 1270
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxs2hd = 1271
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxs2hq = 1272
    Feature_HasNEON | 0, // VCVTxu2fd = 1273
    Feature_HasNEON | 0, // VCVTxu2fq = 1274
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxu2hd = 1275
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxu2hq = 1276
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VDIVD = 1277
    Feature_HasFullFP16 | 0, // VDIVH = 1278
    Feature_HasVFP2 | 0, // VDIVS = 1279
    Feature_HasNEON | 0, // VDUP16d = 1280
    Feature_HasNEON | 0, // VDUP16q = 1281
    Feature_HasNEON | 0, // VDUP32d = 1282
    Feature_HasNEON | 0, // VDUP32q = 1283
    Feature_HasNEON | 0, // VDUP8d = 1284
    Feature_HasNEON | 0, // VDUP8q = 1285
    Feature_HasNEON | 0, // VDUPLN16d = 1286
    Feature_HasNEON | 0, // VDUPLN16q = 1287
    Feature_HasNEON | 0, // VDUPLN32d = 1288
    Feature_HasNEON | 0, // VDUPLN32q = 1289
    Feature_HasNEON | 0, // VDUPLN8d = 1290
    Feature_HasNEON | 0, // VDUPLN8q = 1291
    Feature_HasNEON | 0, // VEORd = 1292
    Feature_HasNEON | 0, // VEORq = 1293
    Feature_HasNEON | 0, // VEXTd16 = 1294
    Feature_HasNEON | 0, // VEXTd32 = 1295
    Feature_HasNEON | 0, // VEXTd8 = 1296
    Feature_HasNEON | 0, // VEXTq16 = 1297
    Feature_HasNEON | 0, // VEXTq32 = 1298
    Feature_HasNEON | 0, // VEXTq64 = 1299
    Feature_HasNEON | 0, // VEXTq8 = 1300
    Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFMAD = 1301
    Feature_HasFullFP16 | 0, // VFMAH = 1302
    Feature_HasVFP4 | 0, // VFMAS = 1303
    Feature_HasNEON | Feature_HasVFP4 | 0, // VFMAfd = 1304
    Feature_HasNEON | Feature_HasVFP4 | 0, // VFMAfq = 1305
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMAhd = 1306
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMAhq = 1307
    Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFMSD = 1308
    Feature_HasFullFP16 | 0, // VFMSH = 1309
    Feature_HasVFP4 | 0, // VFMSS = 1310
    Feature_HasNEON | Feature_HasVFP4 | 0, // VFMSfd = 1311
    Feature_HasNEON | Feature_HasVFP4 | 0, // VFMSfq = 1312
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMShd = 1313
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMShq = 1314
    Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFNMAD = 1315
    Feature_HasFullFP16 | 0, // VFNMAH = 1316
    Feature_HasVFP4 | 0, // VFNMAS = 1317
    Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFNMSD = 1318
    Feature_HasFullFP16 | 0, // VFNMSH = 1319
    Feature_HasVFP4 | 0, // VFNMSS = 1320
    Feature_HasVFP2 | 0, // VGETLNi32 = 1321
    Feature_HasNEON | 0, // VGETLNs16 = 1322
    Feature_HasNEON | 0, // VGETLNs8 = 1323
    Feature_HasNEON | 0, // VGETLNu16 = 1324
    Feature_HasNEON | 0, // VGETLNu8 = 1325
    Feature_HasNEON | 0, // VHADDsv16i8 = 1326
    Feature_HasNEON | 0, // VHADDsv2i32 = 1327
    Feature_HasNEON | 0, // VHADDsv4i16 = 1328
    Feature_HasNEON | 0, // VHADDsv4i32 = 1329
    Feature_HasNEON | 0, // VHADDsv8i16 = 1330
    Feature_HasNEON | 0, // VHADDsv8i8 = 1331
    Feature_HasNEON | 0, // VHADDuv16i8 = 1332
    Feature_HasNEON | 0, // VHADDuv2i32 = 1333
    Feature_HasNEON | 0, // VHADDuv4i16 = 1334
    Feature_HasNEON | 0, // VHADDuv4i32 = 1335
    Feature_HasNEON | 0, // VHADDuv8i16 = 1336
    Feature_HasNEON | 0, // VHADDuv8i8 = 1337
    Feature_HasNEON | 0, // VHSUBsv16i8 = 1338
    Feature_HasNEON | 0, // VHSUBsv2i32 = 1339
    Feature_HasNEON | 0, // VHSUBsv4i16 = 1340
    Feature_HasNEON | 0, // VHSUBsv4i32 = 1341
    Feature_HasNEON | 0, // VHSUBsv8i16 = 1342
    Feature_HasNEON | 0, // VHSUBsv8i8 = 1343
    Feature_HasNEON | 0, // VHSUBuv16i8 = 1344
    Feature_HasNEON | 0, // VHSUBuv2i32 = 1345
    Feature_HasNEON | 0, // VHSUBuv4i16 = 1346
    Feature_HasNEON | 0, // VHSUBuv4i32 = 1347
    Feature_HasNEON | 0, // VHSUBuv8i16 = 1348
    Feature_HasNEON | 0, // VHSUBuv8i8 = 1349
    Feature_HasFullFP16 | 0, // VINSH = 1350
    Feature_HasFPARMv8 | Feature_HasV8_3a | 0, // VJCVT = 1351
    Feature_HasNEON | 0, // VLD1DUPd16 = 1352
    Feature_HasNEON | 0, // VLD1DUPd16wb_fixed = 1353
    Feature_HasNEON | 0, // VLD1DUPd16wb_register = 1354
    Feature_HasNEON | 0, // VLD1DUPd32 = 1355
    Feature_HasNEON | 0, // VLD1DUPd32wb_fixed = 1356
    Feature_HasNEON | 0, // VLD1DUPd32wb_register = 1357
    Feature_HasNEON | 0, // VLD1DUPd8 = 1358
    Feature_HasNEON | 0, // VLD1DUPd8wb_fixed = 1359
    Feature_HasNEON | 0, // VLD1DUPd8wb_register = 1360
    Feature_HasNEON | 0, // VLD1DUPq16 = 1361
    Feature_HasNEON | 0, // VLD1DUPq16wb_fixed = 1362
    Feature_HasNEON | 0, // VLD1DUPq16wb_register = 1363
    Feature_HasNEON | 0, // VLD1DUPq32 = 1364
    Feature_HasNEON | 0, // VLD1DUPq32wb_fixed = 1365
    Feature_HasNEON | 0, // VLD1DUPq32wb_register = 1366
    Feature_HasNEON | 0, // VLD1DUPq8 = 1367
    Feature_HasNEON | 0, // VLD1DUPq8wb_fixed = 1368
    Feature_HasNEON | 0, // VLD1DUPq8wb_register = 1369
    Feature_HasNEON | 0, // VLD1LNd16 = 1370
    Feature_HasNEON | 0, // VLD1LNd16_UPD = 1371
    Feature_HasNEON | 0, // VLD1LNd32 = 1372
    Feature_HasNEON | 0, // VLD1LNd32_UPD = 1373
    Feature_HasNEON | 0, // VLD1LNd8 = 1374
    Feature_HasNEON | 0, // VLD1LNd8_UPD = 1375
    Feature_HasNEON | 0, // VLD1LNq16Pseudo = 1376
    Feature_HasNEON | 0, // VLD1LNq16Pseudo_UPD = 1377
    Feature_HasNEON | 0, // VLD1LNq32Pseudo = 1378
    Feature_HasNEON | 0, // VLD1LNq32Pseudo_UPD = 1379
    Feature_HasNEON | 0, // VLD1LNq8Pseudo = 1380
    Feature_HasNEON | 0, // VLD1LNq8Pseudo_UPD = 1381
    Feature_HasNEON | 0, // VLD1d16 = 1382
    Feature_HasNEON | 0, // VLD1d16Q = 1383
    Feature_HasNEON | 0, // VLD1d16QPseudo = 1384
    Feature_HasNEON | 0, // VLD1d16Qwb_fixed = 1385
    Feature_HasNEON | 0, // VLD1d16Qwb_register = 1386
    Feature_HasNEON | 0, // VLD1d16T = 1387
    Feature_HasNEON | 0, // VLD1d16TPseudo = 1388
    Feature_HasNEON | 0, // VLD1d16Twb_fixed = 1389
    Feature_HasNEON | 0, // VLD1d16Twb_register = 1390
    Feature_HasNEON | 0, // VLD1d16wb_fixed = 1391
    Feature_HasNEON | 0, // VLD1d16wb_register = 1392
    Feature_HasNEON | 0, // VLD1d32 = 1393
    Feature_HasNEON | 0, // VLD1d32Q = 1394
    Feature_HasNEON | 0, // VLD1d32QPseudo = 1395
    Feature_HasNEON | 0, // VLD1d32Qwb_fixed = 1396
    Feature_HasNEON | 0, // VLD1d32Qwb_register = 1397
    Feature_HasNEON | 0, // VLD1d32T = 1398
    Feature_HasNEON | 0, // VLD1d32TPseudo = 1399
    Feature_HasNEON | 0, // VLD1d32Twb_fixed = 1400
    Feature_HasNEON | 0, // VLD1d32Twb_register = 1401
    Feature_HasNEON | 0, // VLD1d32wb_fixed = 1402
    Feature_HasNEON | 0, // VLD1d32wb_register = 1403
    Feature_HasNEON | 0, // VLD1d64 = 1404
    Feature_HasNEON | 0, // VLD1d64Q = 1405
    Feature_HasNEON | 0, // VLD1d64QPseudo = 1406
    Feature_HasNEON | 0, // VLD1d64QPseudoWB_fixed = 1407
    Feature_HasNEON | 0, // VLD1d64QPseudoWB_register = 1408
    Feature_HasNEON | 0, // VLD1d64Qwb_fixed = 1409
    Feature_HasNEON | 0, // VLD1d64Qwb_register = 1410
    Feature_HasNEON | 0, // VLD1d64T = 1411
    Feature_HasNEON | 0, // VLD1d64TPseudo = 1412
    Feature_HasNEON | 0, // VLD1d64TPseudoWB_fixed = 1413
    Feature_HasNEON | 0, // VLD1d64TPseudoWB_register = 1414
    Feature_HasNEON | 0, // VLD1d64Twb_fixed = 1415
    Feature_HasNEON | 0, // VLD1d64Twb_register = 1416
    Feature_HasNEON | 0, // VLD1d64wb_fixed = 1417
    Feature_HasNEON | 0, // VLD1d64wb_register = 1418
    Feature_HasNEON | 0, // VLD1d8 = 1419
    Feature_HasNEON | 0, // VLD1d8Q = 1420
    Feature_HasNEON | 0, // VLD1d8QPseudo = 1421
    Feature_HasNEON | 0, // VLD1d8Qwb_fixed = 1422
    Feature_HasNEON | 0, // VLD1d8Qwb_register = 1423
    Feature_HasNEON | 0, // VLD1d8T = 1424
    Feature_HasNEON | 0, // VLD1d8TPseudo = 1425
    Feature_HasNEON | 0, // VLD1d8Twb_fixed = 1426
    Feature_HasNEON | 0, // VLD1d8Twb_register = 1427
    Feature_HasNEON | 0, // VLD1d8wb_fixed = 1428
    Feature_HasNEON | 0, // VLD1d8wb_register = 1429
    Feature_HasNEON | 0, // VLD1q16 = 1430
    Feature_HasNEON | 0, // VLD1q16HighQPseudo = 1431
    Feature_HasNEON | 0, // VLD1q16HighTPseudo = 1432
    Feature_HasNEON | 0, // VLD1q16LowQPseudo_UPD = 1433
    Feature_HasNEON | 0, // VLD1q16LowTPseudo_UPD = 1434
    Feature_HasNEON | 0, // VLD1q16wb_fixed = 1435
    Feature_HasNEON | 0, // VLD1q16wb_register = 1436
    Feature_HasNEON | 0, // VLD1q32 = 1437
    Feature_HasNEON | 0, // VLD1q32HighQPseudo = 1438
    Feature_HasNEON | 0, // VLD1q32HighTPseudo = 1439
    Feature_HasNEON | 0, // VLD1q32LowQPseudo_UPD = 1440
    Feature_HasNEON | 0, // VLD1q32LowTPseudo_UPD = 1441
    Feature_HasNEON | 0, // VLD1q32wb_fixed = 1442
    Feature_HasNEON | 0, // VLD1q32wb_register = 1443
    Feature_HasNEON | 0, // VLD1q64 = 1444
    Feature_HasNEON | 0, // VLD1q64HighQPseudo = 1445
    Feature_HasNEON | 0, // VLD1q64HighTPseudo = 1446
    Feature_HasNEON | 0, // VLD1q64LowQPseudo_UPD = 1447
    Feature_HasNEON | 0, // VLD1q64LowTPseudo_UPD = 1448
    Feature_HasNEON | 0, // VLD1q64wb_fixed = 1449
    Feature_HasNEON | 0, // VLD1q64wb_register = 1450
    Feature_HasNEON | 0, // VLD1q8 = 1451
    Feature_HasNEON | 0, // VLD1q8HighQPseudo = 1452
    Feature_HasNEON | 0, // VLD1q8HighTPseudo = 1453
    Feature_HasNEON | 0, // VLD1q8LowQPseudo_UPD = 1454
    Feature_HasNEON | 0, // VLD1q8LowTPseudo_UPD = 1455
    Feature_HasNEON | 0, // VLD1q8wb_fixed = 1456
    Feature_HasNEON | 0, // VLD1q8wb_register = 1457
    Feature_HasNEON | 0, // VLD2DUPd16 = 1458
    Feature_HasNEON | 0, // VLD2DUPd16wb_fixed = 1459
    Feature_HasNEON | 0, // VLD2DUPd16wb_register = 1460
    Feature_HasNEON | 0, // VLD2DUPd16x2 = 1461
    Feature_HasNEON | 0, // VLD2DUPd16x2wb_fixed = 1462
    Feature_HasNEON | 0, // VLD2DUPd16x2wb_register = 1463
    Feature_HasNEON | 0, // VLD2DUPd32 = 1464
    Feature_HasNEON | 0, // VLD2DUPd32wb_fixed = 1465
    Feature_HasNEON | 0, // VLD2DUPd32wb_register = 1466
    Feature_HasNEON | 0, // VLD2DUPd32x2 = 1467
    Feature_HasNEON | 0, // VLD2DUPd32x2wb_fixed = 1468
    Feature_HasNEON | 0, // VLD2DUPd32x2wb_register = 1469
    Feature_HasNEON | 0, // VLD2DUPd8 = 1470
    Feature_HasNEON | 0, // VLD2DUPd8wb_fixed = 1471
    Feature_HasNEON | 0, // VLD2DUPd8wb_register = 1472
    Feature_HasNEON | 0, // VLD2DUPd8x2 = 1473
    Feature_HasNEON | 0, // VLD2DUPd8x2wb_fixed = 1474
    Feature_HasNEON | 0, // VLD2DUPd8x2wb_register = 1475
    Feature_HasNEON | 0, // VLD2DUPq16EvenPseudo = 1476
    Feature_HasNEON | 0, // VLD2DUPq16OddPseudo = 1477
    Feature_HasNEON | 0, // VLD2DUPq32EvenPseudo = 1478
    Feature_HasNEON | 0, // VLD2DUPq32OddPseudo = 1479
    Feature_HasNEON | 0, // VLD2DUPq8EvenPseudo = 1480
    Feature_HasNEON | 0, // VLD2DUPq8OddPseudo = 1481
    Feature_HasNEON | 0, // VLD2LNd16 = 1482
    Feature_HasNEON | 0, // VLD2LNd16Pseudo = 1483
    Feature_HasNEON | 0, // VLD2LNd16Pseudo_UPD = 1484
    Feature_HasNEON | 0, // VLD2LNd16_UPD = 1485
    Feature_HasNEON | 0, // VLD2LNd32 = 1486
    Feature_HasNEON | 0, // VLD2LNd32Pseudo = 1487
    Feature_HasNEON | 0, // VLD2LNd32Pseudo_UPD = 1488
    Feature_HasNEON | 0, // VLD2LNd32_UPD = 1489
    Feature_HasNEON | 0, // VLD2LNd8 = 1490
    Feature_HasNEON | 0, // VLD2LNd8Pseudo = 1491
    Feature_HasNEON | 0, // VLD2LNd8Pseudo_UPD = 1492
    Feature_HasNEON | 0, // VLD2LNd8_UPD = 1493
    Feature_HasNEON | 0, // VLD2LNq16 = 1494
    Feature_HasNEON | 0, // VLD2LNq16Pseudo = 1495
    Feature_HasNEON | 0, // VLD2LNq16Pseudo_UPD = 1496
    Feature_HasNEON | 0, // VLD2LNq16_UPD = 1497
    Feature_HasNEON | 0, // VLD2LNq32 = 1498
    Feature_HasNEON | 0, // VLD2LNq32Pseudo = 1499
    Feature_HasNEON | 0, // VLD2LNq32Pseudo_UPD = 1500
    Feature_HasNEON | 0, // VLD2LNq32_UPD = 1501
    Feature_HasNEON | 0, // VLD2b16 = 1502
    Feature_HasNEON | 0, // VLD2b16wb_fixed = 1503
    Feature_HasNEON | 0, // VLD2b16wb_register = 1504
    Feature_HasNEON | 0, // VLD2b32 = 1505
    Feature_HasNEON | 0, // VLD2b32wb_fixed = 1506
    Feature_HasNEON | 0, // VLD2b32wb_register = 1507
    Feature_HasNEON | 0, // VLD2b8 = 1508
    Feature_HasNEON | 0, // VLD2b8wb_fixed = 1509
    Feature_HasNEON | 0, // VLD2b8wb_register = 1510
    Feature_HasNEON | 0, // VLD2d16 = 1511
    Feature_HasNEON | 0, // VLD2d16wb_fixed = 1512
    Feature_HasNEON | 0, // VLD2d16wb_register = 1513
    Feature_HasNEON | 0, // VLD2d32 = 1514
    Feature_HasNEON | 0, // VLD2d32wb_fixed = 1515
    Feature_HasNEON | 0, // VLD2d32wb_register = 1516
    Feature_HasNEON | 0, // VLD2d8 = 1517
    Feature_HasNEON | 0, // VLD2d8wb_fixed = 1518
    Feature_HasNEON | 0, // VLD2d8wb_register = 1519
    Feature_HasNEON | 0, // VLD2q16 = 1520
    Feature_HasNEON | 0, // VLD2q16Pseudo = 1521
    Feature_HasNEON | 0, // VLD2q16PseudoWB_fixed = 1522
    Feature_HasNEON | 0, // VLD2q16PseudoWB_register = 1523
    Feature_HasNEON | 0, // VLD2q16wb_fixed = 1524
    Feature_HasNEON | 0, // VLD2q16wb_register = 1525
    Feature_HasNEON | 0, // VLD2q32 = 1526
    Feature_HasNEON | 0, // VLD2q32Pseudo = 1527
    Feature_HasNEON | 0, // VLD2q32PseudoWB_fixed = 1528
    Feature_HasNEON | 0, // VLD2q32PseudoWB_register = 1529
    Feature_HasNEON | 0, // VLD2q32wb_fixed = 1530
    Feature_HasNEON | 0, // VLD2q32wb_register = 1531
    Feature_HasNEON | 0, // VLD2q8 = 1532
    Feature_HasNEON | 0, // VLD2q8Pseudo = 1533
    Feature_HasNEON | 0, // VLD2q8PseudoWB_fixed = 1534
    Feature_HasNEON | 0, // VLD2q8PseudoWB_register = 1535
    Feature_HasNEON | 0, // VLD2q8wb_fixed = 1536
    Feature_HasNEON | 0, // VLD2q8wb_register = 1537
    Feature_HasNEON | 0, // VLD3DUPd16 = 1538
    Feature_HasNEON | 0, // VLD3DUPd16Pseudo = 1539
    Feature_HasNEON | 0, // VLD3DUPd16Pseudo_UPD = 1540
    Feature_HasNEON | 0, // VLD3DUPd16_UPD = 1541
    Feature_HasNEON | 0, // VLD3DUPd32 = 1542
    Feature_HasNEON | 0, // VLD3DUPd32Pseudo = 1543
    Feature_HasNEON | 0, // VLD3DUPd32Pseudo_UPD = 1544
    Feature_HasNEON | 0, // VLD3DUPd32_UPD = 1545
    Feature_HasNEON | 0, // VLD3DUPd8 = 1546
    Feature_HasNEON | 0, // VLD3DUPd8Pseudo = 1547
    Feature_HasNEON | 0, // VLD3DUPd8Pseudo_UPD = 1548
    Feature_HasNEON | 0, // VLD3DUPd8_UPD = 1549
    Feature_HasNEON | 0, // VLD3DUPq16 = 1550
    Feature_HasNEON | 0, // VLD3DUPq16EvenPseudo = 1551
    Feature_HasNEON | 0, // VLD3DUPq16OddPseudo = 1552
    Feature_HasNEON | 0, // VLD3DUPq16_UPD = 1553
    Feature_HasNEON | 0, // VLD3DUPq32 = 1554
    Feature_HasNEON | 0, // VLD3DUPq32EvenPseudo = 1555
    Feature_HasNEON | 0, // VLD3DUPq32OddPseudo = 1556
    Feature_HasNEON | 0, // VLD3DUPq32_UPD = 1557
    Feature_HasNEON | 0, // VLD3DUPq8 = 1558
    Feature_HasNEON | 0, // VLD3DUPq8EvenPseudo = 1559
    Feature_HasNEON | 0, // VLD3DUPq8OddPseudo = 1560
    Feature_HasNEON | 0, // VLD3DUPq8_UPD = 1561
    Feature_HasNEON | 0, // VLD3LNd16 = 1562
    Feature_HasNEON | 0, // VLD3LNd16Pseudo = 1563
    Feature_HasNEON | 0, // VLD3LNd16Pseudo_UPD = 1564
    Feature_HasNEON | 0, // VLD3LNd16_UPD = 1565
    Feature_HasNEON | 0, // VLD3LNd32 = 1566
    Feature_HasNEON | 0, // VLD3LNd32Pseudo = 1567
    Feature_HasNEON | 0, // VLD3LNd32Pseudo_UPD = 1568
    Feature_HasNEON | 0, // VLD3LNd32_UPD = 1569
    Feature_HasNEON | 0, // VLD3LNd8 = 1570
    Feature_HasNEON | 0, // VLD3LNd8Pseudo = 1571
    Feature_HasNEON | 0, // VLD3LNd8Pseudo_UPD = 1572
    Feature_HasNEON | 0, // VLD3LNd8_UPD = 1573
    Feature_HasNEON | 0, // VLD3LNq16 = 1574
    Feature_HasNEON | 0, // VLD3LNq16Pseudo = 1575
    Feature_HasNEON | 0, // VLD3LNq16Pseudo_UPD = 1576
    Feature_HasNEON | 0, // VLD3LNq16_UPD = 1577
    Feature_HasNEON | 0, // VLD3LNq32 = 1578
    Feature_HasNEON | 0, // VLD3LNq32Pseudo = 1579
    Feature_HasNEON | 0, // VLD3LNq32Pseudo_UPD = 1580
    Feature_HasNEON | 0, // VLD3LNq32_UPD = 1581
    Feature_HasNEON | 0, // VLD3d16 = 1582
    Feature_HasNEON | 0, // VLD3d16Pseudo = 1583
    Feature_HasNEON | 0, // VLD3d16Pseudo_UPD = 1584
    Feature_HasNEON | 0, // VLD3d16_UPD = 1585
    Feature_HasNEON | 0, // VLD3d32 = 1586
    Feature_HasNEON | 0, // VLD3d32Pseudo = 1587
    Feature_HasNEON | 0, // VLD3d32Pseudo_UPD = 1588
    Feature_HasNEON | 0, // VLD3d32_UPD = 1589
    Feature_HasNEON | 0, // VLD3d8 = 1590
    Feature_HasNEON | 0, // VLD3d8Pseudo = 1591
    Feature_HasNEON | 0, // VLD3d8Pseudo_UPD = 1592
    Feature_HasNEON | 0, // VLD3d8_UPD = 1593
    Feature_HasNEON | 0, // VLD3q16 = 1594
    Feature_HasNEON | 0, // VLD3q16Pseudo_UPD = 1595
    Feature_HasNEON | 0, // VLD3q16_UPD = 1596
    Feature_HasNEON | 0, // VLD3q16oddPseudo = 1597
    Feature_HasNEON | 0, // VLD3q16oddPseudo_UPD = 1598
    Feature_HasNEON | 0, // VLD3q32 = 1599
    Feature_HasNEON | 0, // VLD3q32Pseudo_UPD = 1600
    Feature_HasNEON | 0, // VLD3q32_UPD = 1601
    Feature_HasNEON | 0, // VLD3q32oddPseudo = 1602
    Feature_HasNEON | 0, // VLD3q32oddPseudo_UPD = 1603
    Feature_HasNEON | 0, // VLD3q8 = 1604
    Feature_HasNEON | 0, // VLD3q8Pseudo_UPD = 1605
    Feature_HasNEON | 0, // VLD3q8_UPD = 1606
    Feature_HasNEON | 0, // VLD3q8oddPseudo = 1607
    Feature_HasNEON | 0, // VLD3q8oddPseudo_UPD = 1608
    Feature_HasNEON | 0, // VLD4DUPd16 = 1609
    Feature_HasNEON | 0, // VLD4DUPd16Pseudo = 1610
    Feature_HasNEON | 0, // VLD4DUPd16Pseudo_UPD = 1611
    Feature_HasNEON | 0, // VLD4DUPd16_UPD = 1612
    Feature_HasNEON | 0, // VLD4DUPd32 = 1613
    Feature_HasNEON | 0, // VLD4DUPd32Pseudo = 1614
    Feature_HasNEON | 0, // VLD4DUPd32Pseudo_UPD = 1615
    Feature_HasNEON | 0, // VLD4DUPd32_UPD = 1616
    Feature_HasNEON | 0, // VLD4DUPd8 = 1617
    Feature_HasNEON | 0, // VLD4DUPd8Pseudo = 1618
    Feature_HasNEON | 0, // VLD4DUPd8Pseudo_UPD = 1619
    Feature_HasNEON | 0, // VLD4DUPd8_UPD = 1620
    Feature_HasNEON | 0, // VLD4DUPq16 = 1621
    Feature_HasNEON | 0, // VLD4DUPq16EvenPseudo = 1622
    Feature_HasNEON | 0, // VLD4DUPq16OddPseudo = 1623
    Feature_HasNEON | 0, // VLD4DUPq16_UPD = 1624
    Feature_HasNEON | 0, // VLD4DUPq32 = 1625
    Feature_HasNEON | 0, // VLD4DUPq32EvenPseudo = 1626
    Feature_HasNEON | 0, // VLD4DUPq32OddPseudo = 1627
    Feature_HasNEON | 0, // VLD4DUPq32_UPD = 1628
    Feature_HasNEON | 0, // VLD4DUPq8 = 1629
    Feature_HasNEON | 0, // VLD4DUPq8EvenPseudo = 1630
    Feature_HasNEON | 0, // VLD4DUPq8OddPseudo = 1631
    Feature_HasNEON | 0, // VLD4DUPq8_UPD = 1632
    Feature_HasNEON | 0, // VLD4LNd16 = 1633
    Feature_HasNEON | 0, // VLD4LNd16Pseudo = 1634
    Feature_HasNEON | 0, // VLD4LNd16Pseudo_UPD = 1635
    Feature_HasNEON | 0, // VLD4LNd16_UPD = 1636
    Feature_HasNEON | 0, // VLD4LNd32 = 1637
    Feature_HasNEON | 0, // VLD4LNd32Pseudo = 1638
    Feature_HasNEON | 0, // VLD4LNd32Pseudo_UPD = 1639
    Feature_HasNEON | 0, // VLD4LNd32_UPD = 1640
    Feature_HasNEON | 0, // VLD4LNd8 = 1641
    Feature_HasNEON | 0, // VLD4LNd8Pseudo = 1642
    Feature_HasNEON | 0, // VLD4LNd8Pseudo_UPD = 1643
    Feature_HasNEON | 0, // VLD4LNd8_UPD = 1644
    Feature_HasNEON | 0, // VLD4LNq16 = 1645
    Feature_HasNEON | 0, // VLD4LNq16Pseudo = 1646
    Feature_HasNEON | 0, // VLD4LNq16Pseudo_UPD = 1647
    Feature_HasNEON | 0, // VLD4LNq16_UPD = 1648
    Feature_HasNEON | 0, // VLD4LNq32 = 1649
    Feature_HasNEON | 0, // VLD4LNq32Pseudo = 1650
    Feature_HasNEON | 0, // VLD4LNq32Pseudo_UPD = 1651
    Feature_HasNEON | 0, // VLD4LNq32_UPD = 1652
    Feature_HasNEON | 0, // VLD4d16 = 1653
    Feature_HasNEON | 0, // VLD4d16Pseudo = 1654
    Feature_HasNEON | 0, // VLD4d16Pseudo_UPD = 1655
    Feature_HasNEON | 0, // VLD4d16_UPD = 1656
    Feature_HasNEON | 0, // VLD4d32 = 1657
    Feature_HasNEON | 0, // VLD4d32Pseudo = 1658
    Feature_HasNEON | 0, // VLD4d32Pseudo_UPD = 1659
    Feature_HasNEON | 0, // VLD4d32_UPD = 1660
    Feature_HasNEON | 0, // VLD4d8 = 1661
    Feature_HasNEON | 0, // VLD4d8Pseudo = 1662
    Feature_HasNEON | 0, // VLD4d8Pseudo_UPD = 1663
    Feature_HasNEON | 0, // VLD4d8_UPD = 1664
    Feature_HasNEON | 0, // VLD4q16 = 1665
    Feature_HasNEON | 0, // VLD4q16Pseudo_UPD = 1666
    Feature_HasNEON | 0, // VLD4q16_UPD = 1667
    Feature_HasNEON | 0, // VLD4q16oddPseudo = 1668
    Feature_HasNEON | 0, // VLD4q16oddPseudo_UPD = 1669
    Feature_HasNEON | 0, // VLD4q32 = 1670
    Feature_HasNEON | 0, // VLD4q32Pseudo_UPD = 1671
    Feature_HasNEON | 0, // VLD4q32_UPD = 1672
    Feature_HasNEON | 0, // VLD4q32oddPseudo = 1673
    Feature_HasNEON | 0, // VLD4q32oddPseudo_UPD = 1674
    Feature_HasNEON | 0, // VLD4q8 = 1675
    Feature_HasNEON | 0, // VLD4q8Pseudo_UPD = 1676
    Feature_HasNEON | 0, // VLD4q8_UPD = 1677
    Feature_HasNEON | 0, // VLD4q8oddPseudo = 1678
    Feature_HasNEON | 0, // VLD4q8oddPseudo_UPD = 1679
    Feature_HasVFP2 | 0, // VLDMDDB_UPD = 1680
    Feature_HasVFP2 | 0, // VLDMDIA = 1681
    Feature_HasVFP2 | 0, // VLDMDIA_UPD = 1682
    Feature_HasVFP2 | 0, // VLDMQIA = 1683
    Feature_HasVFP2 | 0, // VLDMSDB_UPD = 1684
    Feature_HasVFP2 | 0, // VLDMSIA = 1685
    Feature_HasVFP2 | 0, // VLDMSIA_UPD = 1686
    Feature_HasVFP2 | 0, // VLDRD = 1687
    Feature_HasFullFP16 | 0, // VLDRH = 1688
    Feature_HasVFP2 | 0, // VLDRS = 1689
    Feature_HasV8MMainline | Feature_Has8MSecExt | 0, // VLLDM = 1690
    Feature_HasV8MMainline | Feature_Has8MSecExt | 0, // VLSTM = 1691
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VMAXNMD = 1692
    Feature_HasFullFP16 | 0, // VMAXNMH = 1693
    Feature_HasV8 | Feature_HasNEON | 0, // VMAXNMNDf = 1694
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXNMNDh = 1695
    Feature_HasV8 | Feature_HasNEON | 0, // VMAXNMNQf = 1696
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXNMNQh = 1697
    Feature_HasFPARMv8 | 0, // VMAXNMS = 1698
    Feature_HasNEON | 0, // VMAXfd = 1699
    Feature_HasNEON | 0, // VMAXfq = 1700
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXhd = 1701
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXhq = 1702
    Feature_HasNEON | 0, // VMAXsv16i8 = 1703
    Feature_HasNEON | 0, // VMAXsv2i32 = 1704
    Feature_HasNEON | 0, // VMAXsv4i16 = 1705
    Feature_HasNEON | 0, // VMAXsv4i32 = 1706
    Feature_HasNEON | 0, // VMAXsv8i16 = 1707
    Feature_HasNEON | 0, // VMAXsv8i8 = 1708
    Feature_HasNEON | 0, // VMAXuv16i8 = 1709
    Feature_HasNEON | 0, // VMAXuv2i32 = 1710
    Feature_HasNEON | 0, // VMAXuv4i16 = 1711
    Feature_HasNEON | 0, // VMAXuv4i32 = 1712
    Feature_HasNEON | 0, // VMAXuv8i16 = 1713
    Feature_HasNEON | 0, // VMAXuv8i8 = 1714
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VMINNMD = 1715
    Feature_HasFullFP16 | 0, // VMINNMH = 1716
    Feature_HasV8 | Feature_HasNEON | 0, // VMINNMNDf = 1717
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINNMNDh = 1718
    Feature_HasV8 | Feature_HasNEON | 0, // VMINNMNQf = 1719
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINNMNQh = 1720
    Feature_HasFPARMv8 | 0, // VMINNMS = 1721
    Feature_HasNEON | 0, // VMINfd = 1722
    Feature_HasNEON | 0, // VMINfq = 1723
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINhd = 1724
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINhq = 1725
    Feature_HasNEON | 0, // VMINsv16i8 = 1726
    Feature_HasNEON | 0, // VMINsv2i32 = 1727
    Feature_HasNEON | 0, // VMINsv4i16 = 1728
    Feature_HasNEON | 0, // VMINsv4i32 = 1729
    Feature_HasNEON | 0, // VMINsv8i16 = 1730
    Feature_HasNEON | 0, // VMINsv8i8 = 1731
    Feature_HasNEON | 0, // VMINuv16i8 = 1732
    Feature_HasNEON | 0, // VMINuv2i32 = 1733
    Feature_HasNEON | 0, // VMINuv4i16 = 1734
    Feature_HasNEON | 0, // VMINuv4i32 = 1735
    Feature_HasNEON | 0, // VMINuv8i16 = 1736
    Feature_HasNEON | 0, // VMINuv8i8 = 1737
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMLAD = 1738
    Feature_HasFullFP16 | 0, // VMLAH = 1739
    Feature_HasNEON | 0, // VMLALslsv2i32 = 1740
    Feature_HasNEON | 0, // VMLALslsv4i16 = 1741
    Feature_HasNEON | 0, // VMLALsluv2i32 = 1742
    Feature_HasNEON | 0, // VMLALsluv4i16 = 1743
    Feature_HasNEON | 0, // VMLALsv2i64 = 1744
    Feature_HasNEON | 0, // VMLALsv4i32 = 1745
    Feature_HasNEON | 0, // VMLALsv8i16 = 1746
    Feature_HasNEON | 0, // VMLALuv2i64 = 1747
    Feature_HasNEON | 0, // VMLALuv4i32 = 1748
    Feature_HasNEON | 0, // VMLALuv8i16 = 1749
    Feature_HasVFP2 | 0, // VMLAS = 1750
    Feature_HasNEON | 0, // VMLAfd = 1751
    Feature_HasNEON | 0, // VMLAfq = 1752
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAhd = 1753
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAhq = 1754
    Feature_HasNEON | 0, // VMLAslfd = 1755
    Feature_HasNEON | 0, // VMLAslfq = 1756
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAslhd = 1757
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAslhq = 1758
    Feature_HasNEON | 0, // VMLAslv2i32 = 1759
    Feature_HasNEON | 0, // VMLAslv4i16 = 1760
    Feature_HasNEON | 0, // VMLAslv4i32 = 1761
    Feature_HasNEON | 0, // VMLAslv8i16 = 1762
    Feature_HasNEON | 0, // VMLAv16i8 = 1763
    Feature_HasNEON | 0, // VMLAv2i32 = 1764
    Feature_HasNEON | 0, // VMLAv4i16 = 1765
    Feature_HasNEON | 0, // VMLAv4i32 = 1766
    Feature_HasNEON | 0, // VMLAv8i16 = 1767
    Feature_HasNEON | 0, // VMLAv8i8 = 1768
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMLSD = 1769
    Feature_HasFullFP16 | 0, // VMLSH = 1770
    Feature_HasNEON | 0, // VMLSLslsv2i32 = 1771
    Feature_HasNEON | 0, // VMLSLslsv4i16 = 1772
    Feature_HasNEON | 0, // VMLSLsluv2i32 = 1773
    Feature_HasNEON | 0, // VMLSLsluv4i16 = 1774
    Feature_HasNEON | 0, // VMLSLsv2i64 = 1775
    Feature_HasNEON | 0, // VMLSLsv4i32 = 1776
    Feature_HasNEON | 0, // VMLSLsv8i16 = 1777
    Feature_HasNEON | 0, // VMLSLuv2i64 = 1778
    Feature_HasNEON | 0, // VMLSLuv4i32 = 1779
    Feature_HasNEON | 0, // VMLSLuv8i16 = 1780
    Feature_HasVFP2 | 0, // VMLSS = 1781
    Feature_HasNEON | 0, // VMLSfd = 1782
    Feature_HasNEON | 0, // VMLSfq = 1783
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLShd = 1784
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLShq = 1785
    Feature_HasNEON | 0, // VMLSslfd = 1786
    Feature_HasNEON | 0, // VMLSslfq = 1787
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLSslhd = 1788
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLSslhq = 1789
    Feature_HasNEON | 0, // VMLSslv2i32 = 1790
    Feature_HasNEON | 0, // VMLSslv4i16 = 1791
    Feature_HasNEON | 0, // VMLSslv4i32 = 1792
    Feature_HasNEON | 0, // VMLSslv8i16 = 1793
    Feature_HasNEON | 0, // VMLSv16i8 = 1794
    Feature_HasNEON | 0, // VMLSv2i32 = 1795
    Feature_HasNEON | 0, // VMLSv4i16 = 1796
    Feature_HasNEON | 0, // VMLSv4i32 = 1797
    Feature_HasNEON | 0, // VMLSv8i16 = 1798
    Feature_HasNEON | 0, // VMLSv8i8 = 1799
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMOVD = 1800
    Feature_HasVFP2 | 0, // VMOVDRR = 1801
    Feature_HasFullFP16 | 0, // VMOVH = 1802
    Feature_HasFullFP16 | 0, // VMOVHR = 1803
    Feature_HasNEON | 0, // VMOVLsv2i64 = 1804
    Feature_HasNEON | 0, // VMOVLsv4i32 = 1805
    Feature_HasNEON | 0, // VMOVLsv8i16 = 1806
    Feature_HasNEON | 0, // VMOVLuv2i64 = 1807
    Feature_HasNEON | 0, // VMOVLuv4i32 = 1808
    Feature_HasNEON | 0, // VMOVLuv8i16 = 1809
    Feature_HasNEON | 0, // VMOVNv2i32 = 1810
    Feature_HasNEON | 0, // VMOVNv4i16 = 1811
    Feature_HasNEON | 0, // VMOVNv8i8 = 1812
    Feature_HasFullFP16 | 0, // VMOVRH = 1813
    Feature_HasVFP2 | 0, // VMOVRRD = 1814
    Feature_HasVFP2 | 0, // VMOVRRS = 1815
    Feature_HasVFP2 | 0, // VMOVRS = 1816
    Feature_HasVFP2 | 0, // VMOVS = 1817
    Feature_HasVFP2 | 0, // VMOVSR = 1818
    Feature_HasVFP2 | 0, // VMOVSRR = 1819
    Feature_HasNEON | 0, // VMOVv16i8 = 1820
    Feature_HasNEON | 0, // VMOVv1i64 = 1821
    Feature_HasNEON | 0, // VMOVv2f32 = 1822
    Feature_HasNEON | 0, // VMOVv2i32 = 1823
    Feature_HasNEON | 0, // VMOVv2i64 = 1824
    Feature_HasNEON | 0, // VMOVv4f32 = 1825
    Feature_HasNEON | 0, // VMOVv4i16 = 1826
    Feature_HasNEON | 0, // VMOVv4i32 = 1827
    Feature_HasNEON | 0, // VMOVv8i16 = 1828
    Feature_HasNEON | 0, // VMOVv8i8 = 1829
    Feature_HasVFP2 | 0, // VMRS = 1830
    Feature_HasVFP2 | 0, // VMRS_FPEXC = 1831
    Feature_HasVFP2 | 0, // VMRS_FPINST = 1832
    Feature_HasVFP2 | 0, // VMRS_FPINST2 = 1833
    Feature_HasVFP2 | 0, // VMRS_FPSID = 1834
    Feature_HasVFP2 | 0, // VMRS_MVFR0 = 1835
    Feature_HasVFP2 | 0, // VMRS_MVFR1 = 1836
    Feature_HasFPARMv8 | 0, // VMRS_MVFR2 = 1837
    Feature_HasVFP2 | 0, // VMSR = 1838
    Feature_HasVFP2 | 0, // VMSR_FPEXC = 1839
    Feature_HasVFP2 | 0, // VMSR_FPINST = 1840
    Feature_HasVFP2 | 0, // VMSR_FPINST2 = 1841
    Feature_HasVFP2 | 0, // VMSR_FPSID = 1842
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMULD = 1843
    Feature_HasFullFP16 | 0, // VMULH = 1844
    Feature_HasV8 | Feature_HasCrypto | 0, // VMULLp64 = 1845
    Feature_HasNEON | 0, // VMULLp8 = 1846
    Feature_HasNEON | 0, // VMULLslsv2i32 = 1847
    Feature_HasNEON | 0, // VMULLslsv4i16 = 1848
    Feature_HasNEON | 0, // VMULLsluv2i32 = 1849
    Feature_HasNEON | 0, // VMULLsluv4i16 = 1850
    Feature_HasNEON | 0, // VMULLsv2i64 = 1851
    Feature_HasNEON | 0, // VMULLsv4i32 = 1852
    Feature_HasNEON | 0, // VMULLsv8i16 = 1853
    Feature_HasNEON | 0, // VMULLuv2i64 = 1854
    Feature_HasNEON | 0, // VMULLuv4i32 = 1855
    Feature_HasNEON | 0, // VMULLuv8i16 = 1856
    Feature_HasVFP2 | 0, // VMULS = 1857
    Feature_HasNEON | 0, // VMULfd = 1858
    Feature_HasNEON | 0, // VMULfq = 1859
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULhd = 1860
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULhq = 1861
    Feature_HasNEON | 0, // VMULpd = 1862
    Feature_HasNEON | 0, // VMULpq = 1863
    Feature_HasNEON | 0, // VMULslfd = 1864
    Feature_HasNEON | 0, // VMULslfq = 1865
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULslhd = 1866
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULslhq = 1867
    Feature_HasNEON | 0, // VMULslv2i32 = 1868
    Feature_HasNEON | 0, // VMULslv4i16 = 1869
    Feature_HasNEON | 0, // VMULslv4i32 = 1870
    Feature_HasNEON | 0, // VMULslv8i16 = 1871
    Feature_HasNEON | 0, // VMULv16i8 = 1872
    Feature_HasNEON | 0, // VMULv2i32 = 1873
    Feature_HasNEON | 0, // VMULv4i16 = 1874
    Feature_HasNEON | 0, // VMULv4i32 = 1875
    Feature_HasNEON | 0, // VMULv8i16 = 1876
    Feature_HasNEON | 0, // VMULv8i8 = 1877
    Feature_HasNEON | 0, // VMVNd = 1878
    Feature_HasNEON | 0, // VMVNq = 1879
    Feature_HasNEON | 0, // VMVNv2i32 = 1880
    Feature_HasNEON | 0, // VMVNv4i16 = 1881
    Feature_HasNEON | 0, // VMVNv4i32 = 1882
    Feature_HasNEON | 0, // VMVNv8i16 = 1883
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNEGD = 1884
    Feature_HasFullFP16 | 0, // VNEGH = 1885
    Feature_HasVFP2 | 0, // VNEGS = 1886
    Feature_HasNEON | 0, // VNEGf32q = 1887
    Feature_HasNEON | 0, // VNEGfd = 1888
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VNEGhd = 1889
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VNEGhq = 1890
    Feature_HasNEON | 0, // VNEGs16d = 1891
    Feature_HasNEON | 0, // VNEGs16q = 1892
    Feature_HasNEON | 0, // VNEGs32d = 1893
    Feature_HasNEON | 0, // VNEGs32q = 1894
    Feature_HasNEON | 0, // VNEGs8d = 1895
    Feature_HasNEON | 0, // VNEGs8q = 1896
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMLAD = 1897
    Feature_HasFullFP16 | 0, // VNMLAH = 1898
    Feature_HasVFP2 | 0, // VNMLAS = 1899
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMLSD = 1900
    Feature_HasFullFP16 | 0, // VNMLSH = 1901
    Feature_HasVFP2 | 0, // VNMLSS = 1902
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMULD = 1903
    Feature_HasFullFP16 | 0, // VNMULH = 1904
    Feature_HasVFP2 | 0, // VNMULS = 1905
    Feature_HasNEON | 0, // VORNd = 1906
    Feature_HasNEON | 0, // VORNq = 1907
    Feature_HasNEON | 0, // VORRd = 1908
    Feature_HasNEON | 0, // VORRiv2i32 = 1909
    Feature_HasNEON | 0, // VORRiv4i16 = 1910
    Feature_HasNEON | 0, // VORRiv4i32 = 1911
    Feature_HasNEON | 0, // VORRiv8i16 = 1912
    Feature_HasNEON | 0, // VORRq = 1913
    Feature_HasNEON | 0, // VPADALsv16i8 = 1914
    Feature_HasNEON | 0, // VPADALsv2i32 = 1915
    Feature_HasNEON | 0, // VPADALsv4i16 = 1916
    Feature_HasNEON | 0, // VPADALsv4i32 = 1917
    Feature_HasNEON | 0, // VPADALsv8i16 = 1918
    Feature_HasNEON | 0, // VPADALsv8i8 = 1919
    Feature_HasNEON | 0, // VPADALuv16i8 = 1920
    Feature_HasNEON | 0, // VPADALuv2i32 = 1921
    Feature_HasNEON | 0, // VPADALuv4i16 = 1922
    Feature_HasNEON | 0, // VPADALuv4i32 = 1923
    Feature_HasNEON | 0, // VPADALuv8i16 = 1924
    Feature_HasNEON | 0, // VPADALuv8i8 = 1925
    Feature_HasNEON | 0, // VPADDLsv16i8 = 1926
    Feature_HasNEON | 0, // VPADDLsv2i32 = 1927
    Feature_HasNEON | 0, // VPADDLsv4i16 = 1928
    Feature_HasNEON | 0, // VPADDLsv4i32 = 1929
    Feature_HasNEON | 0, // VPADDLsv8i16 = 1930
    Feature_HasNEON | 0, // VPADDLsv8i8 = 1931
    Feature_HasNEON | 0, // VPADDLuv16i8 = 1932
    Feature_HasNEON | 0, // VPADDLuv2i32 = 1933
    Feature_HasNEON | 0, // VPADDLuv4i16 = 1934
    Feature_HasNEON | 0, // VPADDLuv4i32 = 1935
    Feature_HasNEON | 0, // VPADDLuv8i16 = 1936
    Feature_HasNEON | 0, // VPADDLuv8i8 = 1937
    Feature_HasNEON | 0, // VPADDf = 1938
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VPADDh = 1939
    Feature_HasNEON | 0, // VPADDi16 = 1940
    Feature_HasNEON | 0, // VPADDi32 = 1941
    Feature_HasNEON | 0, // VPADDi8 = 1942
    Feature_HasNEON | 0, // VPMAXf = 1943
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VPMAXh = 1944
    Feature_HasNEON | 0, // VPMAXs16 = 1945
    Feature_HasNEON | 0, // VPMAXs32 = 1946
    Feature_HasNEON | 0, // VPMAXs8 = 1947
    Feature_HasNEON | 0, // VPMAXu16 = 1948
    Feature_HasNEON | 0, // VPMAXu32 = 1949
    Feature_HasNEON | 0, // VPMAXu8 = 1950
    Feature_HasNEON | 0, // VPMINf = 1951
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VPMINh = 1952
    Feature_HasNEON | 0, // VPMINs16 = 1953
    Feature_HasNEON | 0, // VPMINs32 = 1954
    Feature_HasNEON | 0, // VPMINs8 = 1955
    Feature_HasNEON | 0, // VPMINu16 = 1956
    Feature_HasNEON | 0, // VPMINu32 = 1957
    Feature_HasNEON | 0, // VPMINu8 = 1958
    Feature_HasNEON | 0, // VQABSv16i8 = 1959
    Feature_HasNEON | 0, // VQABSv2i32 = 1960
    Feature_HasNEON | 0, // VQABSv4i16 = 1961
    Feature_HasNEON | 0, // VQABSv4i32 = 1962
    Feature_HasNEON | 0, // VQABSv8i16 = 1963
    Feature_HasNEON | 0, // VQABSv8i8 = 1964
    Feature_HasNEON | 0, // VQADDsv16i8 = 1965
    Feature_HasNEON | 0, // VQADDsv1i64 = 1966
    Feature_HasNEON | 0, // VQADDsv2i32 = 1967
    Feature_HasNEON | 0, // VQADDsv2i64 = 1968
    Feature_HasNEON | 0, // VQADDsv4i16 = 1969
    Feature_HasNEON | 0, // VQADDsv4i32 = 1970
    Feature_HasNEON | 0, // VQADDsv8i16 = 1971
    Feature_HasNEON | 0, // VQADDsv8i8 = 1972
    Feature_HasNEON | 0, // VQADDuv16i8 = 1973
    Feature_HasNEON | 0, // VQADDuv1i64 = 1974
    Feature_HasNEON | 0, // VQADDuv2i32 = 1975
    Feature_HasNEON | 0, // VQADDuv2i64 = 1976
    Feature_HasNEON | 0, // VQADDuv4i16 = 1977
    Feature_HasNEON | 0, // VQADDuv4i32 = 1978
    Feature_HasNEON | 0, // VQADDuv8i16 = 1979
    Feature_HasNEON | 0, // VQADDuv8i8 = 1980
    Feature_HasNEON | 0, // VQDMLALslv2i32 = 1981
    Feature_HasNEON | 0, // VQDMLALslv4i16 = 1982
    Feature_HasNEON | 0, // VQDMLALv2i64 = 1983
    Feature_HasNEON | 0, // VQDMLALv4i32 = 1984
    Feature_HasNEON | 0, // VQDMLSLslv2i32 = 1985
    Feature_HasNEON | 0, // VQDMLSLslv4i16 = 1986
    Feature_HasNEON | 0, // VQDMLSLv2i64 = 1987
    Feature_HasNEON | 0, // VQDMLSLv4i32 = 1988
    Feature_HasNEON | 0, // VQDMULHslv2i32 = 1989
    Feature_HasNEON | 0, // VQDMULHslv4i16 = 1990
    Feature_HasNEON | 0, // VQDMULHslv4i32 = 1991
    Feature_HasNEON | 0, // VQDMULHslv8i16 = 1992
    Feature_HasNEON | 0, // VQDMULHv2i32 = 1993
    Feature_HasNEON | 0, // VQDMULHv4i16 = 1994
    Feature_HasNEON | 0, // VQDMULHv4i32 = 1995
    Feature_HasNEON | 0, // VQDMULHv8i16 = 1996
    Feature_HasNEON | 0, // VQDMULLslv2i32 = 1997
    Feature_HasNEON | 0, // VQDMULLslv4i16 = 1998
    Feature_HasNEON | 0, // VQDMULLv2i64 = 1999
    Feature_HasNEON | 0, // VQDMULLv4i32 = 2000
    Feature_HasNEON | 0, // VQMOVNsuv2i32 = 2001
    Feature_HasNEON | 0, // VQMOVNsuv4i16 = 2002
    Feature_HasNEON | 0, // VQMOVNsuv8i8 = 2003
    Feature_HasNEON | 0, // VQMOVNsv2i32 = 2004
    Feature_HasNEON | 0, // VQMOVNsv4i16 = 2005
    Feature_HasNEON | 0, // VQMOVNsv8i8 = 2006
    Feature_HasNEON | 0, // VQMOVNuv2i32 = 2007
    Feature_HasNEON | 0, // VQMOVNuv4i16 = 2008
    Feature_HasNEON | 0, // VQMOVNuv8i8 = 2009
    Feature_HasNEON | 0, // VQNEGv16i8 = 2010
    Feature_HasNEON | 0, // VQNEGv2i32 = 2011
    Feature_HasNEON | 0, // VQNEGv4i16 = 2012
    Feature_HasNEON | 0, // VQNEGv4i32 = 2013
    Feature_HasNEON | 0, // VQNEGv8i16 = 2014
    Feature_HasNEON | 0, // VQNEGv8i8 = 2015
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv2i32 = 2016
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv4i16 = 2017
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv4i32 = 2018
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv8i16 = 2019
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv2i32 = 2020
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv4i16 = 2021
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv4i32 = 2022
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv8i16 = 2023
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv2i32 = 2024
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv4i16 = 2025
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv4i32 = 2026
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv8i16 = 2027
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv2i32 = 2028
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv4i16 = 2029
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv4i32 = 2030
    Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv8i16 = 2031
    Feature_HasNEON | 0, // VQRDMULHslv2i32 = 2032
    Feature_HasNEON | 0, // VQRDMULHslv4i16 = 2033
    Feature_HasNEON | 0, // VQRDMULHslv4i32 = 2034
    Feature_HasNEON | 0, // VQRDMULHslv8i16 = 2035
    Feature_HasNEON | 0, // VQRDMULHv2i32 = 2036
    Feature_HasNEON | 0, // VQRDMULHv4i16 = 2037
    Feature_HasNEON | 0, // VQRDMULHv4i32 = 2038
    Feature_HasNEON | 0, // VQRDMULHv8i16 = 2039
    Feature_HasNEON | 0, // VQRSHLsv16i8 = 2040
    Feature_HasNEON | 0, // VQRSHLsv1i64 = 2041
    Feature_HasNEON | 0, // VQRSHLsv2i32 = 2042
    Feature_HasNEON | 0, // VQRSHLsv2i64 = 2043
    Feature_HasNEON | 0, // VQRSHLsv4i16 = 2044
    Feature_HasNEON | 0, // VQRSHLsv4i32 = 2045
    Feature_HasNEON | 0, // VQRSHLsv8i16 = 2046
    Feature_HasNEON | 0, // VQRSHLsv8i8 = 2047
    Feature_HasNEON | 0, // VQRSHLuv16i8 = 2048
    Feature_HasNEON | 0, // VQRSHLuv1i64 = 2049
    Feature_HasNEON | 0, // VQRSHLuv2i32 = 2050
    Feature_HasNEON | 0, // VQRSHLuv2i64 = 2051
    Feature_HasNEON | 0, // VQRSHLuv4i16 = 2052
    Feature_HasNEON | 0, // VQRSHLuv4i32 = 2053
    Feature_HasNEON | 0, // VQRSHLuv8i16 = 2054
    Feature_HasNEON | 0, // VQRSHLuv8i8 = 2055
    Feature_HasNEON | 0, // VQRSHRNsv2i32 = 2056
    Feature_HasNEON | 0, // VQRSHRNsv4i16 = 2057
    Feature_HasNEON | 0, // VQRSHRNsv8i8 = 2058
    Feature_HasNEON | 0, // VQRSHRNuv2i32 = 2059
    Feature_HasNEON | 0, // VQRSHRNuv4i16 = 2060
    Feature_HasNEON | 0, // VQRSHRNuv8i8 = 2061
    Feature_HasNEON | 0, // VQRSHRUNv2i32 = 2062
    Feature_HasNEON | 0, // VQRSHRUNv4i16 = 2063
    Feature_HasNEON | 0, // VQRSHRUNv8i8 = 2064
    Feature_HasNEON | 0, // VQSHLsiv16i8 = 2065
    Feature_HasNEON | 0, // VQSHLsiv1i64 = 2066
    Feature_HasNEON | 0, // VQSHLsiv2i32 = 2067
    Feature_HasNEON | 0, // VQSHLsiv2i64 = 2068
    Feature_HasNEON | 0, // VQSHLsiv4i16 = 2069
    Feature_HasNEON | 0, // VQSHLsiv4i32 = 2070
    Feature_HasNEON | 0, // VQSHLsiv8i16 = 2071
    Feature_HasNEON | 0, // VQSHLsiv8i8 = 2072
    Feature_HasNEON | 0, // VQSHLsuv16i8 = 2073
    Feature_HasNEON | 0, // VQSHLsuv1i64 = 2074
    Feature_HasNEON | 0, // VQSHLsuv2i32 = 2075
    Feature_HasNEON | 0, // VQSHLsuv2i64 = 2076
    Feature_HasNEON | 0, // VQSHLsuv4i16 = 2077
    Feature_HasNEON | 0, // VQSHLsuv4i32 = 2078
    Feature_HasNEON | 0, // VQSHLsuv8i16 = 2079
    Feature_HasNEON | 0, // VQSHLsuv8i8 = 2080
    Feature_HasNEON | 0, // VQSHLsv16i8 = 2081
    Feature_HasNEON | 0, // VQSHLsv1i64 = 2082
    Feature_HasNEON | 0, // VQSHLsv2i32 = 2083
    Feature_HasNEON | 0, // VQSHLsv2i64 = 2084
    Feature_HasNEON | 0, // VQSHLsv4i16 = 2085
    Feature_HasNEON | 0, // VQSHLsv4i32 = 2086
    Feature_HasNEON | 0, // VQSHLsv8i16 = 2087
    Feature_HasNEON | 0, // VQSHLsv8i8 = 2088
    Feature_HasNEON | 0, // VQSHLuiv16i8 = 2089
    Feature_HasNEON | 0, // VQSHLuiv1i64 = 2090
    Feature_HasNEON | 0, // VQSHLuiv2i32 = 2091
    Feature_HasNEON | 0, // VQSHLuiv2i64 = 2092
    Feature_HasNEON | 0, // VQSHLuiv4i16 = 2093
    Feature_HasNEON | 0, // VQSHLuiv4i32 = 2094
    Feature_HasNEON | 0, // VQSHLuiv8i16 = 2095
    Feature_HasNEON | 0, // VQSHLuiv8i8 = 2096
    Feature_HasNEON | 0, // VQSHLuv16i8 = 2097
    Feature_HasNEON | 0, // VQSHLuv1i64 = 2098
    Feature_HasNEON | 0, // VQSHLuv2i32 = 2099
    Feature_HasNEON | 0, // VQSHLuv2i64 = 2100
    Feature_HasNEON | 0, // VQSHLuv4i16 = 2101
    Feature_HasNEON | 0, // VQSHLuv4i32 = 2102
    Feature_HasNEON | 0, // VQSHLuv8i16 = 2103
    Feature_HasNEON | 0, // VQSHLuv8i8 = 2104
    Feature_HasNEON | 0, // VQSHRNsv2i32 = 2105
    Feature_HasNEON | 0, // VQSHRNsv4i16 = 2106
    Feature_HasNEON | 0, // VQSHRNsv8i8 = 2107
    Feature_HasNEON | 0, // VQSHRNuv2i32 = 2108
    Feature_HasNEON | 0, // VQSHRNuv4i16 = 2109
    Feature_HasNEON | 0, // VQSHRNuv8i8 = 2110
    Feature_HasNEON | 0, // VQSHRUNv2i32 = 2111
    Feature_HasNEON | 0, // VQSHRUNv4i16 = 2112
    Feature_HasNEON | 0, // VQSHRUNv8i8 = 2113
    Feature_HasNEON | 0, // VQSUBsv16i8 = 2114
    Feature_HasNEON | 0, // VQSUBsv1i64 = 2115
    Feature_HasNEON | 0, // VQSUBsv2i32 = 2116
    Feature_HasNEON | 0, // VQSUBsv2i64 = 2117
    Feature_HasNEON | 0, // VQSUBsv4i16 = 2118
    Feature_HasNEON | 0, // VQSUBsv4i32 = 2119
    Feature_HasNEON | 0, // VQSUBsv8i16 = 2120
    Feature_HasNEON | 0, // VQSUBsv8i8 = 2121
    Feature_HasNEON | 0, // VQSUBuv16i8 = 2122
    Feature_HasNEON | 0, // VQSUBuv1i64 = 2123
    Feature_HasNEON | 0, // VQSUBuv2i32 = 2124
    Feature_HasNEON | 0, // VQSUBuv2i64 = 2125
    Feature_HasNEON | 0, // VQSUBuv4i16 = 2126
    Feature_HasNEON | 0, // VQSUBuv4i32 = 2127
    Feature_HasNEON | 0, // VQSUBuv8i16 = 2128
    Feature_HasNEON | 0, // VQSUBuv8i8 = 2129
    Feature_HasNEON | 0, // VRADDHNv2i32 = 2130
    Feature_HasNEON | 0, // VRADDHNv4i16 = 2131
    Feature_HasNEON | 0, // VRADDHNv8i8 = 2132
    Feature_HasNEON | 0, // VRECPEd = 2133
    Feature_HasNEON | 0, // VRECPEfd = 2134
    Feature_HasNEON | 0, // VRECPEfq = 2135
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPEhd = 2136
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPEhq = 2137
    Feature_HasNEON | 0, // VRECPEq = 2138
    Feature_HasNEON | 0, // VRECPSfd = 2139
    Feature_HasNEON | 0, // VRECPSfq = 2140
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPShd = 2141
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPShq = 2142
    Feature_HasNEON | 0, // VREV16d8 = 2143
    Feature_HasNEON | 0, // VREV16q8 = 2144
    Feature_HasNEON | 0, // VREV32d16 = 2145
    Feature_HasNEON | 0, // VREV32d8 = 2146
    Feature_HasNEON | 0, // VREV32q16 = 2147
    Feature_HasNEON | 0, // VREV32q8 = 2148
    Feature_HasNEON | 0, // VREV64d16 = 2149
    Feature_HasNEON | 0, // VREV64d32 = 2150
    Feature_HasNEON | 0, // VREV64d8 = 2151
    Feature_HasNEON | 0, // VREV64q16 = 2152
    Feature_HasNEON | 0, // VREV64q32 = 2153
    Feature_HasNEON | 0, // VREV64q8 = 2154
    Feature_HasNEON | 0, // VRHADDsv16i8 = 2155
    Feature_HasNEON | 0, // VRHADDsv2i32 = 2156
    Feature_HasNEON | 0, // VRHADDsv4i16 = 2157
    Feature_HasNEON | 0, // VRHADDsv4i32 = 2158
    Feature_HasNEON | 0, // VRHADDsv8i16 = 2159
    Feature_HasNEON | 0, // VRHADDsv8i8 = 2160
    Feature_HasNEON | 0, // VRHADDuv16i8 = 2161
    Feature_HasNEON | 0, // VRHADDuv2i32 = 2162
    Feature_HasNEON | 0, // VRHADDuv4i16 = 2163
    Feature_HasNEON | 0, // VRHADDuv4i32 = 2164
    Feature_HasNEON | 0, // VRHADDuv8i16 = 2165
    Feature_HasNEON | 0, // VRHADDuv8i8 = 2166
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTAD = 2167
    Feature_HasFullFP16 | 0, // VRINTAH = 2168
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTANDf = 2169
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTANDh = 2170
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTANQf = 2171
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTANQh = 2172
    Feature_HasFPARMv8 | 0, // VRINTAS = 2173
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTMD = 2174
    Feature_HasFullFP16 | 0, // VRINTMH = 2175
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTMNDf = 2176
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTMNDh = 2177
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTMNQf = 2178
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTMNQh = 2179
    Feature_HasFPARMv8 | 0, // VRINTMS = 2180
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTND = 2181
    Feature_HasFullFP16 | 0, // VRINTNH = 2182
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTNNDf = 2183
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTNNDh = 2184
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTNNQf = 2185
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTNNQh = 2186
    Feature_HasFPARMv8 | 0, // VRINTNS = 2187
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTPD = 2188
    Feature_HasFullFP16 | 0, // VRINTPH = 2189
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTPNDf = 2190
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTPNDh = 2191
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTPNQf = 2192
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTPNQh = 2193
    Feature_HasFPARMv8 | 0, // VRINTPS = 2194
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTRD = 2195
    Feature_HasFullFP16 | 0, // VRINTRH = 2196
    Feature_HasFPARMv8 | 0, // VRINTRS = 2197
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTXD = 2198
    Feature_HasFullFP16 | 0, // VRINTXH = 2199
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTXNDf = 2200
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTXNDh = 2201
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTXNQf = 2202
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTXNQh = 2203
    Feature_HasFPARMv8 | 0, // VRINTXS = 2204
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTZD = 2205
    Feature_HasFullFP16 | 0, // VRINTZH = 2206
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTZNDf = 2207
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTZNDh = 2208
    Feature_HasV8 | Feature_HasNEON | 0, // VRINTZNQf = 2209
    Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTZNQh = 2210
    Feature_HasFPARMv8 | 0, // VRINTZS = 2211
    Feature_HasNEON | 0, // VRSHLsv16i8 = 2212
    Feature_HasNEON | 0, // VRSHLsv1i64 = 2213
    Feature_HasNEON | 0, // VRSHLsv2i32 = 2214
    Feature_HasNEON | 0, // VRSHLsv2i64 = 2215
    Feature_HasNEON | 0, // VRSHLsv4i16 = 2216
    Feature_HasNEON | 0, // VRSHLsv4i32 = 2217
    Feature_HasNEON | 0, // VRSHLsv8i16 = 2218
    Feature_HasNEON | 0, // VRSHLsv8i8 = 2219
    Feature_HasNEON | 0, // VRSHLuv16i8 = 2220
    Feature_HasNEON | 0, // VRSHLuv1i64 = 2221
    Feature_HasNEON | 0, // VRSHLuv2i32 = 2222
    Feature_HasNEON | 0, // VRSHLuv2i64 = 2223
    Feature_HasNEON | 0, // VRSHLuv4i16 = 2224
    Feature_HasNEON | 0, // VRSHLuv4i32 = 2225
    Feature_HasNEON | 0, // VRSHLuv8i16 = 2226
    Feature_HasNEON | 0, // VRSHLuv8i8 = 2227
    Feature_HasNEON | 0, // VRSHRNv2i32 = 2228
    Feature_HasNEON | 0, // VRSHRNv4i16 = 2229
    Feature_HasNEON | 0, // VRSHRNv8i8 = 2230
    Feature_HasNEON | 0, // VRSHRsv16i8 = 2231
    Feature_HasNEON | 0, // VRSHRsv1i64 = 2232
    Feature_HasNEON | 0, // VRSHRsv2i32 = 2233
    Feature_HasNEON | 0, // VRSHRsv2i64 = 2234
    Feature_HasNEON | 0, // VRSHRsv4i16 = 2235
    Feature_HasNEON | 0, // VRSHRsv4i32 = 2236
    Feature_HasNEON | 0, // VRSHRsv8i16 = 2237
    Feature_HasNEON | 0, // VRSHRsv8i8 = 2238
    Feature_HasNEON | 0, // VRSHRuv16i8 = 2239
    Feature_HasNEON | 0, // VRSHRuv1i64 = 2240
    Feature_HasNEON | 0, // VRSHRuv2i32 = 2241
    Feature_HasNEON | 0, // VRSHRuv2i64 = 2242
    Feature_HasNEON | 0, // VRSHRuv4i16 = 2243
    Feature_HasNEON | 0, // VRSHRuv4i32 = 2244
    Feature_HasNEON | 0, // VRSHRuv8i16 = 2245
    Feature_HasNEON | 0, // VRSHRuv8i8 = 2246
    Feature_HasNEON | 0, // VRSQRTEd = 2247
    Feature_HasNEON | 0, // VRSQRTEfd = 2248
    Feature_HasNEON | 0, // VRSQRTEfq = 2249
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTEhd = 2250
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTEhq = 2251
    Feature_HasNEON | 0, // VRSQRTEq = 2252
    Feature_HasNEON | 0, // VRSQRTSfd = 2253
    Feature_HasNEON | 0, // VRSQRTSfq = 2254
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTShd = 2255
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTShq = 2256
    Feature_HasNEON | 0, // VRSRAsv16i8 = 2257
    Feature_HasNEON | 0, // VRSRAsv1i64 = 2258
    Feature_HasNEON | 0, // VRSRAsv2i32 = 2259
    Feature_HasNEON | 0, // VRSRAsv2i64 = 2260
    Feature_HasNEON | 0, // VRSRAsv4i16 = 2261
    Feature_HasNEON | 0, // VRSRAsv4i32 = 2262
    Feature_HasNEON | 0, // VRSRAsv8i16 = 2263
    Feature_HasNEON | 0, // VRSRAsv8i8 = 2264
    Feature_HasNEON | 0, // VRSRAuv16i8 = 2265
    Feature_HasNEON | 0, // VRSRAuv1i64 = 2266
    Feature_HasNEON | 0, // VRSRAuv2i32 = 2267
    Feature_HasNEON | 0, // VRSRAuv2i64 = 2268
    Feature_HasNEON | 0, // VRSRAuv4i16 = 2269
    Feature_HasNEON | 0, // VRSRAuv4i32 = 2270
    Feature_HasNEON | 0, // VRSRAuv8i16 = 2271
    Feature_HasNEON | 0, // VRSRAuv8i8 = 2272
    Feature_HasNEON | 0, // VRSUBHNv2i32 = 2273
    Feature_HasNEON | 0, // VRSUBHNv4i16 = 2274
    Feature_HasNEON | 0, // VRSUBHNv8i8 = 2275
    Feature_HasDotProd | 0, // VSDOTD = 2276
    Feature_HasDotProd | 0, // VSDOTDI = 2277
    Feature_HasDotProd | 0, // VSDOTQ = 2278
    Feature_HasDotProd | 0, // VSDOTQI = 2279
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELEQD = 2280
    Feature_HasFullFP16 | 0, // VSELEQH = 2281
    Feature_HasFPARMv8 | 0, // VSELEQS = 2282
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELGED = 2283
    Feature_HasFullFP16 | 0, // VSELGEH = 2284
    Feature_HasFPARMv8 | 0, // VSELGES = 2285
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELGTD = 2286
    Feature_HasFullFP16 | 0, // VSELGTH = 2287
    Feature_HasFPARMv8 | 0, // VSELGTS = 2288
    Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELVSD = 2289
    Feature_HasFullFP16 | 0, // VSELVSH = 2290
    Feature_HasFPARMv8 | 0, // VSELVSS = 2291
    Feature_HasNEON | 0, // VSETLNi16 = 2292
    Feature_HasVFP2 | 0, // VSETLNi32 = 2293
    Feature_HasNEON | 0, // VSETLNi8 = 2294
    Feature_HasNEON | 0, // VSHLLi16 = 2295
    Feature_HasNEON | 0, // VSHLLi32 = 2296
    Feature_HasNEON | 0, // VSHLLi8 = 2297
    Feature_HasNEON | 0, // VSHLLsv2i64 = 2298
    Feature_HasNEON | 0, // VSHLLsv4i32 = 2299
    Feature_HasNEON | 0, // VSHLLsv8i16 = 2300
    Feature_HasNEON | 0, // VSHLLuv2i64 = 2301
    Feature_HasNEON | 0, // VSHLLuv4i32 = 2302
    Feature_HasNEON | 0, // VSHLLuv8i16 = 2303
    Feature_HasNEON | 0, // VSHLiv16i8 = 2304
    Feature_HasNEON | 0, // VSHLiv1i64 = 2305
    Feature_HasNEON | 0, // VSHLiv2i32 = 2306
    Feature_HasNEON | 0, // VSHLiv2i64 = 2307
    Feature_HasNEON | 0, // VSHLiv4i16 = 2308
    Feature_HasNEON | 0, // VSHLiv4i32 = 2309
    Feature_HasNEON | 0, // VSHLiv8i16 = 2310
    Feature_HasNEON | 0, // VSHLiv8i8 = 2311
    Feature_HasNEON | 0, // VSHLsv16i8 = 2312
    Feature_HasNEON | 0, // VSHLsv1i64 = 2313
    Feature_HasNEON | 0, // VSHLsv2i32 = 2314
    Feature_HasNEON | 0, // VSHLsv2i64 = 2315
    Feature_HasNEON | 0, // VSHLsv4i16 = 2316
    Feature_HasNEON | 0, // VSHLsv4i32 = 2317
    Feature_HasNEON | 0, // VSHLsv8i16 = 2318
    Feature_HasNEON | 0, // VSHLsv8i8 = 2319
    Feature_HasNEON | 0, // VSHLuv16i8 = 2320
    Feature_HasNEON | 0, // VSHLuv1i64 = 2321
    Feature_HasNEON | 0, // VSHLuv2i32 = 2322
    Feature_HasNEON | 0, // VSHLuv2i64 = 2323
    Feature_HasNEON | 0, // VSHLuv4i16 = 2324
    Feature_HasNEON | 0, // VSHLuv4i32 = 2325
    Feature_HasNEON | 0, // VSHLuv8i16 = 2326
    Feature_HasNEON | 0, // VSHLuv8i8 = 2327
    Feature_HasNEON | 0, // VSHRNv2i32 = 2328
    Feature_HasNEON | 0, // VSHRNv4i16 = 2329
    Feature_HasNEON | 0, // VSHRNv8i8 = 2330
    Feature_HasNEON | 0, // VSHRsv16i8 = 2331
    Feature_HasNEON | 0, // VSHRsv1i64 = 2332
    Feature_HasNEON | 0, // VSHRsv2i32 = 2333
    Feature_HasNEON | 0, // VSHRsv2i64 = 2334
    Feature_HasNEON | 0, // VSHRsv4i16 = 2335
    Feature_HasNEON | 0, // VSHRsv4i32 = 2336
    Feature_HasNEON | 0, // VSHRsv8i16 = 2337
    Feature_HasNEON | 0, // VSHRsv8i8 = 2338
    Feature_HasNEON | 0, // VSHRuv16i8 = 2339
    Feature_HasNEON | 0, // VSHRuv1i64 = 2340
    Feature_HasNEON | 0, // VSHRuv2i32 = 2341
    Feature_HasNEON | 0, // VSHRuv2i64 = 2342
    Feature_HasNEON | 0, // VSHRuv4i16 = 2343
    Feature_HasNEON | 0, // VSHRuv4i32 = 2344
    Feature_HasNEON | 0, // VSHRuv8i16 = 2345
    Feature_HasNEON | 0, // VSHRuv8i8 = 2346
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSHTOD = 2347
    Feature_HasFullFP16 | 0, // VSHTOH = 2348
    Feature_HasVFP2 | 0, // VSHTOS = 2349
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSITOD = 2350
    Feature_HasFullFP16 | 0, // VSITOH = 2351
    Feature_HasVFP2 | 0, // VSITOS = 2352
    Feature_HasNEON | 0, // VSLIv16i8 = 2353
    Feature_HasNEON | 0, // VSLIv1i64 = 2354
    Feature_HasNEON | 0, // VSLIv2i32 = 2355
    Feature_HasNEON | 0, // VSLIv2i64 = 2356
    Feature_HasNEON | 0, // VSLIv4i16 = 2357
    Feature_HasNEON | 0, // VSLIv4i32 = 2358
    Feature_HasNEON | 0, // VSLIv8i16 = 2359
    Feature_HasNEON | 0, // VSLIv8i8 = 2360
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSLTOD = 2361
    Feature_HasFullFP16 | 0, // VSLTOH = 2362
    Feature_HasVFP2 | 0, // VSLTOS = 2363
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSQRTD = 2364
    Feature_HasFullFP16 | 0, // VSQRTH = 2365
    Feature_HasVFP2 | 0, // VSQRTS = 2366
    Feature_HasNEON | 0, // VSRAsv16i8 = 2367
    Feature_HasNEON | 0, // VSRAsv1i64 = 2368
    Feature_HasNEON | 0, // VSRAsv2i32 = 2369
    Feature_HasNEON | 0, // VSRAsv2i64 = 2370
    Feature_HasNEON | 0, // VSRAsv4i16 = 2371
    Feature_HasNEON | 0, // VSRAsv4i32 = 2372
    Feature_HasNEON | 0, // VSRAsv8i16 = 2373
    Feature_HasNEON | 0, // VSRAsv8i8 = 2374
    Feature_HasNEON | 0, // VSRAuv16i8 = 2375
    Feature_HasNEON | 0, // VSRAuv1i64 = 2376
    Feature_HasNEON | 0, // VSRAuv2i32 = 2377
    Feature_HasNEON | 0, // VSRAuv2i64 = 2378
    Feature_HasNEON | 0, // VSRAuv4i16 = 2379
    Feature_HasNEON | 0, // VSRAuv4i32 = 2380
    Feature_HasNEON | 0, // VSRAuv8i16 = 2381
    Feature_HasNEON | 0, // VSRAuv8i8 = 2382
    Feature_HasNEON | 0, // VSRIv16i8 = 2383
    Feature_HasNEON | 0, // VSRIv1i64 = 2384
    Feature_HasNEON | 0, // VSRIv2i32 = 2385
    Feature_HasNEON | 0, // VSRIv2i64 = 2386
    Feature_HasNEON | 0, // VSRIv4i16 = 2387
    Feature_HasNEON | 0, // VSRIv4i32 = 2388
    Feature_HasNEON | 0, // VSRIv8i16 = 2389
    Feature_HasNEON | 0, // VSRIv8i8 = 2390
    Feature_HasNEON | 0, // VST1LNd16 = 2391
    Feature_HasNEON | 0, // VST1LNd16_UPD = 2392
    Feature_HasNEON | 0, // VST1LNd32 = 2393
    Feature_HasNEON | 0, // VST1LNd32_UPD = 2394
    Feature_HasNEON | 0, // VST1LNd8 = 2395
    Feature_HasNEON | 0, // VST1LNd8_UPD = 2396
    Feature_HasNEON | 0, // VST1LNq16Pseudo = 2397
    Feature_HasNEON | 0, // VST1LNq16Pseudo_UPD = 2398
    Feature_HasNEON | 0, // VST1LNq32Pseudo = 2399
    Feature_HasNEON | 0, // VST1LNq32Pseudo_UPD = 2400
    Feature_HasNEON | 0, // VST1LNq8Pseudo = 2401
    Feature_HasNEON | 0, // VST1LNq8Pseudo_UPD = 2402
    Feature_HasNEON | 0, // VST1d16 = 2403
    Feature_HasNEON | 0, // VST1d16Q = 2404
    Feature_HasNEON | 0, // VST1d16QPseudo = 2405
    Feature_HasNEON | 0, // VST1d16Qwb_fixed = 2406
    Feature_HasNEON | 0, // VST1d16Qwb_register = 2407
    Feature_HasNEON | 0, // VST1d16T = 2408
    Feature_HasNEON | 0, // VST1d16TPseudo = 2409
    Feature_HasNEON | 0, // VST1d16Twb_fixed = 2410
    Feature_HasNEON | 0, // VST1d16Twb_register = 2411
    Feature_HasNEON | 0, // VST1d16wb_fixed = 2412
    Feature_HasNEON | 0, // VST1d16wb_register = 2413
    Feature_HasNEON | 0, // VST1d32 = 2414
    Feature_HasNEON | 0, // VST1d32Q = 2415
    Feature_HasNEON | 0, // VST1d32QPseudo = 2416
    Feature_HasNEON | 0, // VST1d32Qwb_fixed = 2417
    Feature_HasNEON | 0, // VST1d32Qwb_register = 2418
    Feature_HasNEON | 0, // VST1d32T = 2419
    Feature_HasNEON | 0, // VST1d32TPseudo = 2420
    Feature_HasNEON | 0, // VST1d32Twb_fixed = 2421
    Feature_HasNEON | 0, // VST1d32Twb_register = 2422
    Feature_HasNEON | 0, // VST1d32wb_fixed = 2423
    Feature_HasNEON | 0, // VST1d32wb_register = 2424
    Feature_HasNEON | 0, // VST1d64 = 2425
    Feature_HasNEON | 0, // VST1d64Q = 2426
    Feature_HasNEON | 0, // VST1d64QPseudo = 2427
    Feature_HasNEON | 0, // VST1d64QPseudoWB_fixed = 2428
    Feature_HasNEON | 0, // VST1d64QPseudoWB_register = 2429
    Feature_HasNEON | 0, // VST1d64Qwb_fixed = 2430
    Feature_HasNEON | 0, // VST1d64Qwb_register = 2431
    Feature_HasNEON | 0, // VST1d64T = 2432
    Feature_HasNEON | 0, // VST1d64TPseudo = 2433
    Feature_HasNEON | 0, // VST1d64TPseudoWB_fixed = 2434
    Feature_HasNEON | 0, // VST1d64TPseudoWB_register = 2435
    Feature_HasNEON | 0, // VST1d64Twb_fixed = 2436
    Feature_HasNEON | 0, // VST1d64Twb_register = 2437
    Feature_HasNEON | 0, // VST1d64wb_fixed = 2438
    Feature_HasNEON | 0, // VST1d64wb_register = 2439
    Feature_HasNEON | 0, // VST1d8 = 2440
    Feature_HasNEON | 0, // VST1d8Q = 2441
    Feature_HasNEON | 0, // VST1d8QPseudo = 2442
    Feature_HasNEON | 0, // VST1d8Qwb_fixed = 2443
    Feature_HasNEON | 0, // VST1d8Qwb_register = 2444
    Feature_HasNEON | 0, // VST1d8T = 2445
    Feature_HasNEON | 0, // VST1d8TPseudo = 2446
    Feature_HasNEON | 0, // VST1d8Twb_fixed = 2447
    Feature_HasNEON | 0, // VST1d8Twb_register = 2448
    Feature_HasNEON | 0, // VST1d8wb_fixed = 2449
    Feature_HasNEON | 0, // VST1d8wb_register = 2450
    Feature_HasNEON | 0, // VST1q16 = 2451
    Feature_HasNEON | 0, // VST1q16HighQPseudo = 2452
    Feature_HasNEON | 0, // VST1q16HighTPseudo = 2453
    Feature_HasNEON | 0, // VST1q16LowQPseudo_UPD = 2454
    Feature_HasNEON | 0, // VST1q16LowTPseudo_UPD = 2455
    Feature_HasNEON | 0, // VST1q16wb_fixed = 2456
    Feature_HasNEON | 0, // VST1q16wb_register = 2457
    Feature_HasNEON | 0, // VST1q32 = 2458
    Feature_HasNEON | 0, // VST1q32HighQPseudo = 2459
    Feature_HasNEON | 0, // VST1q32HighTPseudo = 2460
    Feature_HasNEON | 0, // VST1q32LowQPseudo_UPD = 2461
    Feature_HasNEON | 0, // VST1q32LowTPseudo_UPD = 2462
    Feature_HasNEON | 0, // VST1q32wb_fixed = 2463
    Feature_HasNEON | 0, // VST1q32wb_register = 2464
    Feature_HasNEON | 0, // VST1q64 = 2465
    Feature_HasNEON | 0, // VST1q64HighQPseudo = 2466
    Feature_HasNEON | 0, // VST1q64HighTPseudo = 2467
    Feature_HasNEON | 0, // VST1q64LowQPseudo_UPD = 2468
    Feature_HasNEON | 0, // VST1q64LowTPseudo_UPD = 2469
    Feature_HasNEON | 0, // VST1q64wb_fixed = 2470
    Feature_HasNEON | 0, // VST1q64wb_register = 2471
    Feature_HasNEON | 0, // VST1q8 = 2472
    Feature_HasNEON | 0, // VST1q8HighQPseudo = 2473
    Feature_HasNEON | 0, // VST1q8HighTPseudo = 2474
    Feature_HasNEON | 0, // VST1q8LowQPseudo_UPD = 2475
    Feature_HasNEON | 0, // VST1q8LowTPseudo_UPD = 2476
    Feature_HasNEON | 0, // VST1q8wb_fixed = 2477
    Feature_HasNEON | 0, // VST1q8wb_register = 2478
    Feature_HasNEON | 0, // VST2LNd16 = 2479
    Feature_HasNEON | 0, // VST2LNd16Pseudo = 2480
    Feature_HasNEON | 0, // VST2LNd16Pseudo_UPD = 2481
    Feature_HasNEON | 0, // VST2LNd16_UPD = 2482
    Feature_HasNEON | 0, // VST2LNd32 = 2483
    Feature_HasNEON | 0, // VST2LNd32Pseudo = 2484
    Feature_HasNEON | 0, // VST2LNd32Pseudo_UPD = 2485
    Feature_HasNEON | 0, // VST2LNd32_UPD = 2486
    Feature_HasNEON | 0, // VST2LNd8 = 2487
    Feature_HasNEON | 0, // VST2LNd8Pseudo = 2488
    Feature_HasNEON | 0, // VST2LNd8Pseudo_UPD = 2489
    Feature_HasNEON | 0, // VST2LNd8_UPD = 2490
    Feature_HasNEON | 0, // VST2LNq16 = 2491
    Feature_HasNEON | 0, // VST2LNq16Pseudo = 2492
    Feature_HasNEON | 0, // VST2LNq16Pseudo_UPD = 2493
    Feature_HasNEON | 0, // VST2LNq16_UPD = 2494
    Feature_HasNEON | 0, // VST2LNq32 = 2495
    Feature_HasNEON | 0, // VST2LNq32Pseudo = 2496
    Feature_HasNEON | 0, // VST2LNq32Pseudo_UPD = 2497
    Feature_HasNEON | 0, // VST2LNq32_UPD = 2498
    Feature_HasNEON | 0, // VST2b16 = 2499
    Feature_HasNEON | 0, // VST2b16wb_fixed = 2500
    Feature_HasNEON | 0, // VST2b16wb_register = 2501
    Feature_HasNEON | 0, // VST2b32 = 2502
    Feature_HasNEON | 0, // VST2b32wb_fixed = 2503
    Feature_HasNEON | 0, // VST2b32wb_register = 2504
    Feature_HasNEON | 0, // VST2b8 = 2505
    Feature_HasNEON | 0, // VST2b8wb_fixed = 2506
    Feature_HasNEON | 0, // VST2b8wb_register = 2507
    Feature_HasNEON | 0, // VST2d16 = 2508
    Feature_HasNEON | 0, // VST2d16wb_fixed = 2509
    Feature_HasNEON | 0, // VST2d16wb_register = 2510
    Feature_HasNEON | 0, // VST2d32 = 2511
    Feature_HasNEON | 0, // VST2d32wb_fixed = 2512
    Feature_HasNEON | 0, // VST2d32wb_register = 2513
    Feature_HasNEON | 0, // VST2d8 = 2514
    Feature_HasNEON | 0, // VST2d8wb_fixed = 2515
    Feature_HasNEON | 0, // VST2d8wb_register = 2516
    Feature_HasNEON | 0, // VST2q16 = 2517
    Feature_HasNEON | 0, // VST2q16Pseudo = 2518
    Feature_HasNEON | 0, // VST2q16PseudoWB_fixed = 2519
    Feature_HasNEON | 0, // VST2q16PseudoWB_register = 2520
    Feature_HasNEON | 0, // VST2q16wb_fixed = 2521
    Feature_HasNEON | 0, // VST2q16wb_register = 2522
    Feature_HasNEON | 0, // VST2q32 = 2523
    Feature_HasNEON | 0, // VST2q32Pseudo = 2524
    Feature_HasNEON | 0, // VST2q32PseudoWB_fixed = 2525
    Feature_HasNEON | 0, // VST2q32PseudoWB_register = 2526
    Feature_HasNEON | 0, // VST2q32wb_fixed = 2527
    Feature_HasNEON | 0, // VST2q32wb_register = 2528
    Feature_HasNEON | 0, // VST2q8 = 2529
    Feature_HasNEON | 0, // VST2q8Pseudo = 2530
    Feature_HasNEON | 0, // VST2q8PseudoWB_fixed = 2531
    Feature_HasNEON | 0, // VST2q8PseudoWB_register = 2532
    Feature_HasNEON | 0, // VST2q8wb_fixed = 2533
    Feature_HasNEON | 0, // VST2q8wb_register = 2534
    Feature_HasNEON | 0, // VST3LNd16 = 2535
    Feature_HasNEON | 0, // VST3LNd16Pseudo = 2536
    Feature_HasNEON | 0, // VST3LNd16Pseudo_UPD = 2537
    Feature_HasNEON | 0, // VST3LNd16_UPD = 2538
    Feature_HasNEON | 0, // VST3LNd32 = 2539
    Feature_HasNEON | 0, // VST3LNd32Pseudo = 2540
    Feature_HasNEON | 0, // VST3LNd32Pseudo_UPD = 2541
    Feature_HasNEON | 0, // VST3LNd32_UPD = 2542
    Feature_HasNEON | 0, // VST3LNd8 = 2543
    Feature_HasNEON | 0, // VST3LNd8Pseudo = 2544
    Feature_HasNEON | 0, // VST3LNd8Pseudo_UPD = 2545
    Feature_HasNEON | 0, // VST3LNd8_UPD = 2546
    Feature_HasNEON | 0, // VST3LNq16 = 2547
    Feature_HasNEON | 0, // VST3LNq16Pseudo = 2548
    Feature_HasNEON | 0, // VST3LNq16Pseudo_UPD = 2549
    Feature_HasNEON | 0, // VST3LNq16_UPD = 2550
    Feature_HasNEON | 0, // VST3LNq32 = 2551
    Feature_HasNEON | 0, // VST3LNq32Pseudo = 2552
    Feature_HasNEON | 0, // VST3LNq32Pseudo_UPD = 2553
    Feature_HasNEON | 0, // VST3LNq32_UPD = 2554
    Feature_HasNEON | 0, // VST3d16 = 2555
    Feature_HasNEON | 0, // VST3d16Pseudo = 2556
    Feature_HasNEON | 0, // VST3d16Pseudo_UPD = 2557
    Feature_HasNEON | 0, // VST3d16_UPD = 2558
    Feature_HasNEON | 0, // VST3d32 = 2559
    Feature_HasNEON | 0, // VST3d32Pseudo = 2560
    Feature_HasNEON | 0, // VST3d32Pseudo_UPD = 2561
    Feature_HasNEON | 0, // VST3d32_UPD = 2562
    Feature_HasNEON | 0, // VST3d8 = 2563
    Feature_HasNEON | 0, // VST3d8Pseudo = 2564
    Feature_HasNEON | 0, // VST3d8Pseudo_UPD = 2565
    Feature_HasNEON | 0, // VST3d8_UPD = 2566
    Feature_HasNEON | 0, // VST3q16 = 2567
    Feature_HasNEON | 0, // VST3q16Pseudo_UPD = 2568
    Feature_HasNEON | 0, // VST3q16_UPD = 2569
    Feature_HasNEON | 0, // VST3q16oddPseudo = 2570
    Feature_HasNEON | 0, // VST3q16oddPseudo_UPD = 2571
    Feature_HasNEON | 0, // VST3q32 = 2572
    Feature_HasNEON | 0, // VST3q32Pseudo_UPD = 2573
    Feature_HasNEON | 0, // VST3q32_UPD = 2574
    Feature_HasNEON | 0, // VST3q32oddPseudo = 2575
    Feature_HasNEON | 0, // VST3q32oddPseudo_UPD = 2576
    Feature_HasNEON | 0, // VST3q8 = 2577
    Feature_HasNEON | 0, // VST3q8Pseudo_UPD = 2578
    Feature_HasNEON | 0, // VST3q8_UPD = 2579
    Feature_HasNEON | 0, // VST3q8oddPseudo = 2580
    Feature_HasNEON | 0, // VST3q8oddPseudo_UPD = 2581
    Feature_HasNEON | 0, // VST4LNd16 = 2582
    Feature_HasNEON | 0, // VST4LNd16Pseudo = 2583
    Feature_HasNEON | 0, // VST4LNd16Pseudo_UPD = 2584
    Feature_HasNEON | 0, // VST4LNd16_UPD = 2585
    Feature_HasNEON | 0, // VST4LNd32 = 2586
    Feature_HasNEON | 0, // VST4LNd32Pseudo = 2587
    Feature_HasNEON | 0, // VST4LNd32Pseudo_UPD = 2588
    Feature_HasNEON | 0, // VST4LNd32_UPD = 2589
    Feature_HasNEON | 0, // VST4LNd8 = 2590
    Feature_HasNEON | 0, // VST4LNd8Pseudo = 2591
    Feature_HasNEON | 0, // VST4LNd8Pseudo_UPD = 2592
    Feature_HasNEON | 0, // VST4LNd8_UPD = 2593
    Feature_HasNEON | 0, // VST4LNq16 = 2594
    Feature_HasNEON | 0, // VST4LNq16Pseudo = 2595
    Feature_HasNEON | 0, // VST4LNq16Pseudo_UPD = 2596
    Feature_HasNEON | 0, // VST4LNq16_UPD = 2597
    Feature_HasNEON | 0, // VST4LNq32 = 2598
    Feature_HasNEON | 0, // VST4LNq32Pseudo = 2599
    Feature_HasNEON | 0, // VST4LNq32Pseudo_UPD = 2600
    Feature_HasNEON | 0, // VST4LNq32_UPD = 2601
    Feature_HasNEON | 0, // VST4d16 = 2602
    Feature_HasNEON | 0, // VST4d16Pseudo = 2603
    Feature_HasNEON | 0, // VST4d16Pseudo_UPD = 2604
    Feature_HasNEON | 0, // VST4d16_UPD = 2605
    Feature_HasNEON | 0, // VST4d32 = 2606
    Feature_HasNEON | 0, // VST4d32Pseudo = 2607
    Feature_HasNEON | 0, // VST4d32Pseudo_UPD = 2608
    Feature_HasNEON | 0, // VST4d32_UPD = 2609
    Feature_HasNEON | 0, // VST4d8 = 2610
    Feature_HasNEON | 0, // VST4d8Pseudo = 2611
    Feature_HasNEON | 0, // VST4d8Pseudo_UPD = 2612
    Feature_HasNEON | 0, // VST4d8_UPD = 2613
    Feature_HasNEON | 0, // VST4q16 = 2614
    Feature_HasNEON | 0, // VST4q16Pseudo_UPD = 2615
    Feature_HasNEON | 0, // VST4q16_UPD = 2616
    Feature_HasNEON | 0, // VST4q16oddPseudo = 2617
    Feature_HasNEON | 0, // VST4q16oddPseudo_UPD = 2618
    Feature_HasNEON | 0, // VST4q32 = 2619
    Feature_HasNEON | 0, // VST4q32Pseudo_UPD = 2620
    Feature_HasNEON | 0, // VST4q32_UPD = 2621
    Feature_HasNEON | 0, // VST4q32oddPseudo = 2622
    Feature_HasNEON | 0, // VST4q32oddPseudo_UPD = 2623
    Feature_HasNEON | 0, // VST4q8 = 2624
    Feature_HasNEON | 0, // VST4q8Pseudo_UPD = 2625
    Feature_HasNEON | 0, // VST4q8_UPD = 2626
    Feature_HasNEON | 0, // VST4q8oddPseudo = 2627
    Feature_HasNEON | 0, // VST4q8oddPseudo_UPD = 2628
    Feature_HasVFP2 | 0, // VSTMDDB_UPD = 2629
    Feature_HasVFP2 | 0, // VSTMDIA = 2630
    Feature_HasVFP2 | 0, // VSTMDIA_UPD = 2631
    Feature_HasVFP2 | 0, // VSTMQIA = 2632
    Feature_HasVFP2 | 0, // VSTMSDB_UPD = 2633
    Feature_HasVFP2 | 0, // VSTMSIA = 2634
    Feature_HasVFP2 | 0, // VSTMSIA_UPD = 2635
    Feature_HasVFP2 | 0, // VSTRD = 2636
    Feature_HasFullFP16 | 0, // VSTRH = 2637
    Feature_HasVFP2 | 0, // VSTRS = 2638
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSUBD = 2639
    Feature_HasFullFP16 | 0, // VSUBH = 2640
    Feature_HasNEON | 0, // VSUBHNv2i32 = 2641
    Feature_HasNEON | 0, // VSUBHNv4i16 = 2642
    Feature_HasNEON | 0, // VSUBHNv8i8 = 2643
    Feature_HasNEON | 0, // VSUBLsv2i64 = 2644
    Feature_HasNEON | 0, // VSUBLsv4i32 = 2645
    Feature_HasNEON | 0, // VSUBLsv8i16 = 2646
    Feature_HasNEON | 0, // VSUBLuv2i64 = 2647
    Feature_HasNEON | 0, // VSUBLuv4i32 = 2648
    Feature_HasNEON | 0, // VSUBLuv8i16 = 2649
    Feature_HasVFP2 | 0, // VSUBS = 2650
    Feature_HasNEON | 0, // VSUBWsv2i64 = 2651
    Feature_HasNEON | 0, // VSUBWsv4i32 = 2652
    Feature_HasNEON | 0, // VSUBWsv8i16 = 2653
    Feature_HasNEON | 0, // VSUBWuv2i64 = 2654
    Feature_HasNEON | 0, // VSUBWuv4i32 = 2655
    Feature_HasNEON | 0, // VSUBWuv8i16 = 2656
    Feature_HasNEON | 0, // VSUBfd = 2657
    Feature_HasNEON | 0, // VSUBfq = 2658
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VSUBhd = 2659
    Feature_HasNEON | Feature_HasFullFP16 | 0, // VSUBhq = 2660
    Feature_HasNEON | 0, // VSUBv16i8 = 2661
    Feature_HasNEON | 0, // VSUBv1i64 = 2662
    Feature_HasNEON | 0, // VSUBv2i32 = 2663
    Feature_HasNEON | 0, // VSUBv2i64 = 2664
    Feature_HasNEON | 0, // VSUBv4i16 = 2665
    Feature_HasNEON | 0, // VSUBv4i32 = 2666
    Feature_HasNEON | 0, // VSUBv8i16 = 2667
    Feature_HasNEON | 0, // VSUBv8i8 = 2668
    Feature_HasNEON | 0, // VSWPd = 2669
    Feature_HasNEON | 0, // VSWPq = 2670
    Feature_HasNEON | 0, // VTBL1 = 2671
    Feature_HasNEON | 0, // VTBL2 = 2672
    Feature_HasNEON | 0, // VTBL3 = 2673
    Feature_HasNEON | 0, // VTBL3Pseudo = 2674
    Feature_HasNEON | 0, // VTBL4 = 2675
    Feature_HasNEON | 0, // VTBL4Pseudo = 2676
    Feature_HasNEON | 0, // VTBX1 = 2677
    Feature_HasNEON | 0, // VTBX2 = 2678
    Feature_HasNEON | 0, // VTBX3 = 2679
    Feature_HasNEON | 0, // VTBX3Pseudo = 2680
    Feature_HasNEON | 0, // VTBX4 = 2681
    Feature_HasNEON | 0, // VTBX4Pseudo = 2682
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSHD = 2683
    Feature_HasFullFP16 | 0, // VTOSHH = 2684
    Feature_HasVFP2 | 0, // VTOSHS = 2685
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSIRD = 2686
    Feature_HasFullFP16 | 0, // VTOSIRH = 2687
    Feature_HasVFP2 | 0, // VTOSIRS = 2688
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSIZD = 2689
    Feature_HasFullFP16 | 0, // VTOSIZH = 2690
    Feature_HasVFP2 | 0, // VTOSIZS = 2691
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSLD = 2692
    Feature_HasFullFP16 | 0, // VTOSLH = 2693
    Feature_HasVFP2 | 0, // VTOSLS = 2694
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUHD = 2695
    Feature_HasFullFP16 | 0, // VTOUHH = 2696
    Feature_HasVFP2 | 0, // VTOUHS = 2697
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUIRD = 2698
    Feature_HasFullFP16 | 0, // VTOUIRH = 2699
    Feature_HasVFP2 | 0, // VTOUIRS = 2700
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUIZD = 2701
    Feature_HasFullFP16 | 0, // VTOUIZH = 2702
    Feature_HasVFP2 | 0, // VTOUIZS = 2703
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOULD = 2704
    Feature_HasFullFP16 | 0, // VTOULH = 2705
    Feature_HasVFP2 | 0, // VTOULS = 2706
    Feature_HasNEON | 0, // VTRNd16 = 2707
    Feature_HasNEON | 0, // VTRNd32 = 2708
    Feature_HasNEON | 0, // VTRNd8 = 2709
    Feature_HasNEON | 0, // VTRNq16 = 2710
    Feature_HasNEON | 0, // VTRNq32 = 2711
    Feature_HasNEON | 0, // VTRNq8 = 2712
    Feature_HasNEON | 0, // VTSTv16i8 = 2713
    Feature_HasNEON | 0, // VTSTv2i32 = 2714
    Feature_HasNEON | 0, // VTSTv4i16 = 2715
    Feature_HasNEON | 0, // VTSTv4i32 = 2716
    Feature_HasNEON | 0, // VTSTv8i16 = 2717
    Feature_HasNEON | 0, // VTSTv8i8 = 2718
    Feature_HasDotProd | 0, // VUDOTD = 2719
    Feature_HasDotProd | 0, // VUDOTDI = 2720
    Feature_HasDotProd | 0, // VUDOTQ = 2721
    Feature_HasDotProd | 0, // VUDOTQI = 2722
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VUHTOD = 2723
    Feature_HasFullFP16 | 0, // VUHTOH = 2724
    Feature_HasVFP2 | 0, // VUHTOS = 2725
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VUITOD = 2726
    Feature_HasFullFP16 | 0, // VUITOH = 2727
    Feature_HasVFP2 | 0, // VUITOS = 2728
    Feature_HasVFP2 | Feature_HasDPVFP | 0, // VULTOD = 2729
    Feature_HasFullFP16 | 0, // VULTOH = 2730
    Feature_HasVFP2 | 0, // VULTOS = 2731
    Feature_HasNEON | 0, // VUZPd16 = 2732
    Feature_HasNEON | 0, // VUZPd8 = 2733
    Feature_HasNEON | 0, // VUZPq16 = 2734
    Feature_HasNEON | 0, // VUZPq32 = 2735
    Feature_HasNEON | 0, // VUZPq8 = 2736
    Feature_HasNEON | 0, // VZIPd16 = 2737
    Feature_HasNEON | 0, // VZIPd8 = 2738
    Feature_HasNEON | 0, // VZIPq16 = 2739
    Feature_HasNEON | 0, // VZIPq32 = 2740
    Feature_HasNEON | 0, // VZIPq8 = 2741
    Feature_IsARM | 0, // sysLDMDA = 2742
    Feature_IsARM | 0, // sysLDMDA_UPD = 2743
    Feature_IsARM | 0, // sysLDMDB = 2744
    Feature_IsARM | 0, // sysLDMDB_UPD = 2745
    Feature_IsARM | 0, // sysLDMIA = 2746
    Feature_IsARM | 0, // sysLDMIA_UPD = 2747
    Feature_IsARM | 0, // sysLDMIB = 2748
    Feature_IsARM | 0, // sysLDMIB_UPD = 2749
    Feature_IsARM | 0, // sysSTMDA = 2750
    Feature_IsARM | 0, // sysSTMDA_UPD = 2751
    Feature_IsARM | 0, // sysSTMDB = 2752
    Feature_IsARM | 0, // sysSTMDB_UPD = 2753
    Feature_IsARM | 0, // sysSTMIA = 2754
    Feature_IsARM | 0, // sysSTMIA_UPD = 2755
    Feature_IsARM | 0, // sysSTMIB = 2756
    Feature_IsARM | 0, // sysSTMIB_UPD = 2757
    Feature_IsThumb2 | 0, // t2ADCri = 2758
    Feature_IsThumb2 | 0, // t2ADCrr = 2759
    Feature_IsThumb2 | 0, // t2ADCrs = 2760
    Feature_IsThumb2 | 0, // t2ADDri = 2761
    Feature_IsThumb2 | 0, // t2ADDri12 = 2762
    Feature_IsThumb2 | 0, // t2ADDrr = 2763
    Feature_IsThumb2 | 0, // t2ADDrs = 2764
    Feature_IsThumb2 | 0, // t2ADR = 2765
    Feature_IsThumb2 | 0, // t2ANDri = 2766
    Feature_IsThumb2 | 0, // t2ANDrr = 2767
    Feature_IsThumb2 | 0, // t2ANDrs = 2768
    Feature_IsThumb2 | 0, // t2ASRri = 2769
    Feature_IsThumb2 | 0, // t2ASRrr = 2770
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2B = 2771
    Feature_IsThumb2 | 0, // t2BFC = 2772
    Feature_IsThumb2 | 0, // t2BFI = 2773
    Feature_IsThumb2 | 0, // t2BICri = 2774
    Feature_IsThumb2 | 0, // t2BICrr = 2775
    Feature_IsThumb2 | 0, // t2BICrs = 2776
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2BXJ = 2777
    Feature_IsThumb2 | 0, // t2Bcc = 2778
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2CDP = 2779
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2CDP2 = 2780
    Feature_IsThumb | Feature_HasV7Clrex | 0, // t2CLREX = 2781
    Feature_IsThumb2 | 0, // t2CLZ = 2782
    Feature_IsThumb2 | 0, // t2CMNri = 2783
    Feature_IsThumb2 | 0, // t2CMNzrr = 2784
    Feature_IsThumb2 | 0, // t2CMNzrs = 2785
    Feature_IsThumb2 | 0, // t2CMPri = 2786
    Feature_IsThumb2 | 0, // t2CMPrr = 2787
    Feature_IsThumb2 | 0, // t2CMPrs = 2788
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS1p = 2789
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS2p = 2790
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS3p = 2791
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32B = 2792
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CB = 2793
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CH = 2794
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CW = 2795
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32H = 2796
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32W = 2797
    Feature_IsThumb2 | 0, // t2DBG = 2798
    Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS1 = 2799
    Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS2 = 2800
    Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS3 = 2801
    Feature_IsThumb | Feature_HasDB | 0, // t2DMB = 2802
    Feature_IsThumb | Feature_HasDB | 0, // t2DSB = 2803
    Feature_IsThumb2 | 0, // t2EORri = 2804
    Feature_IsThumb2 | 0, // t2EORrr = 2805
    Feature_IsThumb2 | 0, // t2EORrs = 2806
    Feature_IsThumb2 | 0, // t2HINT = 2807
    Feature_IsThumb2 | Feature_HasVirtualization | 0, // t2HVC = 2808
    Feature_IsThumb | Feature_HasDB | 0, // t2ISB = 2809
    Feature_IsThumb2 | 0, // t2IT = 2810
    Feature_IsThumb2 | Feature_HasVFP2 | 0, // t2Int_eh_sjlj_setjmp = 2811
    Feature_IsThumb2 | 0, // t2Int_eh_sjlj_setjmp_nofp = 2812
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDA = 2813
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDAB = 2814
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEX = 2815
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEXB = 2816
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | Feature_IsNotMClass | 0, // t2LDAEXD = 2817
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEXH = 2818
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDAH = 2819
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_OFFSET = 2820
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_OPTION = 2821
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_POST = 2822
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_PRE = 2823
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_OFFSET = 2824
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_OPTION = 2825
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_POST = 2826
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_PRE = 2827
    Feature_IsThumb2 | 0, // t2LDCL_OFFSET = 2828
    Feature_IsThumb2 | 0, // t2LDCL_OPTION = 2829
    Feature_IsThumb2 | 0, // t2LDCL_POST = 2830
    Feature_IsThumb2 | 0, // t2LDCL_PRE = 2831
    Feature_IsThumb2 | 0, // t2LDC_OFFSET = 2832
    Feature_IsThumb2 | 0, // t2LDC_OPTION = 2833
    Feature_IsThumb2 | 0, // t2LDC_POST = 2834
    Feature_IsThumb2 | 0, // t2LDC_PRE = 2835
    Feature_IsThumb2 | 0, // t2LDMDB = 2836
    Feature_IsThumb2 | 0, // t2LDMDB_UPD = 2837
    Feature_IsThumb2 | 0, // t2LDMIA = 2838
    Feature_IsThumb2 | 0, // t2LDMIA_UPD = 2839
    Feature_IsThumb2 | 0, // t2LDRBT = 2840
    Feature_IsThumb2 | 0, // t2LDRB_POST = 2841
    Feature_IsThumb2 | 0, // t2LDRB_PRE = 2842
    Feature_IsThumb2 | 0, // t2LDRBi12 = 2843
    Feature_IsThumb2 | 0, // t2LDRBi8 = 2844
    Feature_IsThumb2 | 0, // t2LDRBpci = 2845
    Feature_IsThumb2 | 0, // t2LDRBs = 2846
    Feature_IsThumb2 | 0, // t2LDRD_POST = 2847
    Feature_IsThumb2 | 0, // t2LDRD_PRE = 2848
    Feature_IsThumb2 | 0, // t2LDRDi8 = 2849
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREX = 2850
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREXB = 2851
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2LDREXD = 2852
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREXH = 2853
    Feature_IsThumb2 | 0, // t2LDRHT = 2854
    Feature_IsThumb2 | 0, // t2LDRH_POST = 2855
    Feature_IsThumb2 | 0, // t2LDRH_PRE = 2856
    Feature_IsThumb2 | 0, // t2LDRHi12 = 2857
    Feature_IsThumb2 | 0, // t2LDRHi8 = 2858
    Feature_IsThumb2 | 0, // t2LDRHpci = 2859
    Feature_IsThumb2 | 0, // t2LDRHs = 2860
    Feature_IsThumb2 | 0, // t2LDRSBT = 2861
    Feature_IsThumb2 | 0, // t2LDRSB_POST = 2862
    Feature_IsThumb2 | 0, // t2LDRSB_PRE = 2863
    Feature_IsThumb2 | 0, // t2LDRSBi12 = 2864
    Feature_IsThumb2 | 0, // t2LDRSBi8 = 2865
    Feature_IsThumb2 | 0, // t2LDRSBpci = 2866
    Feature_IsThumb2 | 0, // t2LDRSBs = 2867
    Feature_IsThumb2 | 0, // t2LDRSHT = 2868
    Feature_IsThumb2 | 0, // t2LDRSH_POST = 2869
    Feature_IsThumb2 | 0, // t2LDRSH_PRE = 2870
    Feature_IsThumb2 | 0, // t2LDRSHi12 = 2871
    Feature_IsThumb2 | 0, // t2LDRSHi8 = 2872
    Feature_IsThumb2 | 0, // t2LDRSHpci = 2873
    Feature_IsThumb2 | 0, // t2LDRSHs = 2874
    Feature_IsThumb2 | 0, // t2LDRT = 2875
    Feature_IsThumb2 | 0, // t2LDR_POST = 2876
    Feature_IsThumb2 | 0, // t2LDR_PRE = 2877
    Feature_IsThumb2 | 0, // t2LDRi12 = 2878
    Feature_IsThumb2 | 0, // t2LDRi8 = 2879
    Feature_IsThumb2 | 0, // t2LDRpci = 2880
    Feature_IsThumb2 | 0, // t2LDRs = 2881
    Feature_IsThumb2 | 0, // t2LSLri = 2882
    Feature_IsThumb2 | 0, // t2LSLrr = 2883
    Feature_IsThumb2 | 0, // t2LSRri = 2884
    Feature_IsThumb2 | 0, // t2LSRrr = 2885
    Feature_IsThumb2 | 0, // t2MCR = 2886
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2MCR2 = 2887
    Feature_IsThumb2 | 0, // t2MCRR = 2888
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2MCRR2 = 2889
    Feature_IsThumb2 | 0, // t2MLA = 2890
    Feature_IsThumb2 | 0, // t2MLS = 2891
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVTi16 = 2892
    Feature_IsThumb2 | 0, // t2MOVi = 2893
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVi16 = 2894
    Feature_IsThumb2 | 0, // t2MOVr = 2895
    Feature_IsThumb2 | 0, // t2MOVsra_flag = 2896
    Feature_IsThumb2 | 0, // t2MOVsrl_flag = 2897
    Feature_IsThumb2 | 0, // t2MRC = 2898
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2MRC2 = 2899
    Feature_IsThumb2 | 0, // t2MRRC = 2900
    Feature_IsThumb2 | Feature_PreV8 | 0, // t2MRRC2 = 2901
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MRS_AR = 2902
    Feature_IsThumb | Feature_IsMClass | 0, // t2MRS_M = 2903
    Feature_IsThumb | Feature_HasVirtualization | 0, // t2MRSbanked = 2904
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MRSsys_AR = 2905
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MSR_AR = 2906
    Feature_IsThumb | Feature_IsMClass | 0, // t2MSR_M = 2907
    Feature_IsThumb | Feature_HasVirtualization | 0, // t2MSRbanked = 2908
    Feature_IsThumb2 | 0, // t2MUL = 2909
    Feature_IsThumb2 | 0, // t2MVNi = 2910
    Feature_IsThumb2 | 0, // t2MVNr = 2911
    Feature_IsThumb2 | 0, // t2MVNs = 2912
    Feature_IsThumb2 | 0, // t2ORNri = 2913
    Feature_IsThumb2 | 0, // t2ORNrr = 2914
    Feature_IsThumb2 | 0, // t2ORNrs = 2915
    Feature_IsThumb2 | 0, // t2ORRri = 2916
    Feature_IsThumb2 | 0, // t2ORRrr = 2917
    Feature_IsThumb2 | 0, // t2ORRrs = 2918
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2PKHBT = 2919
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2PKHTB = 2920
    Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWi12 = 2921
    Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWi8 = 2922
    Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWs = 2923
    Feature_IsThumb2 | 0, // t2PLDi12 = 2924
    Feature_IsThumb2 | 0, // t2PLDi8 = 2925
    Feature_IsThumb2 | 0, // t2PLDpci = 2926
    Feature_IsThumb2 | 0, // t2PLDs = 2927
    Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIi12 = 2928
    Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIi8 = 2929
    Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIpci = 2930
    Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIs = 2931
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD = 2932
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD16 = 2933
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD8 = 2934
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QASX = 2935
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QDADD = 2936
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QDSUB = 2937
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSAX = 2938
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB = 2939
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB16 = 2940
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB8 = 2941
    Feature_IsThumb2 | 0, // t2RBIT = 2942
    Feature_IsThumb2 | 0, // t2REV = 2943
    Feature_IsThumb2 | 0, // t2REV16 = 2944
    Feature_IsThumb2 | 0, // t2REVSH = 2945
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEDB = 2946
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEDBW = 2947
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEIA = 2948
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEIAW = 2949
    Feature_IsThumb2 | 0, // t2RORri = 2950
    Feature_IsThumb2 | 0, // t2RORrr = 2951
    Feature_IsThumb2 | 0, // t2RRX = 2952
    Feature_IsThumb2 | 0, // t2RSBri = 2953
    Feature_IsThumb2 | 0, // t2RSBrr = 2954
    Feature_IsThumb2 | 0, // t2RSBrs = 2955
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SADD16 = 2956
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SADD8 = 2957
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SASX = 2958
    Feature_IsThumb2 | 0, // t2SBCri = 2959
    Feature_IsThumb2 | 0, // t2SBCrr = 2960
    Feature_IsThumb2 | 0, // t2SBCrs = 2961
    Feature_IsThumb2 | 0, // t2SBFX = 2962
    Feature_HasDivideInThumb | Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2SDIV = 2963
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SEL = 2964
    Feature_IsThumb2 | Feature_HasV8 | Feature_HasV8_1a | 0, // t2SETPAN = 2965
    Feature_Has8MSecExt | 0, // t2SG = 2966
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHADD16 = 2967
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHADD8 = 2968
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHASX = 2969
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSAX = 2970
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSUB16 = 2971
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSUB8 = 2972
    Feature_IsThumb2 | Feature_HasTrustZone | 0, // t2SMC = 2973
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLABB = 2974
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLABT = 2975
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAD = 2976
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLADX = 2977
    Feature_IsThumb2 | 0, // t2SMLAL = 2978
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALBB = 2979
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALBT = 2980
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALD = 2981
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALDX = 2982
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALTB = 2983
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALTT = 2984
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLATB = 2985
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLATT = 2986
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAWB = 2987
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAWT = 2988
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSD = 2989
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSDX = 2990
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSLD = 2991
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSLDX = 2992
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLA = 2993
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLAR = 2994
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLS = 2995
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLSR = 2996
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMUL = 2997
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMULR = 2998
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUAD = 2999
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUADX = 3000
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULBB = 3001
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULBT = 3002
    Feature_IsThumb2 | 0, // t2SMULL = 3003
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULTB = 3004
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULTT = 3005
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULWB = 3006
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULWT = 3007
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUSD = 3008
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUSDX = 3009
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSDB = 3010
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSDB_UPD = 3011
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSIA = 3012
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSIA_UPD = 3013
    Feature_IsThumb2 | 0, // t2SSAT = 3014
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSAT16 = 3015
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSAX = 3016
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSUB16 = 3017
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSUB8 = 3018
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_OFFSET = 3019
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_OPTION = 3020
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_POST = 3021
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_PRE = 3022
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_OFFSET = 3023
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_OPTION = 3024
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_POST = 3025
    Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_PRE = 3026
    Feature_IsThumb2 | 0, // t2STCL_OFFSET = 3027
    Feature_IsThumb2 | 0, // t2STCL_OPTION = 3028
    Feature_IsThumb2 | 0, // t2STCL_POST = 3029
    Feature_IsThumb2 | 0, // t2STCL_PRE = 3030
    Feature_IsThumb2 | 0, // t2STC_OFFSET = 3031
    Feature_IsThumb2 | 0, // t2STC_OPTION = 3032
    Feature_IsThumb2 | 0, // t2STC_POST = 3033
    Feature_IsThumb2 | 0, // t2STC_PRE = 3034
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STL = 3035
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STLB = 3036
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEX = 3037
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEXB = 3038
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | Feature_IsNotMClass | 0, // t2STLEXD = 3039
    Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEXH = 3040
    Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STLH = 3041
    Feature_IsThumb2 | 0, // t2STMDB = 3042
    Feature_IsThumb2 | 0, // t2STMDB_UPD = 3043
    Feature_IsThumb2 | 0, // t2STMIA = 3044
    Feature_IsThumb2 | 0, // t2STMIA_UPD = 3045
    Feature_IsThumb2 | 0, // t2STRBT = 3046
    Feature_IsThumb2 | 0, // t2STRB_POST = 3047
    Feature_IsThumb2 | 0, // t2STRB_PRE = 3048
    Feature_IsThumb2 | 0, // t2STRBi12 = 3049
    Feature_IsThumb2 | 0, // t2STRBi8 = 3050
    Feature_IsThumb2 | 0, // t2STRBs = 3051
    Feature_IsThumb2 | 0, // t2STRD_POST = 3052
    Feature_IsThumb2 | 0, // t2STRD_PRE = 3053
    Feature_IsThumb2 | 0, // t2STRDi8 = 3054
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREX = 3055
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREXB = 3056
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2STREXD = 3057
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREXH = 3058
    Feature_IsThumb2 | 0, // t2STRHT = 3059
    Feature_IsThumb2 | 0, // t2STRH_POST = 3060
    Feature_IsThumb2 | 0, // t2STRH_PRE = 3061
    Feature_IsThumb2 | 0, // t2STRHi12 = 3062
    Feature_IsThumb2 | 0, // t2STRHi8 = 3063
    Feature_IsThumb2 | 0, // t2STRHs = 3064
    Feature_IsThumb2 | 0, // t2STRT = 3065
    Feature_IsThumb2 | 0, // t2STR_POST = 3066
    Feature_IsThumb2 | 0, // t2STR_PRE = 3067
    Feature_IsThumb2 | 0, // t2STRi12 = 3068
    Feature_IsThumb2 | 0, // t2STRi8 = 3069
    Feature_IsThumb2 | 0, // t2STRs = 3070
    Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SUBS_PC_LR = 3071
    Feature_IsThumb2 | 0, // t2SUBri = 3072
    Feature_IsThumb2 | 0, // t2SUBri12 = 3073
    Feature_IsThumb2 | 0, // t2SUBrr = 3074
    Feature_IsThumb2 | 0, // t2SUBrs = 3075
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAB = 3076
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAB16 = 3077
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAH = 3078
    Feature_IsThumb2 | 0, // t2SXTB = 3079
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTB16 = 3080
    Feature_IsThumb2 | 0, // t2SXTH = 3081
    Feature_IsThumb2 | 0, // t2TBB = 3082
    Feature_IsThumb2 | 0, // t2TBH = 3083
    Feature_IsThumb2 | 0, // t2TEQri = 3084
    Feature_IsThumb2 | 0, // t2TEQrr = 3085
    Feature_IsThumb2 | 0, // t2TEQrs = 3086
    Feature_IsThumb | Feature_HasV8_4a | 0, // t2TSB = 3087
    Feature_IsThumb2 | 0, // t2TSTri = 3088
    Feature_IsThumb2 | 0, // t2TSTrr = 3089
    Feature_IsThumb2 | 0, // t2TSTrs = 3090
    Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TT = 3091
    Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTA = 3092
    Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTAT = 3093
    Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTT = 3094
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UADD16 = 3095
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UADD8 = 3096
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UASX = 3097
    Feature_IsThumb2 | 0, // t2UBFX = 3098
    Feature_IsThumb2 | 0, // t2UDF = 3099
    Feature_HasDivideInThumb | Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2UDIV = 3100
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHADD16 = 3101
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHADD8 = 3102
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHASX = 3103
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSAX = 3104
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSUB16 = 3105
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSUB8 = 3106
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UMAAL = 3107
    Feature_IsThumb2 | 0, // t2UMLAL = 3108
    Feature_IsThumb2 | 0, // t2UMULL = 3109
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQADD16 = 3110
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQADD8 = 3111
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQASX = 3112
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSAX = 3113
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSUB16 = 3114
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSUB8 = 3115
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAD8 = 3116
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USADA8 = 3117
    Feature_IsThumb2 | 0, // t2USAT = 3118
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAT16 = 3119
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAX = 3120
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USUB16 = 3121
    Feature_IsThumb2 | Feature_HasDSP | 0, // t2USUB8 = 3122
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAB = 3123
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAB16 = 3124
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAH = 3125
    Feature_IsThumb2 | 0, // t2UXTB = 3126
    Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTB16 = 3127
    Feature_IsThumb2 | 0, // t2UXTH = 3128
    Feature_IsThumb | 0, // tADC = 3129
    Feature_IsThumb | 0, // tADDhirr = 3130
    Feature_IsThumb | 0, // tADDi3 = 3131
    Feature_IsThumb | 0, // tADDi8 = 3132
    Feature_IsThumb | 0, // tADDrSP = 3133
    Feature_IsThumb | 0, // tADDrSPi = 3134
    Feature_IsThumb | 0, // tADDrr = 3135
    Feature_IsThumb | 0, // tADDspi = 3136
    Feature_IsThumb | 0, // tADDspr = 3137
    Feature_IsThumb | 0, // tADR = 3138
    Feature_IsThumb | 0, // tAND = 3139
    Feature_IsThumb | 0, // tASRri = 3140
    Feature_IsThumb | 0, // tASRrr = 3141
    Feature_IsThumb | 0, // tB = 3142
    Feature_IsThumb | 0, // tBIC = 3143
    Feature_IsThumb | 0, // tBKPT = 3144
    Feature_IsThumb | 0, // tBL = 3145
    Feature_IsThumb | Feature_Has8MSecExt | 0, // tBLXNSr = 3146
    Feature_IsThumb | Feature_HasV5T | Feature_IsNotMClass | 0, // tBLXi = 3147
    Feature_IsThumb | Feature_HasV5T | 0, // tBLXr = 3148
    Feature_IsThumb | 0, // tBX = 3149
    Feature_IsThumb | Feature_Has8MSecExt | 0, // tBXNS = 3150
    Feature_IsThumb | 0, // tBcc = 3151
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // tCBNZ = 3152
    Feature_IsThumb | Feature_HasV8MBaseline | 0, // tCBZ = 3153
    Feature_IsThumb | 0, // tCMNz = 3154
    Feature_IsThumb | 0, // tCMPhir = 3155
    Feature_IsThumb | 0, // tCMPi8 = 3156
    Feature_IsThumb | 0, // tCMPr = 3157
    Feature_IsThumb | 0, // tCPS = 3158
    Feature_IsThumb | 0, // tEOR = 3159
    Feature_IsThumb | Feature_HasV6M | 0, // tHINT = 3160
    Feature_IsThumb | Feature_HasV8 | 0, // tHLT = 3161
    Feature_IsThumb | 0, // tInt_WIN_eh_sjlj_longjmp = 3162
    Feature_IsThumb | 0, // tInt_eh_sjlj_longjmp = 3163
    Feature_IsThumb | 0, // tInt_eh_sjlj_setjmp = 3164
    Feature_IsThumb | 0, // tLDMIA = 3165
    Feature_IsThumb | 0, // tLDRBi = 3166
    Feature_IsThumb | 0, // tLDRBr = 3167
    Feature_IsThumb | 0, // tLDRHi = 3168
    Feature_IsThumb | 0, // tLDRHr = 3169
    Feature_IsThumb | 0, // tLDRSB = 3170
    Feature_IsThumb | 0, // tLDRSH = 3171
    Feature_IsThumb | 0, // tLDRi = 3172
    Feature_IsThumb | 0, // tLDRpci = 3173
    Feature_IsThumb | 0, // tLDRr = 3174
    Feature_IsThumb | 0, // tLDRspi = 3175
    Feature_IsThumb | 0, // tLSLri = 3176
    Feature_IsThumb | 0, // tLSLrr = 3177
    Feature_IsThumb | 0, // tLSRri = 3178
    Feature_IsThumb | 0, // tLSRrr = 3179
    Feature_IsThumb | 0, // tMOVSr = 3180
    Feature_IsThumb | 0, // tMOVi8 = 3181
    Feature_IsThumb | 0, // tMOVr = 3182
    Feature_IsThumb | 0, // tMUL = 3183
    Feature_IsThumb | 0, // tMVN = 3184
    Feature_IsThumb | 0, // tORR = 3185
    Feature_IsThumb | 0, // tPICADD = 3186
    Feature_IsThumb | 0, // tPOP = 3187
    Feature_IsThumb | 0, // tPUSH = 3188
    Feature_IsThumb | Feature_HasV6 | 0, // tREV = 3189
    Feature_IsThumb | Feature_HasV6 | 0, // tREV16 = 3190
    Feature_IsThumb | Feature_HasV6 | 0, // tREVSH = 3191
    Feature_IsThumb | 0, // tROR = 3192
    Feature_IsThumb | 0, // tRSB = 3193
    Feature_IsThumb | 0, // tSBC = 3194
    Feature_IsThumb | Feature_IsNotMClass | 0, // tSETEND = 3195
    Feature_IsThumb | 0, // tSTMIA_UPD = 3196
    Feature_IsThumb | 0, // tSTRBi = 3197
    Feature_IsThumb | 0, // tSTRBr = 3198
    Feature_IsThumb | 0, // tSTRHi = 3199
    Feature_IsThumb | 0, // tSTRHr = 3200
    Feature_IsThumb | 0, // tSTRi = 3201
    Feature_IsThumb | 0, // tSTRr = 3202
    Feature_IsThumb | 0, // tSTRspi = 3203
    Feature_IsThumb | 0, // tSUBi3 = 3204
    Feature_IsThumb | 0, // tSUBi8 = 3205
    Feature_IsThumb | 0, // tSUBrr = 3206
    Feature_IsThumb | 0, // tSUBspi = 3207
    Feature_IsThumb | 0, // tSVC = 3208
    Feature_IsThumb | Feature_HasV6 | 0, // tSXTB = 3209
    Feature_IsThumb | Feature_HasV6 | 0, // tSXTH = 3210
    Feature_IsThumb | 0, // tTRAP = 3211
    Feature_IsThumb | 0, // tTST = 3212
    Feature_IsThumb | 0, // tUDF = 3213
    Feature_IsThumb | Feature_HasV6 | 0, // tUXTB = 3214
    Feature_IsThumb | Feature_HasV6 | 0, // tUXTH = 3215
    Feature_IsThumb | 0, // t__brkdiv0 = 3216
  };

  assert(Inst.getOpcode() < 3217);
  uint64_t MissingFeatures =
      (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^
      RequiredFeatures[Inst.getOpcode()];
  if (MissingFeatures) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
        << " instruction but the ";
    for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i)
      if (MissingFeatures & (1ULL << i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str());
  }
#else
// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
(void)MCII;
#endif // NDEBUG
}
#endif