// Copyright 2016, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

{
  "mnemonics": [
    "Adc",  // ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Add",  // ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "And",  // AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Bic",  // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Eor",  // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Orr",  // ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Rsb",  // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Rsc",  // RSC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Sbc",  // SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Sub",  // SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
    "Subs"  // SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
  ],
  "description": {
    "operands": [
      {
        "name": "cond",
        "type": "Condition"
      },
      {
        "name": "rd",
        "type": "AllRegisters"
      },
      {
        "name": "rn",
        "type": "AllRegisters"
      },
      {
        "name": "op",
        "wrapper": "Operand",
        "operands": [
          {
            "name": "rm",
            "type": "AllRegisters"
          },
          {
            "name": "shift",
            "type": "Shift"
          },
          {
            "name": "rs",
            "type": "AllRegisters"
          }
        ]
      }
    ],
    "inputs": [
      {
        "name": "apsr",
        "type": "NZCV"
      },
      {
        "name": "rd",
        "type": "Register"
      },
      {
        "name": "rn",
        "type": "Register"
      },
      {
        "name": "rm",
        "type": "Register"
      },
      {
        "name": "rs",
        "type": "RegisterShift"
      }
    ]
  },
  "test-files": [
    {
      "type": "assembler",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn", "rm", "shift", "rs"
          ],
          "operand-limit": 1000,
          "operand-filter": "(rd != 'r15') and (rn != 'r15') and (rm != 'r15') and (rs != 'r15')"
        }
      ]
    },
    {
      "type": "assembler-negative",
      "test-cases": [
        {
          "name": "Operands",
          "operands": [
            "cond", "rd", "rn", "rm", "shift", "rs"
          ],
          "operand-limit": 1000,
          "operand-filter": "(rd == 'r15') or (rn == 'r15') or (rm == 'r15') or (rs == 'r15')"
        }
      ]
    },
    {
      "type": "simulator",
      "test-cases": [
        {
          "name": "Condition",
          "operands": [
            "cond"
          ],
          "inputs": [
            "apsr"
          ]
        },
        // Test combinations of registers values with rd == rn.
        {
          "name": "RdIsRn",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd == rn and rn != rm",
          "operand-limit": 10,
          "input-filter": "rd == rn",
          "input-limit": 200
        },
        // Test combinations of registers values with rd == rm.
        {
          "name": "RdIsRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd == rm and rn != rm",
          "operand-limit": 10,
          "input-filter": "rd == rm",
          "input-limit": 200
        },
        // Test combinations of registers values.
        {
          "name": "RdIsNotRnIsNotRm",
          "operands": [
            "rd", "rn", "rm"
          ],
          "inputs": [
            "rd", "rn", "rm"
          ],
          "operand-filter": "rd != rn != rm",
          "operand-limit": 10,
          "input-limit": 200
        },
        // Test combinations of shift types and register values.
        {
          "name": "ShiftTypes",
          "operands": [
            "rm", "shift", "rs"
          ],
          "inputs": [
            "rm", "rs"
          ],
          "operand-filter": "rm == 'r1' and rs == 'r2'"
        }
      ]
    }
  ]
}