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Searched defs:RC (Results 1 – 25 of 509) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp93 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
121 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
129 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
277 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
284 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
285 -> BT::RegisterCell { in evaluate()
294 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
329 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
345 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
352 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
219 -> BT::RegisterCell { in evaluate()
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
279 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
300 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
309 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h74 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
90 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
97 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
107 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
123 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
131 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
DTargetRegisterInfo.h110 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
115 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
122 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
127 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
314 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
320 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
326 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
331 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
340 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
344 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const { in legalclasstypes_end()
[all …]
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DIRBuilder.h503 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
516 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
523 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
536 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
543 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
556 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
563 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
575 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
586 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
592 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp41 const TargetRegisterClass *RC = in getGlobalBaseReg() local
58 const TargetRegisterClass *RC = in createEhDataRegsFI() local
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI() local
96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
356 const TargetRegisterClass *RC = in expandExtractElementF64() local
395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
695 const TargetRegisterClass *RC = in emitEpilogue() local
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp81 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
98 static unsigned getGetLocalOpcode(const TargetRegisterClass *RC) { in getGetLocalOpcode()
115 static unsigned getSetLocalOpcode(const TargetRegisterClass *RC) { in getSetLocalOpcode()
132 static unsigned getTeeLocalOpcode(const TargetRegisterClass *RC) { in getTeeLocalOpcode()
149 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
239 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
272 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
340 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp39 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
57 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
70 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm/include/llvm/IR/
DIRBuilder.h781 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
795 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
803 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
817 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
825 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
839 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
847 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
859 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
871 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
878 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterClassInfo.h64 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
80 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
87 ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const { in getOrder()
97 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
DLiveStackAnalysis.cpp55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterBankEmitter.cpp73 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
171 CodeGenRegBank &RegisterClassHierarchy, const CodeGenRegisterClass *RC, in visitRegisterBankClasses()
223 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
230 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
246 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation() local
289 for (const CodeGenRegisterClass *RC : in run() local
293 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp162 const TargetRegisterClass *RC) { in inClass()
175 const TargetRegisterClass *RC, in storeRegToStackSlot()
212 const TargetRegisterClass *RC, in storeRegToAddr()
222 const TargetRegisterClass *RC, in loadRegFromStackSlot()
253 const TargetRegisterClass *RC, in loadRegFromAddr()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp58 const TargetRegisterClass &RC = in createEhDataRegsFI() local
73 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
97 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp174 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
189 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
232 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
265 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
318 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
384 const TargetRegisterClass *RC = in expandExtractElementF64() local
422 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
720 const TargetRegisterClass *RC = in emitEpilogue() local
835 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h142 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
148 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
155 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
383 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
396 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, in canCombineSubRegIndices()
482 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
491 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
500 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
512 getRawAllocationOrder(const TargetRegisterClass *RC, in getRawAllocationOrder()
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DRegisterInfoEmitter.cpp340 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
455 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetHeader() local
503 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
514 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
548 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
561 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
592 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
604 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
620 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
[all …]
/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLiveStacks.cpp58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp463 const TargetRegisterClass *RC, in PPCEmitLoad()
609 const TargetRegisterClass *RC = in SelectLoad() local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
988 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1095 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1184 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1346 const TargetRegisterClass *RC = in processCallArgs() local
1358 const TargetRegisterClass *RC = in processCallArgs() local
1675 const TargetRegisterClass *RC = in SelectRet() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp466 const TargetRegisterClass *RC, in PPCEmitLoad()
623 const TargetRegisterClass *RC = in SelectLoad() local
640 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
1047 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1126 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1170 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1271 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1433 const TargetRegisterClass *RC = in processCallArgs() local
1445 const TargetRegisterClass *RC = in processCallArgs() local
1762 const TargetRegisterClass *RC = in SelectRet() local
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local

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