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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4  */
5 
6 #ifndef _ARCH_IRQ_H_
7 #define _ARCH_IRQ_H_
8 
9 #include <dt-bindings/interrupt-router/intel-irq.h>
10 
11 /**
12  * Intel interrupt router configuration mechanism
13  *
14  * There are two known ways of Intel interrupt router configuration mechanism
15  * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
16  * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
17  * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
18  * in the IBASE register block where IBASE is memory-mapped.
19  */
20 enum pirq_config {
21 	PIRQ_VIA_PCI,
22 	PIRQ_VIA_IBASE
23 };
24 
25 struct pirq_regmap {
26 	int link;
27 	int offset;
28 };
29 
30 /**
31  * Intel interrupt router control block
32  *
33  * Its members' value will be filled in based on device tree's input.
34  *
35  * @config:	PIRQ_VIA_PCI or PIRQ_VIA_IBASE
36  * @link_base:	link value base number
37  * @link_num:	number of PIRQ links supported
38  * @has_regmap:	has mapping table between PIRQ link and routing register offset
39  * @irq_mask:	IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
40  *		IRQ N is available to be routed
41  * @lb_bdf:	irq router's PCI bus/device/function number encoding
42  * @ibase:	IBASE register block base address
43  * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
44  * @actl_addr:	ACTL register offset
45  */
46 struct irq_router {
47 	int config;
48 	u32 link_base;
49 	int link_num;
50 	bool has_regmap;
51 	struct pirq_regmap *regmap;
52 	u16 irq_mask;
53 	u32 bdf;
54 	u32 ibase;
55 	bool actl_8bit;
56 	int actl_addr;
57 };
58 
59 struct pirq_routing {
60 	int bdf;
61 	int pin;
62 	int pirq;
63 };
64 
65 #define PIRQ_BITMAP		0xdef8
66 
67 #endif /* _ARCH_IRQ_H_ */
68