1 /* 2 * Copyright © 2014 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 **************************************************************************************************** 29 * @file addrlib.h 30 * @brief Contains the Addr::Lib base class definition. 31 **************************************************************************************************** 32 */ 33 34 #ifndef __ADDR_LIB_H__ 35 #define __ADDR_LIB_H__ 36 37 #include "addrinterface.h" 38 #include "addrobject.h" 39 #include "addrelemlib.h" 40 41 #include "amdgpu_asic_addr.h" 42 43 #ifndef CIASICIDGFXENGINE_R600 44 #define CIASICIDGFXENGINE_R600 0x00000006 45 #endif 46 47 #ifndef CIASICIDGFXENGINE_R800 48 #define CIASICIDGFXENGINE_R800 0x00000008 49 #endif 50 51 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND 52 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A 53 #endif 54 55 #ifndef CIASICIDGFXENGINE_ARCTICISLAND 56 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D 57 #endif 58 59 namespace Addr 60 { 61 62 /** 63 **************************************************************************************************** 64 * @brief Neutral enums that define pipeinterleave 65 **************************************************************************************************** 66 */ 67 enum PipeInterleave 68 { 69 ADDR_PIPEINTERLEAVE_256B = 256, 70 ADDR_PIPEINTERLEAVE_512B = 512, 71 ADDR_PIPEINTERLEAVE_1KB = 1024, 72 ADDR_PIPEINTERLEAVE_2KB = 2048, 73 }; 74 75 /** 76 **************************************************************************************************** 77 * @brief Neutral enums that define DRAM row size 78 **************************************************************************************************** 79 */ 80 enum RowSize 81 { 82 ADDR_ROWSIZE_1KB = 1024, 83 ADDR_ROWSIZE_2KB = 2048, 84 ADDR_ROWSIZE_4KB = 4096, 85 ADDR_ROWSIZE_8KB = 8192, 86 }; 87 88 /** 89 **************************************************************************************************** 90 * @brief Neutral enums that define bank interleave 91 **************************************************************************************************** 92 */ 93 enum BankInterleave 94 { 95 ADDR_BANKINTERLEAVE_1 = 1, 96 ADDR_BANKINTERLEAVE_2 = 2, 97 ADDR_BANKINTERLEAVE_4 = 4, 98 ADDR_BANKINTERLEAVE_8 = 8, 99 }; 100 101 /** 102 **************************************************************************************************** 103 * @brief Neutral enums that define shader engine tile size 104 **************************************************************************************************** 105 */ 106 enum ShaderEngineTileSize 107 { 108 ADDR_SE_TILESIZE_16 = 16, 109 ADDR_SE_TILESIZE_32 = 32, 110 }; 111 112 /** 113 **************************************************************************************************** 114 * @brief Neutral enums that define bank swap size 115 **************************************************************************************************** 116 */ 117 enum BankSwapSize 118 { 119 ADDR_BANKSWAP_128B = 128, 120 ADDR_BANKSWAP_256B = 256, 121 ADDR_BANKSWAP_512B = 512, 122 ADDR_BANKSWAP_1KB = 1024, 123 }; 124 125 /** 126 **************************************************************************************************** 127 * @brief Enums that define max compressed fragments config 128 **************************************************************************************************** 129 */ 130 enum NumMaxCompressedFragmentsConfig 131 { 132 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 133 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 134 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 135 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 136 }; 137 138 /** 139 **************************************************************************************************** 140 * @brief Enums that define num pipes config 141 **************************************************************************************************** 142 */ 143 enum NumPipesConfig 144 { 145 ADDR_CONFIG_1_PIPE = 0x00000000, 146 ADDR_CONFIG_2_PIPE = 0x00000001, 147 ADDR_CONFIG_4_PIPE = 0x00000002, 148 ADDR_CONFIG_8_PIPE = 0x00000003, 149 ADDR_CONFIG_16_PIPE = 0x00000004, 150 ADDR_CONFIG_32_PIPE = 0x00000005, 151 ADDR_CONFIG_64_PIPE = 0x00000006, 152 }; 153 154 /** 155 **************************************************************************************************** 156 * @brief Enums that define num banks config 157 **************************************************************************************************** 158 */ 159 enum NumBanksConfig 160 { 161 ADDR_CONFIG_1_BANK = 0x00000000, 162 ADDR_CONFIG_2_BANK = 0x00000001, 163 ADDR_CONFIG_4_BANK = 0x00000002, 164 ADDR_CONFIG_8_BANK = 0x00000003, 165 ADDR_CONFIG_16_BANK = 0x00000004, 166 }; 167 168 /** 169 **************************************************************************************************** 170 * @brief Enums that define num rb per shader engine config 171 **************************************************************************************************** 172 */ 173 enum NumRbPerShaderEngineConfig 174 { 175 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 176 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 177 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 178 }; 179 180 /** 181 **************************************************************************************************** 182 * @brief Enums that define num shader engines config 183 **************************************************************************************************** 184 */ 185 enum NumShaderEnginesConfig 186 { 187 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 188 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 189 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 190 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 191 }; 192 193 /** 194 **************************************************************************************************** 195 * @brief Enums that define pipe interleave size config 196 **************************************************************************************************** 197 */ 198 enum PipeInterleaveSizeConfig 199 { 200 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 201 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 202 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 203 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 204 }; 205 206 /** 207 **************************************************************************************************** 208 * @brief Enums that define row size config 209 **************************************************************************************************** 210 */ 211 enum RowSizeConfig 212 { 213 ADDR_CONFIG_1KB_ROW = 0x00000000, 214 ADDR_CONFIG_2KB_ROW = 0x00000001, 215 ADDR_CONFIG_4KB_ROW = 0x00000002, 216 }; 217 218 /** 219 **************************************************************************************************** 220 * @brief Enums that define bank interleave size config 221 **************************************************************************************************** 222 */ 223 enum BankInterleaveSizeConfig 224 { 225 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 226 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 227 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 228 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 229 }; 230 231 /** 232 **************************************************************************************************** 233 * @brief Enums that define engine tile size config 234 **************************************************************************************************** 235 */ 236 enum ShaderEngineTileSizeConfig 237 { 238 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 239 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 240 }; 241 242 /** 243 **************************************************************************************************** 244 * @brief This class contains asic independent address lib functionalities 245 **************************************************************************************************** 246 */ 247 class Lib : public Object 248 { 249 public: 250 virtual ~Lib(); 251 252 static ADDR_E_RETURNCODE Create( 253 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut); 254 255 /// Pair of Create Destroy()256 VOID Destroy() 257 { 258 delete this; 259 } 260 261 static Lib* GetLib(ADDR_HANDLE hLib); 262 263 /// Returns AddrLib version (from compiled binary instead include file) GetVersion()264 UINT_32 GetVersion() 265 { 266 return m_version; 267 } 268 269 /// Returns asic chip family name defined by AddrLib GetChipFamily()270 ChipFamily GetChipFamily() 271 { 272 return m_chipFamily; 273 } 274 275 ADDR_E_RETURNCODE Flt32ToDepthPixel( 276 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 277 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const; 278 279 ADDR_E_RETURNCODE Flt32ToColorPixel( 280 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 281 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const; 282 283 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const; 284 285 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 286 287 protected: 288 Lib(); // Constructor is protected 289 Lib(const Client* pClient); 290 291 /// Pure virtual function to get max alignments 292 virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const = 0; 293 294 // 295 // Initialization 296 // 297 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers 298 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0; 299 300 /// Pure Virtual function for Hwl converting chip family 301 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0; 302 303 /// Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)304 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 305 { 306 *ppEquationTable = NULL; 307 308 return 0; 309 } 310 311 // 312 // Misc helper 313 // 314 static UINT_32 Bits2Number(UINT_32 bitNum, ...); 315 GetNumFragments(UINT_32 numSamples,UINT_32 numFrags)316 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags) 317 { 318 return (numFrags != 0) ? numFrags : Max(1u, numSamples); 319 } 320 321 /// Returns pointer of ElemLib GetElemLib()322 ElemLib* GetElemLib() const 323 { 324 return m_pElemLib; 325 } 326 327 /// Returns fillSizeFields flag GetFillSizeFieldsFlags()328 UINT_32 GetFillSizeFieldsFlags() const 329 { 330 return m_configFlags.fillSizeFields; 331 } 332 333 private: 334 // Disallow the copy constructor 335 Lib(const Lib& a); 336 337 // Disallow the assignment operator 338 Lib& operator=(const Lib& a); 339 340 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 341 342 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels); 343 344 protected: 345 LibClass m_class; ///< Store class type (HWL type) 346 347 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h 348 349 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h 350 351 UINT_32 m_version; ///< Current version 352 353 // 354 // Global parameters 355 // 356 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by 357 /// AddrLib instead of Client except forceLinearAligned 358 359 UINT_32 m_pipes; ///< Number of pipes 360 UINT_32 m_banks; ///< Number of banks 361 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK 362 /// Keep it here to do default parameter calculation 363 364 UINT_32 m_pipeInterleaveBytes; 365 ///< Specifies the size of contiguous address space 366 /// within each tiling pipe when making linear 367 /// accesses. (Formerly Group Size) 368 369 UINT_32 m_rowSize; ///< DRAM row size, in bytes 370 371 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels 372 UINT_32 m_maxSamples; ///< Max numSamples 373 private: 374 ElemLib* m_pElemLib; ///< Element Lib pointer 375 }; 376 377 Lib* SiHwlInit (const Client* pClient); 378 Lib* CiHwlInit (const Client* pClient); 379 Lib* Gfx9HwlInit (const Client* pClient); 380 381 } // Addr 382 383 #endif 384