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1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
11 // a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef SPU_ISELLOWERING_H
16 #define SPU_ISELLOWERING_H
17 
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "SPU.h"
21 
22 namespace llvm {
23   namespace SPUISD {
24     enum NodeType {
25       // Start the numbering where the builting ops and target ops leave off.
26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 
28       // Pseudo instructions:
29       RET_FLAG,                 ///< Return with flag, matched by bi instruction
30 
31       Hi,                       ///< High address component (upper 16)
32       Lo,                       ///< Low address component (lower 16)
33       PCRelAddr,                ///< Program counter relative address
34       AFormAddr,                ///< A-form address (local store)
35       IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
36 
37       LDRESULT,                 ///< Load result (value, chain)
38       CALL,                     ///< CALL instruction
39       SHUFB,                    ///< Vector shuffle (permute)
40       SHUFFLE_MASK,             ///< Shuffle mask
41       CNTB,                     ///< Count leading ones in bytes
42       PREFSLOT2VEC,             ///< Promote scalar->vector
43       VEC2PREFSLOT,             ///< Extract element 0
44       SHL_BITS,                 ///< Shift quad left, by bits
45       SHL_BYTES,                ///< Shift quad left, by bytes
46       SRL_BYTES,                ///< Shift quad right, by bytes. Insert zeros.
47       VEC_ROTL,                 ///< Vector rotate left
48       VEC_ROTR,                 ///< Vector rotate right
49       ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
50       ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
51       SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
52       SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
53       // Markers: These aren't used to generate target-dependent nodes, but
54       // are used during instruction selection.
55       ADD64_MARKER,             ///< i64 addition marker
56       SUB64_MARKER,             ///< i64 subtraction marker
57       MUL64_MARKER,             ///< i64 multiply marker
58       LAST_SPUISD               ///< Last user-defined instruction
59     };
60   }
61 
62   //! Utility functions specific to CellSPU:
63   namespace SPU {
64     SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
65                              EVT ValueType);
66     SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
67                              EVT ValueType);
68     SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
69                              EVT ValueType);
70     SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
71                             EVT ValueType);
72     SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
73                               EVT ValueType);
74     SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75     SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
76 
77     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
78                               const SPUTargetMachine &TM);
79     //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
80     SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
81                              DebugLoc dl);
82   }
83 
84   class SPUTargetMachine;            // forward dec'l.
85 
86   class SPUTargetLowering :
87     public TargetLowering
88   {
89     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
90     SPUTargetMachine &SPUTM;
91 
92   public:
93     //! The venerable constructor
94     /*!
95      This is where the CellSPU backend sets operation handling (i.e., legal,
96      custom, expand or promote.)
97      */
98     SPUTargetLowering(SPUTargetMachine &TM);
99 
100     //! Get the target machine
getSPUTargetMachine()101     SPUTargetMachine &getSPUTargetMachine() {
102       return SPUTM;
103     }
104 
105     /// getTargetNodeName() - This method returns the name of a target specific
106     /// DAG node.
107     virtual const char *getTargetNodeName(unsigned Opcode) const;
108 
109     /// getSetCCResultType - Return the ValueType for ISD::SETCC
110     virtual EVT getSetCCResultType(EVT VT) const;
111 
getShiftAmountTy(EVT LHSTy)112     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
113 
114     //! Custom lowering hooks
115     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
116 
117     //! Custom lowering hook for nodes with illegal result types.
118     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
119                                     SelectionDAG &DAG) const;
120 
121     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
122 
123     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
124                                                 const APInt &Mask,
125                                                 APInt &KnownZero,
126                                                 APInt &KnownOne,
127                                                 const SelectionDAG &DAG,
128                                                 unsigned Depth = 0) const;
129 
130     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
131                                                    unsigned Depth = 0) const;
132 
133     ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
134 
135     /// Examine constraint string and operand type and determine a weight value.
136     /// The operand object must already have been set up with the operand type.
137     ConstraintWeight getSingleConstraintMatchWeight(
138       AsmOperandInfo &info, const char *constraint) const;
139 
140     std::pair<unsigned, const TargetRegisterClass*>
141       getRegForInlineAsmConstraint(const std::string &Constraint,
142                                    EVT VT) const;
143 
144     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
145                                       std::vector<SDValue> &Ops,
146                                       SelectionDAG &DAG) const;
147 
148     /// isLegalAddressImmediate - Return true if the integer value can be used
149     /// as the offset of the target addressing mode.
150     virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
151     virtual bool isLegalAddressImmediate(GlobalValue *) const;
152 
153     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
154 
155     virtual SDValue
156       LowerFormalArguments(SDValue Chain,
157                            CallingConv::ID CallConv, bool isVarArg,
158                            const SmallVectorImpl<ISD::InputArg> &Ins,
159                            DebugLoc dl, SelectionDAG &DAG,
160                            SmallVectorImpl<SDValue> &InVals) const;
161 
162     virtual SDValue
163       LowerCall(SDValue Chain, SDValue Callee,
164                 CallingConv::ID CallConv, bool isVarArg,
165                 bool &isTailCall,
166                 const SmallVectorImpl<ISD::OutputArg> &Outs,
167                 const SmallVectorImpl<SDValue> &OutVals,
168                 const SmallVectorImpl<ISD::InputArg> &Ins,
169                 DebugLoc dl, SelectionDAG &DAG,
170                 SmallVectorImpl<SDValue> &InVals) const;
171 
172     virtual SDValue
173       LowerReturn(SDValue Chain,
174                   CallingConv::ID CallConv, bool isVarArg,
175                   const SmallVectorImpl<ISD::OutputArg> &Outs,
176                   const SmallVectorImpl<SDValue> &OutVals,
177                   DebugLoc dl, SelectionDAG &DAG) const;
178 
179     virtual bool isLegalICmpImmediate(int64_t Imm) const;
180 
181     virtual bool isLegalAddressingMode(const AddrMode &AM,
182                                        Type *Ty) const;
183   };
184 }
185 
186 #endif
187