1 /*
2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27
28 #ifndef AMDGPU_WINSYS_H
29 #define AMDGPU_WINSYS_H
30
31 #include "pipebuffer/pb_cache.h"
32 #include "pipebuffer/pb_slab.h"
33 #include "gallium/drivers/radeon/radeon_winsys.h"
34 #include "addrlib/addrinterface.h"
35 #include "util/simple_mtx.h"
36 #include "util/u_queue.h"
37 #include <amdgpu.h>
38
39 struct amdgpu_cs;
40
41 #define AMDGPU_SLAB_MIN_SIZE_LOG2 9 /* 512 bytes */
42 #define AMDGPU_SLAB_MAX_SIZE_LOG2 16 /* 64 KB */
43 #define AMDGPU_SLAB_BO_SIZE_LOG2 17 /* 128 KB */
44
45 struct amdgpu_winsys {
46 struct radeon_winsys base;
47 struct pipe_reference reference;
48 struct pb_cache bo_cache;
49 struct pb_slabs bo_slabs;
50
51 amdgpu_device_handle dev;
52
53 simple_mtx_t bo_fence_lock;
54
55 int num_cs; /* The number of command streams created. */
56 unsigned num_total_rejected_cs;
57 uint32_t surf_index_color;
58 uint32_t surf_index_fmask;
59 uint32_t next_bo_unique_id;
60 uint64_t allocated_vram;
61 uint64_t allocated_gtt;
62 uint64_t mapped_vram;
63 uint64_t mapped_gtt;
64 uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
65 uint64_t num_gfx_IBs;
66 uint64_t num_sdma_IBs;
67 uint64_t num_mapped_buffers;
68 uint64_t gfx_bo_list_counter;
69 uint64_t gfx_ib_size_counter;
70
71 struct radeon_info info;
72
73 /* multithreaded IB submission */
74 struct util_queue cs_queue;
75
76 struct amdgpu_gpu_info amdinfo;
77 ADDR_HANDLE addrlib;
78
79 bool check_vm;
80 bool debug_all_bos;
81 bool reserve_vmid;
82
83 /* List of all allocated buffers */
84 simple_mtx_t global_bo_list_lock;
85 struct list_head global_bo_list;
86 unsigned num_buffers;
87 };
88
89 static inline struct amdgpu_winsys *
amdgpu_winsys(struct radeon_winsys * base)90 amdgpu_winsys(struct radeon_winsys *base)
91 {
92 return (struct amdgpu_winsys*)base;
93 }
94
95 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws);
96
97 #endif
98