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1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an ARM MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 /* Capstone Disassembly Engine */
15 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
16 
17 #ifdef CAPSTONE_HAS_ARM
18 
19 #include <stdio.h>	// DEBUG
20 #include <stdlib.h>
21 #include <string.h>
22 #include <platform.h>
23 
24 #include "ARMInstPrinter.h"
25 #include "ARMAddressingModes.h"
26 #include "ARMBaseInfo.h"
27 #include "ARMDisassembler.h"
28 #include "../../MCInst.h"
29 #include "../../SStream.h"
30 #include "../../MCRegisterInfo.h"
31 #include "../../utils.h"
32 #include "ARMMapping.h"
33 
34 #define GET_SUBTARGETINFO_ENUM
35 #include "ARMGenSubtargetInfo.inc"
36 
37 static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo);
38 
39 // Autogenerated by tblgen.
40 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
41 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
42 static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
43 static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
44 
45 static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
46 static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
47 static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
48 static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
49 static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
50 static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
51 static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
52 static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0);
53 static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
54 static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
55 static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
56 static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
57 static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
58 static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
59 static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
60 
61 static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
62 static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
63 static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
64 static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
65 static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
66 static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned);
67 static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
68 static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
69 static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
70 static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
71 static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale);
72 static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
73 static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
74 static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
75 static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
76 static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
77 static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
78 static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
79 static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
80 static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
81 static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
82 static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
83 static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
84 static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
85 static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
86 static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
87 static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
88 static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
89 static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
90 static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
91 static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
92 static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
93 static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
94 static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
95 static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
96 static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
97 static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
98 static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
99 static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
100 static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
101 static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
102 static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
103 static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
104 static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
105 static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
106 static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
107 static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI);
108 static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
109 static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
110 static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
111 static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *RI);
112 static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
113 static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
114 static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O, MCRegisterInfo *MRI);
115 static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
116 static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
117 static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
118 static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
119 
120 static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
121 
set_mem_access(MCInst * MI,bool status)122 static void set_mem_access(MCInst *MI, bool status)
123 {
124 	if (MI->csh->detail != CS_OPT_ON)
125 		return;
126 
127 	MI->csh->doing_mem = status;
128 	if (status) {
129 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
130 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
131 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
132 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
133 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
134 	} else {
135 		// done, create the next operand slot
136 		MI->flat_insn->detail->arm.op_count++;
137 	}
138 }
139 
op_addImm(MCInst * MI,int v)140 static void op_addImm(MCInst *MI, int v)
141 {
142 	if (MI->csh->detail) {
143 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
144 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
145 		MI->flat_insn->detail->arm.op_count++;
146 	}
147 }
148 
149 #define GET_INSTRINFO_ENUM
150 #include "ARMGenInstrInfo.inc"
151 
152 //#define PRINT_ALIAS_INSTR
153 #include "ARMGenAsmWriter.inc"
154 
ARM_getRegName(cs_struct * handle,int value)155 void ARM_getRegName(cs_struct *handle, int value)
156 {
157 	if (value == CS_OPT_SYNTAX_NOREGNAME) {
158 		handle->get_regname = getRegisterName2;
159 		handle->reg_name = ARM_reg_name2;;
160 	} else {
161 		handle->get_regname = getRegisterName;
162 		handle->reg_name = ARM_reg_name;;
163 	}
164 }
165 
166 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
167 ///
168 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
translateShiftImm(unsigned imm)169 static unsigned translateShiftImm(unsigned imm)
170 {
171 	// lsr #32 and asr #32 exist, but should be encoded as a 0.
172 	//assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
173 	if (imm == 0)
174 		return 32;
175 	return imm;
176 }
177 
178 /// Prints the shift value with an immediate value.
printRegImmShift(MCInst * MI,SStream * O,ARM_AM_ShiftOpc ShOpc,unsigned ShImm)179 static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
180 {
181 	if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
182 		return;
183 	SStream_concat0(O, ", ");
184 
185 	//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
186 	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
187 	if (MI->csh->detail) {
188 		if (MI->csh->doing_mem)
189 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
190 		else
191 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
192 	}
193 
194 	if (ShOpc != ARM_AM_rrx) {
195 		SStream_concat0(O, " ");
196 		SStream_concat(O, "#%u", translateShiftImm(ShImm));
197 		if (MI->csh->detail) {
198 			if (MI->csh->doing_mem)
199 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
200 			else
201 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
202 		}
203 	}
204 }
205 
printRegName(cs_struct * h,SStream * OS,unsigned RegNo)206 static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
207 {
208 #ifndef CAPSTONE_DIET
209 	SStream_concat0(OS, h->get_regname(RegNo));
210 #endif
211 }
212 
213 static name_map insn_update_flgs[] = {
214 	{ ARM_INS_CMN, "cmn" },
215 	{ ARM_INS_CMP, "cmp" },
216 	{ ARM_INS_TEQ, "teq" },
217 	{ ARM_INS_TST, "tst" },
218 
219 	{ ARM_INS_ADC, "adcs" },
220 	{ ARM_INS_ADD, "adds" },
221 	{ ARM_INS_AND, "ands" },
222 	{ ARM_INS_ASR, "asrs" },
223 	{ ARM_INS_BIC, "bics" },
224 	{ ARM_INS_EOR, "eors" },
225 	{ ARM_INS_LSL, "lsls" },
226 	{ ARM_INS_LSR, "lsrs" },
227 	{ ARM_INS_MLA, "mlas" },
228 	{ ARM_INS_MOV, "movs" },
229 	{ ARM_INS_MUL, "muls" },
230 	{ ARM_INS_MVN, "mvns" },
231 	{ ARM_INS_ORN, "orns" },
232 	{ ARM_INS_ORR, "orrs" },
233 	{ ARM_INS_ROR, "rors" },
234 	{ ARM_INS_RRX, "rrxs" },
235 	{ ARM_INS_RSB, "rsbs" },
236 	{ ARM_INS_RSC, "rscs" },
237 	{ ARM_INS_SBC, "sbcs" },
238 	{ ARM_INS_SMLAL, "smlals" },
239 	{ ARM_INS_SMULL, "smulls" },
240 	{ ARM_INS_SUB, "subs" },
241 	{ ARM_INS_UMLAL, "umlals" },
242 	{ ARM_INS_UMULL, "umulls" },
243 
244 	{ ARM_INS_UADD8, "uadd8" },
245 };
246 
ARM_post_printer(csh ud,cs_insn * insn,char * insn_asm,MCInst * mci)247 void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
248 {
249 	if (((cs_struct *)ud)->detail != CS_OPT_ON)
250 		return;
251 
252 	// check if this insn requests write-back
253 	if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) {
254 		insn->detail->arm.writeback = true;
255 	} else if (mci->csh->mode & CS_MODE_THUMB) {
256 		// handle some special instructions with writeback
257         //printf(">> Opcode = %u\n", mci->Opcode);
258 		switch(mci->Opcode) {
259 			default:
260 				break;
261 			case ARM_t2LDC2L_PRE:
262 			case ARM_t2LDC2_PRE:
263 			case ARM_t2LDCL_PRE:
264 			case ARM_t2LDC_PRE:
265 
266 			case ARM_t2LDRB_PRE:
267 			case ARM_t2LDRD_PRE:
268 			case ARM_t2LDRH_PRE:
269 			case ARM_t2LDRSB_PRE:
270 			case ARM_t2LDRSH_PRE:
271 			case ARM_t2LDR_PRE:
272 
273 			case ARM_t2STC2L_PRE:
274 			case ARM_t2STC2_PRE:
275 			case ARM_t2STCL_PRE:
276 			case ARM_t2STC_PRE:
277 
278 			case ARM_t2STRB_PRE:
279 			case ARM_t2STRD_PRE:
280 			case ARM_t2STRH_PRE:
281 			case ARM_t2STR_PRE:
282 
283 			case ARM_t2LDC2L_POST:
284 			case ARM_t2LDC2_POST:
285 			case ARM_t2LDCL_POST:
286 			case ARM_t2LDC_POST:
287 
288 			case ARM_t2LDRB_POST:
289 			case ARM_t2LDRD_POST:
290 			case ARM_t2LDRH_POST:
291 			case ARM_t2LDRSB_POST:
292 			case ARM_t2LDRSH_POST:
293 			case ARM_t2LDR_POST:
294 
295 			case ARM_t2STC2L_POST:
296 			case ARM_t2STC2_POST:
297 			case ARM_t2STCL_POST:
298 			case ARM_t2STC_POST:
299 
300 			case ARM_t2STRB_POST:
301 			case ARM_t2STRD_POST:
302 			case ARM_t2STRH_POST:
303 			case ARM_t2STR_POST:
304 				insn->detail->arm.writeback = true;
305 				break;
306 		}
307 	} else {	// ARM mode
308 		// handle some special instructions with writeback
309         //printf(">> Opcode = %u\n", mci->Opcode);
310 		switch(mci->Opcode) {
311 			default:
312 				break;
313 			case ARM_LDC2L_PRE:
314 			case ARM_LDC2_PRE:
315 			case ARM_LDCL_PRE:
316 			case ARM_LDC_PRE:
317 
318 			case ARM_LDRD_PRE:
319 			case ARM_LDRH_PRE:
320 			case ARM_LDRSB_PRE:
321 			case ARM_LDRSH_PRE:
322 
323 			case ARM_STC2L_PRE:
324 			case ARM_STC2_PRE:
325 			case ARM_STCL_PRE:
326 			case ARM_STC_PRE:
327 
328 			case ARM_STRD_PRE:
329 			case ARM_STRH_PRE:
330 
331 			case ARM_LDC2L_POST:
332 			case ARM_LDC2_POST:
333 			case ARM_LDCL_POST:
334 			case ARM_LDC_POST:
335 
336 			case ARM_LDRBT_POST:
337 			case ARM_LDRD_POST:
338 			case ARM_LDRH_POST:
339 			case ARM_LDRSB_POST:
340 			case ARM_LDRSH_POST:
341 
342 			case ARM_STC2L_POST:
343 			case ARM_STC2_POST:
344 			case ARM_STCL_POST:
345 			case ARM_STC_POST:
346 
347 			case ARM_STRBT_POST:
348 			case ARM_STRD_POST:
349 			case ARM_STRH_POST:
350 
351 			case ARM_LDRB_POST_IMM:
352 			case ARM_LDR_POST_IMM:
353 			case ARM_LDR_POST_REG:
354 			case ARM_STRB_POST_IMM:
355 			case ARM_STR_POST_IMM:
356 
357 				insn->detail->arm.writeback = true;
358 				break;
359 		}
360 	}
361 
362 	// check if this insn requests update flags
363 	if (insn->detail->arm.update_flags == false) {
364 		// some insn still update flags, regardless of tabgen info
365 		unsigned int i, j;
366 
367 		for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
368 			if (insn->id == insn_update_flgs[i].id &&
369 					!strncmp(insn_asm, insn_update_flgs[i].name,
370 						strlen(insn_update_flgs[i].name))) {
371 				insn->detail->arm.update_flags = true;
372 				// we have to update regs_write array as well
373 				for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
374 					if (insn->detail->regs_write[j] == 0) {
375 						insn->detail->regs_write[j] = ARM_REG_CPSR;
376 						break;
377 					}
378 				}
379 				break;
380 			}
381 		}
382 	}
383 
384 	// instruction should not have invalid CC
385 	if (insn->detail->arm.cc == ARM_CC_INVALID) {
386 		insn->detail->arm.cc = ARM_CC_AL;
387 	}
388 
389 	// manual fix for some special instructions
390 	// printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
391 	switch(mci->Opcode) {
392 		default:
393 			break;
394 		case ARM_MOVPCLR:
395 			insn->detail->arm.operands[0].type = ARM_OP_REG;
396 			insn->detail->arm.operands[0].reg = ARM_REG_PC;
397 			insn->detail->arm.operands[1].type = ARM_OP_REG;
398 			insn->detail->arm.operands[1].reg = ARM_REG_LR;
399 			insn->detail->arm.op_count = 2;
400 			break;
401 	}
402 }
403 
ARM_printInst(MCInst * MI,SStream * O,void * Info)404 void ARM_printInst(MCInst *MI, SStream *O, void *Info)
405 {
406 	MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
407 
408 	unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode;
409 
410 	switch(Opcode) {
411 		// Check for HINT instructions w/ canonical names.
412 		case ARM_HINT:
413 		case ARM_tHINT:
414 		case ARM_t2HINT:
415 			switch (MCOperand_getImm(MCInst_getOperand(MI, 0))) {
416 				case 0: SStream_concat0(O, "nop"); pubOpcode = ARM_INS_NOP; break;
417 				case 1: SStream_concat0(O, "yield"); pubOpcode = ARM_INS_YIELD; break;
418 				case 2: SStream_concat0(O, "wfe"); pubOpcode = ARM_INS_WFE; break;
419 				case 3: SStream_concat0(O, "wfi"); pubOpcode = ARM_INS_WFI; break;
420 				case 4: SStream_concat0(O, "sev"); pubOpcode = ARM_INS_SEV; break;
421 				case 5:
422 						if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) {
423 							SStream_concat0(O, "sevl");
424 							pubOpcode = ARM_INS_SEVL;
425 							break;
426 						}
427 						// Fallthrough for non-v8
428 				default:
429 						// Anything else should just print normally.
430 						printInstruction(MI, O, MRI);
431 						return;
432 			}
433 			printPredicateOperand(MI, 1, O);
434 			if (Opcode == ARM_t2HINT)
435 				SStream_concat0(O, ".w");
436 
437 			MCInst_setOpcodePub(MI, pubOpcode);
438 
439 			return;
440 
441 			// Check for MOVs and print canonical forms, instead.
442 		case ARM_MOVsr: {
443 							// FIXME: Thumb variants?
444 							MCOperand *Dst = MCInst_getOperand(MI, 0);
445 							MCOperand *MO1 = MCInst_getOperand(MI, 1);
446 							MCOperand *MO2 = MCInst_getOperand(MI, 2);
447 							MCOperand *MO3 = MCInst_getOperand(MI, 3);
448 
449 							SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
450 							printSBitModifierOperand(MI, 6, O);
451 							printPredicateOperand(MI, 4, O);
452 
453 							SStream_concat0(O, "\t");
454 							printRegName(MI->csh, O, MCOperand_getReg(Dst));
455 							if (MI->csh->detail) {
456 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
457 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
458 								MI->flat_insn->detail->arm.op_count++;
459 							}
460 
461 							SStream_concat0(O, ", ");
462 							printRegName(MI->csh, O, MCOperand_getReg(MO1));
463 
464 							if (MI->csh->detail) {
465 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
466 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
467 								MI->flat_insn->detail->arm.op_count++;
468 							}
469 
470 							SStream_concat0(O, ", ");
471 							printRegName(MI->csh, O, MCOperand_getReg(MO2));
472 							if (MI->csh->detail) {
473 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
474 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
475 								MI->flat_insn->detail->arm.op_count++;
476 							}
477 							//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
478 							return;
479 						}
480 
481 		case ARM_MOVsi: {
482 							// FIXME: Thumb variants?
483 							MCOperand *Dst = MCInst_getOperand(MI, 0);
484 							MCOperand *MO1 = MCInst_getOperand(MI, 1);
485 							MCOperand *MO2 = MCInst_getOperand(MI, 2);
486 
487 							SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
488 							printSBitModifierOperand(MI, 5, O);
489 							printPredicateOperand(MI, 3, O);
490 
491 							SStream_concat0(O, "\t");
492 							printRegName(MI->csh, O, MCOperand_getReg(Dst));
493 							if (MI->csh->detail) {
494 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
495 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
496 								MI->flat_insn->detail->arm.op_count++;
497 							}
498 
499 							SStream_concat0(O, ", ");
500 							printRegName(MI->csh, O, MCOperand_getReg(MO1));
501 							if (MI->csh->detail) {
502 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
503 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
504 								MI->flat_insn->detail->arm.op_count++;
505 							}
506 
507 							if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
508 								//printAnnotation(O, Annot);
509 								return;
510 							}
511 
512 							SStream_concat0(O, ", ");
513 							tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
514 							if (tmp > HEX_THRESHOLD)
515 								SStream_concat(O, "#0x%x", tmp);
516 							else
517 								SStream_concat(O, "#%u", tmp);
518 							if (MI->csh->detail) {
519 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
520 									(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
521 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
522 							}
523 							return;
524 						}
525 
526 						// A8.6.123 PUSH
527 		case ARM_STMDB_UPD:
528 		case ARM_t2STMDB_UPD:
529 						if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
530 								MCInst_getNumOperands(MI) > 5) {
531 							// Should only print PUSH if there are at least two registers in the list.
532 							SStream_concat0(O, "push");
533 							MCInst_setOpcodePub(MI, ARM_INS_PUSH);
534 							printPredicateOperand(MI, 2, O);
535 							if (Opcode == ARM_t2STMDB_UPD)
536 								SStream_concat0(O, ".w");
537 							SStream_concat0(O, "\t");
538 							printRegisterList(MI, 4, O);
539 							return;
540 						}
541 						break;
542 
543 		case ARM_STR_PRE_IMM:
544 						if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
545 								MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
546 							SStream_concat0(O, "push");
547 							MCInst_setOpcodePub(MI, ARM_INS_PUSH);
548 							printPredicateOperand(MI, 4, O);
549 							SStream_concat0(O, "\t{");
550 							printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
551 							if (MI->csh->detail) {
552 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
553 								MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
554 								MI->flat_insn->detail->arm.op_count++;
555 							}
556 							SStream_concat0(O, "}");
557 							return;
558 						}
559 						break;
560 
561 						// A8.6.122 POP
562 		case ARM_LDMIA_UPD:
563 		case ARM_t2LDMIA_UPD:
564 						if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
565 								MCInst_getNumOperands(MI) > 5) {
566 							// Should only print POP if there are at least two registers in the list.
567 							SStream_concat0(O, "pop");
568 							MCInst_setOpcodePub(MI, ARM_INS_POP);
569 							printPredicateOperand(MI, 2, O);
570 							if (Opcode == ARM_t2LDMIA_UPD)
571 								SStream_concat0(O, ".w");
572 							SStream_concat0(O, "\t");
573 							printRegisterList(MI, 4, O);
574 							return;
575 						}
576 						break;
577 
578 		case ARM_LDR_POST_IMM:
579 						if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) {
580 							MCOperand *MO2 = MCInst_getOperand(MI, 4);
581 							if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add &&
582 										getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) ||
583 									MCOperand_getImm(MO2) == 4) {
584 								SStream_concat0(O, "pop");
585 								MCInst_setOpcodePub(MI, ARM_INS_POP);
586 								printPredicateOperand(MI, 5, O);
587 								SStream_concat0(O, "\t{");
588 								printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
589 								if (MI->csh->detail) {
590 									MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
591 									MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
592 									MI->flat_insn->detail->arm.op_count++;
593                                     // this instruction implicitly read/write SP register
594                                     MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
595                                     MI->flat_insn->detail->regs_read_count++;
596                                     MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
597                                     MI->flat_insn->detail->regs_write_count++;
598 								}
599 								SStream_concat0(O, "}");
600 								return;
601 							}
602 						}
603 						break;
604 
605 						// A8.6.355 VPUSH
606 		case ARM_VSTMSDB_UPD:
607 		case ARM_VSTMDDB_UPD:
608 						if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
609 							SStream_concat0(O, "vpush");
610 							MCInst_setOpcodePub(MI, ARM_INS_VPUSH);
611 							printPredicateOperand(MI, 2, O);
612 							SStream_concat0(O, "\t");
613 							printRegisterList(MI, 4, O);
614 							return;
615 						}
616 						break;
617 
618 						// A8.6.354 VPOP
619 		case ARM_VLDMSIA_UPD:
620 		case ARM_VLDMDIA_UPD:
621 						if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
622 							SStream_concat0(O, "vpop");
623 							MCInst_setOpcodePub(MI, ARM_INS_VPOP);
624 							printPredicateOperand(MI, 2, O);
625 							SStream_concat0(O, "\t");
626 							printRegisterList(MI, 4, O);
627 							return;
628 						}
629 						break;
630 
631 		case ARM_tLDMIA: {
632 							 bool Writeback = true;
633 							 unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
634 							 unsigned i;
635 							 for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
636 								 if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
637 									 Writeback = false;
638 							 }
639 
640 							 SStream_concat0(O, "ldm");
641 							 MCInst_setOpcodePub(MI, ARM_INS_LDM);
642 
643 							 printPredicateOperand(MI, 1, O);
644 							 SStream_concat0(O, "\t");
645 							 printRegName(MI->csh, O, BaseReg);
646 							 if (MI->csh->detail) {
647 								 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
648 								 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
649 								 MI->flat_insn->detail->arm.op_count++;
650 							 }
651 							 if (Writeback) {
652 								 MI->writeback = true;
653 								 SStream_concat0(O, "!");
654 							 }
655 							 SStream_concat0(O, ", ");
656 							 printRegisterList(MI, 3, O);
657 							 return;
658 						 }
659 
660 						 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
661 						 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
662 						 // a single GPRPair reg operand is used in the .td file to replace the two
663 						 // GPRs. However, when decoding them, the two GRPs cannot be automatically
664 						 // expressed as a GPRPair, so we have to manually merge them.
665 						 // FIXME: We would really like to be able to tablegen'erate this.
666 		case ARM_LDREXD:
667 		case ARM_STREXD:
668 		case ARM_LDAEXD:
669 		case ARM_STLEXD: {
670 				MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
671 				bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
672 
673 				unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
674 				if (MCRegisterClass_contains(MRC, Reg)) {
675 				    MCInst NewMI;
676 
677 				    MCInst_Init(&NewMI);
678 				    MCInst_setOpcode(&NewMI, Opcode);
679 
680 				    if (isStore)
681 						MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
682 
683 				    MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
684 								MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
685 
686 				    // Copy the rest operands into NewMI.
687 				    for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
688 						MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
689 
690 				    printInstruction(&NewMI, O, MRI);
691 				    return;
692 				}
693 		 }
694 	}
695 
696 	//if (printAliasInstr(MI, O, MRI))
697 	//	printInstruction(MI, O, MRI);
698 	printInstruction(MI, O, MRI);
699 }
700 
printOperand(MCInst * MI,unsigned OpNo,SStream * O)701 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
702 {
703 	int32_t imm;
704 	MCOperand *Op = MCInst_getOperand(MI, OpNo);
705 	if (MCOperand_isReg(Op)) {
706 		unsigned Reg = MCOperand_getReg(Op);
707 		printRegName(MI->csh, O, Reg);
708 		if (MI->csh->detail) {
709 			if (MI->csh->doing_mem) {
710 				if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
711 					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
712 				else
713 					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
714 			} else {
715 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
716 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
717 				MI->flat_insn->detail->arm.op_count++;
718 			}
719 		}
720 	} else if (MCOperand_isImm(Op)) {
721 		unsigned int opc = MCInst_getOpcode(MI);
722 
723 		imm = (int32_t)MCOperand_getImm(Op);
724 
725 		// relative branch only has relative offset, so we have to update it
726 		// to reflect absolute address.
727 		// Note: in ARM, PC is always 2 instructions ahead, so we have to
728 		// add 8 in ARM mode, or 4 in Thumb mode
729 		// printf(">> opcode: %u\n", MCInst_getOpcode(MI));
730 		if (ARM_rel_branch(MI->csh, opc)) {
731 			uint32_t address;
732 
733 			// only do this for relative branch
734 			if (MI->csh->mode & CS_MODE_THUMB) {
735 				address = (uint32_t)MI->address + 4;
736 				if (ARM_blx_to_arm_mode(MI->csh, opc)) {
737 					// here need to align down to the nearest 4-byte address
738 #define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
739 					address = _ALIGN_DOWN(address, 4);
740 #undef _ALIGN_DOWN
741 				}
742 			} else {
743 				address = (uint32_t)MI->address + 8;
744 			}
745 
746 			imm += address;
747 
748 			if (imm > HEX_THRESHOLD)
749 				SStream_concat(O, "#0x%x", imm);
750 			else
751 				SStream_concat(O, "#%u", imm);
752 		} else {
753 			switch(MI->flat_insn->id) {
754 				default:
755 					if (imm >= 0) {
756 						if (imm > HEX_THRESHOLD)
757 							SStream_concat(O, "#0x%x", imm);
758 						else
759 							SStream_concat(O, "#%u", imm);
760 					} else {
761 						if (imm < -HEX_THRESHOLD)
762 							SStream_concat(O, "#-0x%x", -imm);
763 						else
764 							SStream_concat(O, "#-%u", -imm);
765 					}
766 					break;
767 				case ARM_INS_AND:
768 				case ARM_INS_ORR:
769 				case ARM_INS_EOR:
770 				case ARM_INS_BIC:
771 				case ARM_INS_MVN:
772 					// do not print number in negative form
773 					if (imm >= 0 && imm <= HEX_THRESHOLD)
774 						SStream_concat(O, "#%u", imm);
775 					else
776 						SStream_concat(O, "#0x%x", imm);
777 					break;
778 			}
779 		}
780 
781 		if (MI->csh->detail) {
782 			if (MI->csh->doing_mem)
783 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
784 			else {
785 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
786 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
787 				MI->flat_insn->detail->arm.op_count++;
788 			}
789 		}
790 	}
791 }
792 
printThumbLdrLabelOperand(MCInst * MI,unsigned OpNum,SStream * O)793 static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
794 {
795 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
796 	int32_t OffImm;
797 	bool isSub;
798 	SStream_concat0(O, "[pc, ");
799 
800 	OffImm = (int32_t)MCOperand_getImm(MO1);
801 	isSub = OffImm < 0;
802 
803 	// Special value for #-0. All others are normal.
804 	if (OffImm == INT32_MIN)
805 		OffImm = 0;
806 	if (isSub) {
807 		SStream_concat(O, "#-0x%x", -OffImm);
808 	} else {
809 		if (OffImm > HEX_THRESHOLD)
810 			SStream_concat(O, "#0x%x", OffImm);
811 		else
812 			SStream_concat(O, "#%u", OffImm);
813 	}
814 
815 	SStream_concat0(O, "]");
816 
817 	if (MI->csh->detail) {
818 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
819 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
820 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
821 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
822 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
823 		MI->flat_insn->detail->arm.op_count++;
824 	}
825 }
826 
827 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
828 // "Addressing Mode 1 - Data-processing operands" forms.  This includes:
829 //    REG 0   0           - e.g. R5
830 //    REG REG 0,SH_OPC    - e.g. R5, ROR R3
831 //    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
printSORegRegOperand(MCInst * MI,unsigned OpNum,SStream * O)832 static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
833 {
834 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
835 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
836 	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
837 	ARM_AM_ShiftOpc ShOpc;
838 
839 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
840 
841 	if (MI->csh->detail) {
842 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
843 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
844 
845 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
846 		MI->flat_insn->detail->arm.op_count++;
847 	}
848 
849 	// Print the shift opc.
850 	ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
851 	SStream_concat0(O, ", ");
852 	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
853 	if (ShOpc == ARM_AM_rrx)
854 		return;
855 
856 	SStream_concat0(O, " ");
857 	printRegName(MI->csh, O, MCOperand_getReg(MO2));
858 	if (MI->csh->detail)
859 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
860 	//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
861 }
862 
printSORegImmOperand(MCInst * MI,unsigned OpNum,SStream * O)863 static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
864 {
865 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
866 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
867 
868 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
869 	if (MI->csh->detail) {
870 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
871 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
872 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
873 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
874 		MI->flat_insn->detail->arm.op_count++;
875 	}
876 
877 	// Print the shift opc.
878 	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
879 			getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
880 }
881 
882 //===--------------------------------------------------------------------===//
883 // Addressing Mode #2
884 //===--------------------------------------------------------------------===//
885 
printAM2PreOrOffsetIndexOp(MCInst * MI,unsigned Op,SStream * O)886 static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
887 {
888 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
889 	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
890 	MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
891 	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
892 
893 	SStream_concat0(O, "[");
894 	set_mem_access(MI, true);
895 
896 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
897 	if (MI->csh->detail) {
898 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
899 	}
900 
901 	if (!MCOperand_getReg(MO2)) {
902 		unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
903 		if (tmp) { // Don't print +0.
904 			subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
905 
906 			SStream_concat0(O, ", ");
907 			if (tmp > HEX_THRESHOLD)
908 				SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp);
909 			else
910 				SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp);
911 			if (MI->csh->detail) {
912 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
913 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
914 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
915 			}
916 		}
917 		SStream_concat0(O, "]");
918 		set_mem_access(MI, false);
919 		return;
920 	}
921 
922 	SStream_concat0(O, ", ");
923 	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
924 	printRegName(MI->csh, O, MCOperand_getReg(MO2));
925 	if (MI->csh->detail) {
926 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
927 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
928 	}
929 
930 	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
931 			getAM2Offset((unsigned int)MCOperand_getImm(MO3)));
932 	SStream_concat0(O, "]");
933 	set_mem_access(MI, false);
934 }
935 
printAddrModeTBB(MCInst * MI,unsigned Op,SStream * O)936 static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
937 {
938 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
939 	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
940 	SStream_concat0(O, "[");
941 	set_mem_access(MI, true);
942 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
943 	if (MI->csh->detail)
944 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
945 	SStream_concat0(O, ", ");
946 	printRegName(MI->csh, O, MCOperand_getReg(MO2));
947 	if (MI->csh->detail)
948 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
949 	SStream_concat0(O, "]");
950 	set_mem_access(MI, false);
951 }
952 
printAddrModeTBH(MCInst * MI,unsigned Op,SStream * O)953 static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
954 {
955 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
956 	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
957 	SStream_concat0(O, "[");
958 	set_mem_access(MI, true);
959 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
960 	if (MI->csh->detail)
961 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
962 	SStream_concat0(O, ", ");
963 	printRegName(MI->csh, O, MCOperand_getReg(MO2));
964 	if (MI->csh->detail)
965 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
966 	SStream_concat0(O, ", lsl #1]");
967 	if (MI->csh->detail) {
968 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
969 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
970 	}
971 	set_mem_access(MI, false);
972 }
973 
printAddrMode2Operand(MCInst * MI,unsigned Op,SStream * O)974 static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O)
975 {
976 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
977 
978 	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
979 		printOperand(MI, Op, O);
980 		return;
981 	}
982 
983 	printAM2PreOrOffsetIndexOp(MI, Op, O);
984 }
985 
printAddrMode2OffsetOperand(MCInst * MI,unsigned OpNum,SStream * O)986 static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
987 {
988 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
989 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
990 	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2));
991 
992 	if (!MCOperand_getReg(MO1)) {
993 		unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
994 		if (ImmOffs > HEX_THRESHOLD)
995 			SStream_concat(O, "#%s0x%x",
996 					ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
997 		else
998 			SStream_concat(O, "#%s%u",
999 					ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1000 		if (MI->csh->detail) {
1001 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1002 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1003 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1004 			MI->flat_insn->detail->arm.op_count++;
1005 		}
1006 		return;
1007 	}
1008 
1009 	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
1010 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1011 	if (MI->csh->detail) {
1012 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1013 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1014 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1015 		MI->flat_insn->detail->arm.op_count++;
1016 	}
1017 
1018 	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
1019 			getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
1020 }
1021 
1022 //===--------------------------------------------------------------------===//
1023 // Addressing Mode #3
1024 //===--------------------------------------------------------------------===//
1025 
printAM3PreOrOffsetIndexOp(MCInst * MI,unsigned Op,SStream * O,bool AlwaysPrintImm0)1026 static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
1027 		bool AlwaysPrintImm0)
1028 {
1029 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
1030 	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
1031 	MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
1032 	ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3));
1033 	unsigned ImmOffs;
1034 
1035 	SStream_concat0(O, "[");
1036 	set_mem_access(MI, true);
1037 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1038 	if (MI->csh->detail)
1039 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1040 
1041 	if (MCOperand_getReg(MO2)) {
1042 		SStream_concat0(O, ", ");
1043 		SStream_concat0(O, ARM_AM_getAddrOpcStr(sign));
1044 		printRegName(MI->csh, O, MCOperand_getReg(MO2));
1045 		if (MI->csh->detail) {
1046 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
1047 			if (!sign) {
1048 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
1049 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
1050 			}
1051 		}
1052 		SStream_concat0(O, "]");
1053 		set_mem_access(MI, false);
1054 		return;
1055 	}
1056 
1057 	//If the op is sub we have to print the immediate even if it is 0
1058 	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
1059 
1060 	if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) {
1061 		if (ImmOffs > HEX_THRESHOLD)
1062 			SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs);
1063 		else
1064 			SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs);
1065 	}
1066 
1067 	if (MI->csh->detail) {
1068 		if (!sign) {
1069 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
1070 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
1071 		} else
1072 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs;
1073 	}
1074 
1075 	SStream_concat0(O, "]");
1076 	set_mem_access(MI, false);
1077 }
1078 
printAddrMode3Operand(MCInst * MI,unsigned Op,SStream * O,bool AlwaysPrintImm0)1079 static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
1080 		bool AlwaysPrintImm0)
1081 {
1082 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
1083 	if (!MCOperand_isReg(MO1)) {   //  For label symbolic references.
1084 		printOperand(MI, Op, O);
1085 		return;
1086 	}
1087 
1088 	printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
1089 }
1090 
printAddrMode3OffsetOperand(MCInst * MI,unsigned OpNum,SStream * O)1091 static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
1092 {
1093 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1094 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1095 	ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2));
1096 	unsigned ImmOffs;
1097 
1098 	if (MCOperand_getReg(MO1)) {
1099 		SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
1100 		printRegName(MI->csh, O, MCOperand_getReg(MO1));
1101 		if (MI->csh->detail) {
1102 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1103 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1104 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
1105 			MI->flat_insn->detail->arm.op_count++;
1106 		}
1107 		return;
1108 	}
1109 
1110 	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
1111 	if (ImmOffs > HEX_THRESHOLD)
1112 		SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1113 	else
1114 		SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
1115 	if (MI->csh->detail) {
1116 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1117 
1118 		if (subtracted) {
1119 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1120 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
1121 		} else
1122 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
1123 
1124 		MI->flat_insn->detail->arm.op_count++;
1125 	}
1126 }
1127 
printPostIdxImm8Operand(MCInst * MI,unsigned OpNum,SStream * O)1128 static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
1129 {
1130 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
1131 	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
1132 	if ((Imm & 0xff) > HEX_THRESHOLD)
1133 		SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1134 	else
1135 		SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1136 	if (MI->csh->detail) {
1137 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1138 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
1139 		MI->flat_insn->detail->arm.op_count++;
1140 	}
1141 }
1142 
printPostIdxRegOperand(MCInst * MI,unsigned OpNum,SStream * O)1143 static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
1144 {
1145 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1146 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1147 
1148 	SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
1149 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1150 	if (MI->csh->detail) {
1151 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1152 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
1153 		MI->flat_insn->detail->arm.op_count++;
1154 	}
1155 }
1156 
printPostIdxImm8s4Operand(MCInst * MI,unsigned OpNum,SStream * O)1157 static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
1158 {
1159 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
1160 	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
1161 
1162 	if (((Imm & 0xff) << 2) > HEX_THRESHOLD) {
1163 		SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1164 	} else {
1165 		SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1166 	}
1167 
1168 	if (MI->csh->detail) {
1169 		int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((((int)Imm) & 0xff) << 2);
1170 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1171 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
1172 		MI->flat_insn->detail->arm.op_count++;
1173 	}
1174 }
1175 
printAddrMode5Operand(MCInst * MI,unsigned OpNum,SStream * O,bool AlwaysPrintImm0)1176 static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
1177 		bool AlwaysPrintImm0)
1178 {
1179 	unsigned ImmOffs;
1180 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1181 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1182 	ARM_AM_AddrOpc subtracted = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
1183 
1184 	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1185 		printOperand(MI, OpNum, O);
1186 		return;
1187 	}
1188 
1189 	SStream_concat0(O, "[");
1190 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1191 
1192 	if (MI->csh->detail) {
1193 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
1194 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1195 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
1196 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
1197 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
1198 	}
1199 
1200 	ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
1201 	if (AlwaysPrintImm0 || ImmOffs || subtracted == ARM_AM_sub) {
1202 		if (ImmOffs * 4 > HEX_THRESHOLD)
1203 			SStream_concat(O, ", #%s0x%x",
1204 					ARM_AM_getAddrOpcStr(subtracted),
1205 					ImmOffs * 4);
1206 		else
1207 			SStream_concat(O, ", #%s%u",
1208 					ARM_AM_getAddrOpcStr(subtracted),
1209 					ImmOffs * 4);
1210 		if (MI->csh->detail) {
1211 			if (subtracted)
1212 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
1213 			else
1214 				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4;
1215 		}
1216 	}
1217 	SStream_concat0(O, "]");
1218 
1219 	if (MI->csh->detail) {
1220 		MI->flat_insn->detail->arm.op_count++;
1221 	}
1222 }
1223 
printAddrMode6Operand(MCInst * MI,unsigned OpNum,SStream * O)1224 static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
1225 {
1226 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1227 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1228 	unsigned tmp;
1229 
1230 	SStream_concat0(O, "[");
1231 	set_mem_access(MI, true);
1232 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1233 	if (MI->csh->detail)
1234 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1235 	tmp = (unsigned int)MCOperand_getImm(MO2);
1236 	if (tmp) {
1237 		if (tmp << 3 > HEX_THRESHOLD)
1238 			SStream_concat(O, ":0x%x", (tmp << 3));
1239 		else
1240 			SStream_concat(O, ":%u", (tmp << 3));
1241 		if (MI->csh->detail)
1242 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
1243 	}
1244 	SStream_concat0(O, "]");
1245 	set_mem_access(MI, false);
1246 }
1247 
printAddrMode7Operand(MCInst * MI,unsigned OpNum,SStream * O)1248 static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
1249 {
1250 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1251 	SStream_concat0(O, "[");
1252 	set_mem_access(MI, true);
1253 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1254 	if (MI->csh->detail)
1255 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1256 	SStream_concat0(O, "]");
1257 	set_mem_access(MI, false);
1258 }
1259 
printAddrMode6OffsetOperand(MCInst * MI,unsigned OpNum,SStream * O)1260 static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
1261 {
1262 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
1263 	if (MCOperand_getReg(MO) == 0) {
1264 		MI->writeback = true;
1265 		SStream_concat0(O, "!");
1266 	} else {
1267 		SStream_concat0(O, ", ");
1268 		printRegName(MI->csh, O, MCOperand_getReg(MO));
1269 		if (MI->csh->detail) {
1270 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1271 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
1272 			MI->flat_insn->detail->arm.op_count++;
1273 		}
1274 	}
1275 }
1276 
printBitfieldInvMaskImmOperand(MCInst * MI,unsigned OpNum,SStream * O)1277 static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1278 {
1279 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
1280 	uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
1281 	int32_t lsb = CountTrailingZeros_32(v);
1282 	int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
1283 
1284 	//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
1285 	if (lsb > HEX_THRESHOLD)
1286 		SStream_concat(O, "#0x%x", lsb);
1287 	else
1288 		SStream_concat(O, "#%u", lsb);
1289 
1290 	if (width > HEX_THRESHOLD)
1291 		SStream_concat(O, ", #0x%x", width);
1292 	else
1293 		SStream_concat(O, ", #%u", width);
1294 
1295 	if (MI->csh->detail) {
1296 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1297 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
1298 		MI->flat_insn->detail->arm.op_count++;
1299 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1300 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
1301 		MI->flat_insn->detail->arm.op_count++;
1302 	}
1303 }
1304 
printMemBOption(MCInst * MI,unsigned OpNum,SStream * O)1305 static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
1306 {
1307 	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1308 	SStream_concat0(O, ARM_MB_MemBOptToString(val + 1,
1309 				(ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops) != 0));
1310 
1311 	if (MI->csh->detail) {
1312 		MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1);
1313 	}
1314 }
1315 
printInstSyncBOption(MCInst * MI,unsigned OpNum,SStream * O)1316 void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
1317 {
1318 	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1319 	SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
1320 }
1321 
printShiftImmOperand(MCInst * MI,unsigned OpNum,SStream * O)1322 static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1323 {
1324 	unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1325 	bool isASR = (ShiftOp & (1 << 5)) != 0;
1326 	unsigned Amt = ShiftOp & 0x1f;
1327 	if (isASR) {
1328 		unsigned tmp = Amt == 0 ? 32 : Amt;
1329 		if (tmp > HEX_THRESHOLD)
1330 			SStream_concat(O, ", asr #0x%x", tmp);
1331 		else
1332 			SStream_concat(O, ", asr #%u", tmp);
1333 		if (MI->csh->detail) {
1334 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
1335 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
1336 		}
1337 	} else if (Amt) {
1338 		if (Amt > HEX_THRESHOLD)
1339 			SStream_concat(O, ", lsl #0x%x", Amt);
1340 		else
1341 			SStream_concat(O, ", lsl #%u", Amt);
1342 		if (MI->csh->detail) {
1343 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
1344 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
1345 		}
1346 	}
1347 }
1348 
printPKHLSLShiftImm(MCInst * MI,unsigned OpNum,SStream * O)1349 static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
1350 {
1351 	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1352 	if (Imm == 0)
1353 		return;
1354 	//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
1355 	if (Imm > HEX_THRESHOLD)
1356 		SStream_concat(O, ", lsl #0x%x", Imm);
1357 	else
1358 		SStream_concat(O, ", lsl #%u", Imm);
1359 	if (MI->csh->detail) {
1360 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
1361 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1362 	}
1363 }
1364 
printPKHASRShiftImm(MCInst * MI,unsigned OpNum,SStream * O)1365 static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
1366 {
1367 	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1368 	// A shift amount of 32 is encoded as 0.
1369 	if (Imm == 0)
1370 		Imm = 32;
1371 	//assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
1372 	if (Imm > HEX_THRESHOLD)
1373 		SStream_concat(O, ", asr #0x%x", Imm);
1374 	else
1375 		SStream_concat(O, ", asr #%u", Imm);
1376 	if (MI->csh->detail) {
1377 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
1378 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1379 	}
1380 }
1381 
1382 // FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
printRegisterList(MCInst * MI,unsigned OpNum,SStream * O)1383 static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
1384 {
1385 	unsigned i, e;
1386 	SStream_concat0(O, "{");
1387 	for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
1388 		if (i != OpNum) SStream_concat0(O, ", ");
1389 		printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
1390 		if (MI->csh->detail) {
1391 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1392 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
1393 			MI->flat_insn->detail->arm.op_count++;
1394 		}
1395 	}
1396 	SStream_concat0(O, "}");
1397 }
1398 
printGPRPairOperand(MCInst * MI,unsigned OpNum,SStream * O,MCRegisterInfo * MRI)1399 static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O,
1400 		MCRegisterInfo *MRI)
1401 {
1402 	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
1403 	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
1404 	if (MI->csh->detail) {
1405 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1406 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
1407 		MI->flat_insn->detail->arm.op_count++;
1408 	}
1409 	SStream_concat0(O, ", ");
1410 	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
1411 	if (MI->csh->detail) {
1412 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1413 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
1414 		MI->flat_insn->detail->arm.op_count++;
1415 	}
1416 }
1417 
1418 // SETEND BE/LE
printSetendOperand(MCInst * MI,unsigned OpNum,SStream * O)1419 static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
1420 {
1421 	MCOperand *Op = MCInst_getOperand(MI, OpNum);
1422 	if (MCOperand_getImm(Op)) {
1423 		SStream_concat0(O, "be");
1424 		if (MI->csh->detail) {
1425 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
1426 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE;
1427 			MI->flat_insn->detail->arm.op_count++;
1428 		}
1429 	} else {
1430 		SStream_concat0(O, "le");
1431 		if (MI->csh->detail) {
1432 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
1433 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE;
1434 			MI->flat_insn->detail->arm.op_count++;
1435 		}
1436 	}
1437 }
1438 
printCPSIMod(MCInst * MI,unsigned OpNum,SStream * O)1439 static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
1440 {
1441 	MCOperand *Op = MCInst_getOperand(MI, OpNum);
1442 	unsigned int mode = (unsigned int)MCOperand_getImm(Op);
1443 
1444 	SStream_concat0(O, ARM_PROC_IModToString(mode));
1445 
1446 	if (MI->csh->detail) {
1447 		MI->flat_insn->detail->arm.cps_mode = mode;
1448 	}
1449 }
1450 
printCPSIFlag(MCInst * MI,unsigned OpNum,SStream * O)1451 static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
1452 {
1453 	MCOperand *Op = MCInst_getOperand(MI, OpNum);
1454 	unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
1455 	int i;
1456 
1457 	for (i = 2; i >= 0; --i)
1458 		if (IFlags & (1 << i)) {
1459 			SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
1460 		}
1461 
1462 	if (IFlags == 0) {
1463 		SStream_concat0(O, "none");
1464 		IFlags = ARM_CPSFLAG_NONE;
1465 	}
1466 
1467 	if (MI->csh->detail) {
1468 		MI->flat_insn->detail->arm.cps_flag = IFlags;
1469 	}
1470 }
1471 
printMSRMaskOperand(MCInst * MI,unsigned OpNum,SStream * O)1472 static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
1473 {
1474 	MCOperand *Op = MCInst_getOperand(MI, OpNum);
1475 	unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
1476 	unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf;
1477 	unsigned reg;
1478 
1479 	if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
1480 		unsigned SYSm = (unsigned)MCOperand_getImm(Op);
1481 		unsigned Opcode = MCInst_getOpcode(MI);
1482 		// For reads of the special registers ignore the "mask encoding" bits
1483 		// which are only for writes.
1484 		if (Opcode == ARM_t2MRS_M)
1485 			SYSm &= 0xff;
1486 		switch (SYSm) {
1487 			default: //llvm_unreachable("Unexpected mask value!");
1488 			case     0:
1489 			case 0x800: SStream_concat0(O, "apsr"); ARM_addSysReg(MI, ARM_SYSREG_APSR); return; // with _nzcvq bits is an alias for aspr
1490 			case 0x400: SStream_concat0(O, "apsr_g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
1491 			case 0xc00: SStream_concat0(O, "apsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
1492 			case     1:
1493 			case 0x801: SStream_concat0(O, "iapsr"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR); return; // with _nzcvq bits is an alias for iapsr
1494 			case 0x401: SStream_concat0(O, "iapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_G); return;
1495 			case 0xc01: SStream_concat0(O, "iapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_IAPSR_NZCVQG); return;
1496 			case     2:
1497 			case 0x802: SStream_concat0(O, "eapsr"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR); return; // with _nzcvq bits is an alias for eapsr
1498 			case 0x402: SStream_concat0(O, "eapsr_g"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_G); return;
1499 			case 0xc02: SStream_concat0(O, "eapsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_EAPSR_NZCVQG); return;
1500 			case     3:
1501 			case 0x803: SStream_concat0(O, "xpsr"); ARM_addSysReg(MI, ARM_SYSREG_XPSR); return; // with _nzcvq bits is an alias for xpsr
1502 			case 0x403: SStream_concat0(O, "xpsr_g"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_G); return;
1503 			case 0xc03: SStream_concat0(O, "xpsr_nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_XPSR_NZCVQG); return;
1504 			case     5:
1505 			case 0x805: SStream_concat0(O, "ipsr"); ARM_addSysReg(MI, ARM_SYSREG_IPSR); return;
1506 			case     6:
1507 			case 0x806: SStream_concat0(O, "epsr"); ARM_addSysReg(MI, ARM_SYSREG_EPSR); return;
1508 			case     7:
1509 			case 0x807: SStream_concat0(O, "iepsr"); ARM_addSysReg(MI, ARM_SYSREG_IEPSR); return;
1510 			case     8:
1511 			case 0x808: SStream_concat0(O, "msp"); ARM_addSysReg(MI, ARM_SYSREG_MSP); return;
1512 			case     9:
1513 			case 0x809: SStream_concat0(O, "psp"); ARM_addSysReg(MI, ARM_SYSREG_PSP); return;
1514 			case  0x10:
1515 			case 0x810: SStream_concat0(O, "primask"); ARM_addSysReg(MI, ARM_SYSREG_PRIMASK); return;
1516 			case  0x11:
1517 			case 0x811: SStream_concat0(O, "basepri"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI); return;
1518 			case  0x12:
1519 			case 0x812: SStream_concat0(O, "basepri_max"); ARM_addSysReg(MI, ARM_SYSREG_BASEPRI_MAX); return;
1520 			case  0x13:
1521 			case 0x813: SStream_concat0(O, "faultmask"); ARM_addSysReg(MI, ARM_SYSREG_FAULTMASK); return;
1522 			case  0x14:
1523 			case 0x814: SStream_concat0(O, "control"); ARM_addSysReg(MI, ARM_SYSREG_CONTROL); return;
1524 		}
1525 	}
1526 
1527 	// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
1528 	// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
1529 	if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
1530 		SStream_concat0(O, "apsr_");
1531 		switch (Mask) {
1532 			default: // llvm_unreachable("Unexpected mask value!");
1533 			case 4:  SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
1534 			case 8:  SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
1535 			case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
1536 		}
1537 	}
1538 
1539 	reg = 0;
1540 	if (SpecRegRBit) {
1541 		SStream_concat0(O, "spsr");
1542 		if (Mask) {
1543 			SStream_concat0(O, "_");
1544 			if (Mask & 8) {
1545 				SStream_concat0(O, "f");
1546 				reg += ARM_SYSREG_SPSR_F;
1547 			}
1548 
1549 			if (Mask & 4) {
1550 				SStream_concat0(O, "s");
1551 				reg += ARM_SYSREG_SPSR_S;
1552 			}
1553 
1554 			if (Mask & 2) {
1555 				SStream_concat0(O, "x");
1556 				reg += ARM_SYSREG_SPSR_X;
1557 			}
1558 
1559 			if (Mask & 1) {
1560 				SStream_concat0(O, "c");
1561 				reg += ARM_SYSREG_SPSR_C;
1562 			}
1563 			ARM_addSysReg(MI, reg);
1564 		}
1565 	} else {
1566 		SStream_concat0(O, "cpsr");
1567 		if (Mask) {
1568 			SStream_concat0(O, "_");
1569 			if (Mask & 8) {
1570 				SStream_concat0(O, "f");
1571 				reg += ARM_SYSREG_CPSR_F;
1572 			}
1573 
1574 			if (Mask & 4) {
1575 				SStream_concat0(O, "s");
1576 				reg += ARM_SYSREG_CPSR_S;
1577 			}
1578 
1579 			if (Mask & 2) {
1580 				SStream_concat0(O, "x");
1581 				reg += ARM_SYSREG_CPSR_X;
1582 			}
1583 
1584 			if (Mask & 1) {
1585 				SStream_concat0(O, "c");
1586 				reg += ARM_SYSREG_CPSR_C;
1587 			}
1588 			ARM_addSysReg(MI, reg);
1589 		}
1590 	}
1591 }
1592 
printPredicateOperand(MCInst * MI,unsigned OpNum,SStream * O)1593 static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
1594 {
1595 	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1596 	// Handle the undefined 15 CC value here for printing so we don't abort().
1597 	if ((unsigned)CC == 15) {
1598 		SStream_concat0(O, "<und>");
1599 		if (MI->csh->detail)
1600 			MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
1601 	} else {
1602 		if (CC != ARMCC_AL) {
1603 			SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
1604 		}
1605 		if (MI->csh->detail)
1606 			MI->flat_insn->detail->arm.cc = CC + 1;
1607 	}
1608 }
1609 
1610 // TODO: test this
printMandatoryPredicateOperand(MCInst * MI,unsigned OpNum,SStream * O)1611 static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
1612 {
1613 	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1614 	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
1615 	if (MI->csh->detail)
1616 		MI->flat_insn->detail->arm.cc = CC + 1;
1617 }
1618 
printSBitModifierOperand(MCInst * MI,unsigned OpNum,SStream * O)1619 static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
1620 {
1621 	if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
1622 		//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
1623 		//       "Expect ARM CPSR register!");
1624 		SStream_concat0(O, "s");
1625 		if (MI->csh->detail)
1626 			MI->flat_insn->detail->arm.update_flags = true;
1627 	}
1628 }
1629 
printNoHashImmediate(MCInst * MI,unsigned OpNum,SStream * O)1630 static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1631 {
1632 	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1633 	if (tmp > HEX_THRESHOLD)
1634 		SStream_concat(O, "0x%x", tmp);
1635 	else
1636 		SStream_concat(O, "%u", tmp);
1637 	if (MI->csh->detail) {
1638 		if (MI->csh->doing_mem) {
1639 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
1640 		} else {
1641 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1642 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1643 			MI->flat_insn->detail->arm.op_count++;
1644 		}
1645 	}
1646 }
1647 
printPImmediate(MCInst * MI,unsigned OpNum,SStream * O)1648 static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1649 {
1650 	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1651 
1652 	SStream_concat(O, "p%u", imm);
1653 	if (MI->csh->detail) {
1654 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
1655 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1656 		MI->flat_insn->detail->arm.op_count++;
1657 	}
1658 }
1659 
printCImmediate(MCInst * MI,unsigned OpNum,SStream * O)1660 static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
1661 {
1662 	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1663 
1664 	SStream_concat(O, "c%u", imm);
1665 	if (MI->csh->detail) {
1666 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
1667 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1668 		MI->flat_insn->detail->arm.op_count++;
1669 	}
1670 }
1671 
printCoprocOptionImm(MCInst * MI,unsigned OpNum,SStream * O)1672 static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
1673 {
1674 	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1675 	if (tmp > HEX_THRESHOLD)
1676 		SStream_concat(O, "{0x%x}", tmp);
1677 	else
1678 		SStream_concat(O, "{%u}", tmp);
1679 	if (MI->csh->detail) {
1680 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1681 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1682 		MI->flat_insn->detail->arm.op_count++;
1683 	}
1684 }
1685 
printAdrLabelOperand(MCInst * MI,unsigned OpNum,SStream * O,unsigned scale)1686 static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale)
1687 {
1688 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
1689 
1690 	int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
1691 
1692 	if (OffImm == INT32_MIN) {
1693 		SStream_concat0(O, "#-0");
1694 		if (MI->csh->detail) {
1695 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1696 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
1697 			MI->flat_insn->detail->arm.op_count++;
1698 		}
1699 	} else {
1700 		if (OffImm < 0)
1701 			SStream_concat(O, "#-0x%x", -OffImm);
1702 		else {
1703 			if (OffImm > HEX_THRESHOLD)
1704 				SStream_concat(O, "#0x%x", OffImm);
1705 			else
1706 				SStream_concat(O, "#%u", OffImm);
1707 		}
1708 		if (MI->csh->detail) {
1709 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1710 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
1711 			MI->flat_insn->detail->arm.op_count++;
1712 		}
1713 	}
1714 }
1715 
printThumbS4ImmOperand(MCInst * MI,unsigned OpNum,SStream * O)1716 static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
1717 {
1718 	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
1719 	if (tmp > HEX_THRESHOLD)
1720 		SStream_concat(O, "#0x%x", tmp);
1721 	else
1722 		SStream_concat(O, "#%u", tmp);
1723 	if (MI->csh->detail) {
1724 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1725 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1726 		MI->flat_insn->detail->arm.op_count++;
1727 	}
1728 }
1729 
printThumbSRImm(MCInst * MI,unsigned OpNum,SStream * O)1730 static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
1731 {
1732 	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1733 	unsigned tmp = Imm == 0 ? 32 : Imm;
1734 	if (tmp > HEX_THRESHOLD)
1735 		SStream_concat(O, "#0x%x", tmp);
1736 	else
1737 		SStream_concat(O, "#%u", tmp);
1738 
1739 	if (MI->csh->detail) {
1740 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
1741 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1742 		MI->flat_insn->detail->arm.op_count++;
1743 	}
1744 }
1745 
printThumbITMask(MCInst * MI,unsigned OpNum,SStream * O)1746 static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
1747 {
1748 	// (3 - the number of trailing zeros) is the number of then / else.
1749 	unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1750 	unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
1751 	unsigned CondBit0 = Firstcond & 1;
1752 	unsigned NumTZ = CountTrailingZeros_32(Mask);
1753 	//assert(NumTZ <= 3 && "Invalid IT mask!");
1754 	unsigned Pos, e;
1755 	for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
1756 		bool T = ((Mask >> Pos) & 1) == CondBit0;
1757 		if (T)
1758 			SStream_concat0(O, "t");
1759 		else
1760 			SStream_concat0(O, "e");
1761 	}
1762 }
1763 
printThumbAddrModeRROperand(MCInst * MI,unsigned Op,SStream * O)1764 static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
1765 {
1766 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
1767 	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
1768 	unsigned RegNum;
1769 
1770 	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1771 		printOperand(MI, Op, O);
1772 		return;
1773 	}
1774 
1775 	SStream_concat0(O, "[");
1776 	set_mem_access(MI, true);
1777 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1778 	if (MI->csh->detail)
1779 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1780 	RegNum = MCOperand_getReg(MO2);
1781 	if (RegNum) {
1782 		SStream_concat0(O, ", ");
1783 		printRegName(MI->csh, O, RegNum);
1784 		if (MI->csh->detail)
1785 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
1786 	}
1787 	SStream_concat0(O, "]");
1788 	set_mem_access(MI, false);
1789 }
1790 
printThumbAddrModeImm5SOperand(MCInst * MI,unsigned Op,SStream * O,unsigned Scale)1791 static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
1792 		unsigned Scale)
1793 {
1794 	MCOperand *MO1 = MCInst_getOperand(MI, Op);
1795 	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
1796 	unsigned ImmOffs, tmp;
1797 
1798 	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1799 		printOperand(MI, Op, O);
1800 		return;
1801 	}
1802 
1803 	SStream_concat0(O, "[");
1804 	set_mem_access(MI, true);
1805 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1806 	if (MI->csh->detail)
1807 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1808 	ImmOffs = (unsigned int)MCOperand_getImm(MO2);
1809 	if (ImmOffs) {
1810 		tmp = ImmOffs * Scale;
1811 		SStream_concat0(O, ", ");
1812 		if (tmp > HEX_THRESHOLD)
1813 			SStream_concat(O, "#0x%x", tmp);
1814 		else
1815 			SStream_concat(O, "#%u", tmp);
1816 		if (MI->csh->detail)
1817 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
1818 	}
1819 	SStream_concat0(O, "]");
1820 	set_mem_access(MI, false);
1821 }
1822 
printThumbAddrModeImm5S1Operand(MCInst * MI,unsigned Op,SStream * O)1823 static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O)
1824 {
1825 	printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1826 }
1827 
printThumbAddrModeImm5S2Operand(MCInst * MI,unsigned Op,SStream * O)1828 static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O)
1829 {
1830 	printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1831 }
1832 
printThumbAddrModeImm5S4Operand(MCInst * MI,unsigned Op,SStream * O)1833 static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O)
1834 {
1835 	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1836 }
1837 
printThumbAddrModeSPOperand(MCInst * MI,unsigned Op,SStream * O)1838 static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
1839 {
1840 	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1841 }
1842 
1843 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1844 // register with shift forms.
1845 // REG 0   0           - e.g. R5
1846 // REG IMM, SH_OPC     - e.g. R5, LSL #3
printT2SOOperand(MCInst * MI,unsigned OpNum,SStream * O)1847 static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
1848 {
1849 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1850 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1851 
1852 	unsigned Reg = MCOperand_getReg(MO1);
1853 	printRegName(MI->csh, O, Reg);
1854 	if (MI->csh->detail) {
1855 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
1856 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
1857 		MI->flat_insn->detail->arm.op_count++;
1858 	}
1859 
1860 	// Print the shift opc.
1861 	//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1862 	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
1863 			getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
1864 }
1865 
printAddrModeImm12Operand(MCInst * MI,unsigned OpNum,SStream * O,bool AlwaysPrintImm0)1866 static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
1867 		SStream *O, bool AlwaysPrintImm0)
1868 {
1869 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1870 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1871 	int32_t OffImm;
1872 	bool isSub;
1873 
1874 	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
1875 		printOperand(MI, OpNum, O);
1876 		return;
1877 	}
1878 
1879 	SStream_concat0(O, "[");
1880 	set_mem_access(MI, true);
1881 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1882 
1883 	if (MI->csh->detail)
1884 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1885 
1886 	OffImm = (int32_t)MCOperand_getImm(MO2);
1887 	isSub = OffImm < 0;
1888 	// Special value for #-0. All others are normal.
1889 	if (OffImm == INT32_MIN)
1890 		OffImm = 0;
1891 	if (isSub) {
1892 		if (OffImm < -HEX_THRESHOLD)
1893 			SStream_concat(O, ", #-0x%x", -OffImm);
1894 		else
1895 			SStream_concat(O, ", #-%u", -OffImm);
1896 	} else if (AlwaysPrintImm0 || OffImm > 0) {
1897 		if (OffImm >= 0) {
1898 			if (OffImm > HEX_THRESHOLD)
1899 				SStream_concat(O, ", #0x%x", OffImm);
1900 			else
1901 				SStream_concat(O, ", #%u", OffImm);
1902 		} else {
1903 			if (OffImm < -HEX_THRESHOLD)
1904 				SStream_concat(O, ", #-0x%x", -OffImm);
1905 			else
1906 				SStream_concat(O, ", #-%u", -OffImm);
1907 		}
1908 	}
1909 	if (MI->csh->detail)
1910 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
1911 	SStream_concat0(O, "]");
1912 	set_mem_access(MI, false);
1913 }
1914 
printT2AddrModeImm8Operand(MCInst * MI,unsigned OpNum,SStream * O,bool AlwaysPrintImm0)1915 static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
1916 		bool AlwaysPrintImm0)
1917 {
1918 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1919 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1920 	int32_t OffImm;
1921 	bool isSub;
1922 
1923 	SStream_concat0(O, "[");
1924 	set_mem_access(MI, true);
1925 
1926 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1927 	if (MI->csh->detail)
1928 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1929 
1930 	OffImm = (int32_t)MCOperand_getImm(MO2);
1931 	isSub = OffImm < 0;
1932 	// Don't print +0.
1933 	if (OffImm == INT32_MIN)
1934 		OffImm = 0;
1935 
1936 	if (isSub)
1937 		SStream_concat(O, ", #-0x%x", -OffImm);
1938 	else if (AlwaysPrintImm0 || OffImm > 0) {
1939 		if (OffImm > HEX_THRESHOLD)
1940 			SStream_concat(O, ", #0x%x", OffImm);
1941 		else
1942 			SStream_concat(O, ", #%u", OffImm);
1943 	}
1944 
1945 	if (MI->csh->detail)
1946 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
1947 	SStream_concat0(O, "]");
1948 	set_mem_access(MI, false);
1949 }
1950 
printT2AddrModeImm8s4Operand(MCInst * MI,unsigned OpNum,SStream * O,bool AlwaysPrintImm0)1951 static void printT2AddrModeImm8s4Operand(MCInst *MI,
1952 		unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
1953 {
1954 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1955 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1956 	int32_t OffImm;
1957 	bool isSub;
1958 
1959 	if (!MCOperand_isReg(MO1)) {   //  For label symbolic references.
1960 		printOperand(MI, OpNum, O);
1961 		return;
1962 	}
1963 
1964 	SStream_concat0(O, "[");
1965 	set_mem_access(MI, true);
1966 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
1967 	if (MI->csh->detail)
1968 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
1969 
1970 	OffImm = (int32_t)MCOperand_getImm(MO2);
1971 	isSub = OffImm < 0;
1972 
1973 	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1974 
1975 	// Don't print +0.
1976 	if (OffImm == INT32_MIN)
1977 		OffImm = 0;
1978 	if (isSub) {
1979 		SStream_concat(O, ", #-0x%x", -OffImm);
1980 	} else if (AlwaysPrintImm0 || OffImm > 0) {
1981 		if (OffImm > HEX_THRESHOLD)
1982 			SStream_concat(O, ", #0x%x", OffImm);
1983 		else
1984 			SStream_concat(O, ", #%u", OffImm);
1985 	}
1986 	if (MI->csh->detail)
1987 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
1988 
1989 	SStream_concat0(O, "]");
1990 	set_mem_access(MI, false);
1991 }
1992 
printT2AddrModeImm0_1020s4Operand(MCInst * MI,unsigned OpNum,SStream * O)1993 static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
1994 {
1995 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
1996 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
1997 	unsigned tmp;
1998 
1999 	SStream_concat0(O, "[");
2000 	set_mem_access(MI, true);
2001 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
2002 	if (MI->csh->detail)
2003 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2004 	if (MCOperand_getImm(MO2)) {
2005 		SStream_concat0(O, ", ");
2006 		tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
2007 		if (tmp > HEX_THRESHOLD)
2008 			SStream_concat(O, "#0x%x", tmp);
2009 		else
2010 			SStream_concat(O, "#%u", tmp);
2011 		if (MI->csh->detail)
2012 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
2013 	}
2014 	SStream_concat0(O, "]");
2015 	set_mem_access(MI, false);
2016 }
2017 
printT2AddrModeImm8OffsetOperand(MCInst * MI,unsigned OpNum,SStream * O)2018 static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
2019 		unsigned OpNum, SStream *O)
2020 {
2021 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2022 	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
2023 	SStream_concat0(O, ", ");
2024 	if (OffImm == INT32_MIN) {
2025 		SStream_concat0(O, "#-0");
2026 		if (MI->csh->detail) {
2027 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2028 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2029 			MI->flat_insn->detail->arm.op_count++;
2030 		}
2031 	} else {
2032 		if (OffImm < 0) {
2033 			if (OffImm < -HEX_THRESHOLD)
2034 				SStream_concat(O, "#-0x%x", -OffImm);
2035 			else
2036 				SStream_concat(O, "#-%u", -OffImm);
2037 		} else {
2038 			if (OffImm > HEX_THRESHOLD)
2039 				SStream_concat(O, "#0x%x", OffImm);
2040 			else
2041 				SStream_concat(O, "#%u", OffImm);
2042 		}
2043 		if (MI->csh->detail) {
2044 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2045 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2046 			MI->flat_insn->detail->arm.op_count++;
2047 		}
2048 	}
2049 }
2050 
printT2AddrModeImm8s4OffsetOperand(MCInst * MI,unsigned OpNum,SStream * O)2051 static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
2052 		unsigned OpNum, SStream *O)
2053 {
2054 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2055 	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
2056 
2057 	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
2058 
2059 	SStream_concat0(O, ", ");
2060 	if (OffImm == INT32_MIN) {
2061 		SStream_concat0(O, "#-0");
2062 		if (MI->csh->detail) {
2063 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2064 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2065 			MI->flat_insn->detail->arm.op_count++;
2066 		}
2067 	} else {
2068 		if (OffImm < 0) {
2069 			if (OffImm < -HEX_THRESHOLD)
2070 				SStream_concat(O, "#-0x%x", -OffImm);
2071 			else
2072 				SStream_concat(O, "#-%u", -OffImm);
2073 		} else {
2074 			if (OffImm > HEX_THRESHOLD)
2075 				SStream_concat(O, "#0x%x", OffImm);
2076 			else
2077 				SStream_concat(O, "#%u", OffImm);
2078 		}
2079 		if (MI->csh->detail) {
2080 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2081 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2082 			MI->flat_insn->detail->arm.op_count++;
2083 		}
2084 	}
2085 }
2086 
printT2AddrModeSoRegOperand(MCInst * MI,unsigned OpNum,SStream * O)2087 static void printT2AddrModeSoRegOperand(MCInst *MI,
2088 		unsigned OpNum, SStream *O)
2089 {
2090 	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
2091 	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
2092 	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
2093 	unsigned ShAmt;
2094 
2095 	SStream_concat0(O, "[");
2096 	set_mem_access(MI, true);
2097 	printRegName(MI->csh, O, MCOperand_getReg(MO1));
2098 	if (MI->csh->detail)
2099 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
2100 
2101 	//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
2102 	SStream_concat0(O, ", ");
2103 	printRegName(MI->csh, O, MCOperand_getReg(MO2));
2104 	if (MI->csh->detail)
2105 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
2106 
2107 	ShAmt = (unsigned int)MCOperand_getImm(MO3);
2108 	if (ShAmt) {
2109 		//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
2110 		SStream_concat0(O, ", lsl ");
2111 		SStream_concat(O, "#%d", ShAmt);
2112 		if (MI->csh->detail) {
2113 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
2114 			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;
2115 		}
2116 	}
2117 
2118 	SStream_concat0(O, "]");
2119 	set_mem_access(MI, false);
2120 }
2121 
printFPImmOperand(MCInst * MI,unsigned OpNum,SStream * O)2122 static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2123 {
2124 	MCOperand *MO = MCInst_getOperand(MI, OpNum);
2125 
2126 #if defined(_KERNEL_MODE)
2127 	// Issue #681: Windows kernel does not support formatting float point
2128 	SStream_concat(O, "#<float_point_unsupported>");
2129 #else
2130 	SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
2131 #endif
2132 	if (MI->csh->detail) {
2133 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
2134 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
2135 		MI->flat_insn->detail->arm.op_count++;
2136 	}
2137 }
2138 
printNEONModImmOperand(MCInst * MI,unsigned OpNum,SStream * O)2139 static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2140 {
2141 	unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2142 	unsigned EltBits;
2143 	uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
2144 	if (Val > HEX_THRESHOLD)
2145 		SStream_concat(O, "#0x%"PRIx64, Val);
2146 	else
2147 		SStream_concat(O, "#%"PRIu64, Val);
2148 	if (MI->csh->detail) {
2149 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2150 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
2151 		MI->flat_insn->detail->arm.op_count++;
2152 	}
2153 }
2154 
printImmPlusOneOperand(MCInst * MI,unsigned OpNum,SStream * O)2155 static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
2156 {
2157 	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2158 	if (Imm + 1 > HEX_THRESHOLD)
2159 		SStream_concat(O, "#0x%x", Imm + 1);
2160 	else
2161 		SStream_concat(O, "#%u", Imm + 1);
2162 	if (MI->csh->detail) {
2163 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2164 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
2165 		MI->flat_insn->detail->arm.op_count++;
2166 	}
2167 }
2168 
printRotImmOperand(MCInst * MI,unsigned OpNum,SStream * O)2169 static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
2170 {
2171 	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2172 	if (Imm == 0)
2173 		return;
2174 	SStream_concat0(O, ", ror #");
2175 	switch (Imm) {
2176 		default: //assert (0 && "illegal ror immediate!");
2177 		case 1: SStream_concat0(O, "8"); break;
2178 		case 2: SStream_concat0(O, "16"); break;
2179 		case 3: SStream_concat0(O, "24"); break;
2180 	}
2181 	if (MI->csh->detail) {
2182 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
2183 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
2184 	}
2185 }
2186 
printFBits16(MCInst * MI,unsigned OpNum,SStream * O)2187 static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
2188 {
2189 	unsigned tmp;
2190 
2191 	tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2192 	if (tmp > HEX_THRESHOLD)
2193 		SStream_concat(O, "#0x%x", tmp);
2194 	else
2195 		SStream_concat(O, "#%u", tmp);
2196 	if (MI->csh->detail) {
2197 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2198 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
2199 		MI->flat_insn->detail->arm.op_count++;
2200 	}
2201 }
2202 
printFBits32(MCInst * MI,unsigned OpNum,SStream * O)2203 static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
2204 {
2205 	unsigned tmp;
2206 
2207 	tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2208 	if (tmp > HEX_THRESHOLD)
2209 		SStream_concat(O, "#0x%x", tmp);
2210 	else
2211 		SStream_concat(O, "#%u", tmp);
2212 	if (MI->csh->detail) {
2213 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
2214 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
2215 		MI->flat_insn->detail->arm.op_count++;
2216 	}
2217 }
2218 
printVectorIndex(MCInst * MI,unsigned OpNum,SStream * O)2219 static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
2220 {
2221 	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2222 	if (tmp > HEX_THRESHOLD)
2223 		SStream_concat(O, "[0x%x]",tmp);
2224 	else
2225 		SStream_concat(O, "[%u]",tmp);
2226 	if (MI->csh->detail) {
2227 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
2228 	}
2229 }
2230 
printVectorListOne(MCInst * MI,unsigned OpNum,SStream * O)2231 static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
2232 {
2233 	SStream_concat0(O, "{");
2234 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2235 	if (MI->csh->detail) {
2236 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2237 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2238 		MI->flat_insn->detail->arm.op_count++;
2239 	}
2240 	SStream_concat0(O, "}");
2241 }
2242 
printVectorListTwo(MCInst * MI,unsigned OpNum,SStream * O,MCRegisterInfo * MRI)2243 static void printVectorListTwo(MCInst *MI, unsigned OpNum,
2244 		SStream *O, MCRegisterInfo *MRI)
2245 {
2246 	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2247 	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
2248 	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
2249 	SStream_concat0(O, "{");
2250 	printRegName(MI->csh, O, Reg0);
2251 	if (MI->csh->detail) {
2252 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2253 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2254 		MI->flat_insn->detail->arm.op_count++;
2255 	}
2256 	SStream_concat0(O, ", ");
2257 	printRegName(MI->csh, O, Reg1);
2258 	if (MI->csh->detail) {
2259 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2260 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2261 		MI->flat_insn->detail->arm.op_count++;
2262 	}
2263 	SStream_concat0(O, "}");
2264 }
2265 
printVectorListTwoSpaced(MCInst * MI,unsigned OpNum,SStream * O,MCRegisterInfo * MRI)2266 static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
2267 		SStream *O, MCRegisterInfo *MRI)
2268 {
2269 	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2270 	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
2271 	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
2272 	SStream_concat0(O, "{");
2273 	printRegName(MI->csh, O, Reg0);
2274 	if (MI->csh->detail) {
2275 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2276 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2277 		MI->flat_insn->detail->arm.op_count++;
2278 	}
2279 	SStream_concat0(O, ", ");
2280 	printRegName(MI->csh, O, Reg1);
2281 	if (MI->csh->detail) {
2282 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2283 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2284 		MI->flat_insn->detail->arm.op_count++;
2285 	}
2286 	SStream_concat0(O, "}");
2287 }
2288 
printVectorListThree(MCInst * MI,unsigned OpNum,SStream * O)2289 static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
2290 {
2291 	// Normally, it's not safe to use register enum values directly with
2292 	// addition to get the next register, but for VFP registers, the
2293 	// sort order is guaranteed because they're all of the form D<n>.
2294 	SStream_concat0(O, "{");
2295 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2296 	if (MI->csh->detail) {
2297 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2298 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2299 		MI->flat_insn->detail->arm.op_count++;
2300 	}
2301 	SStream_concat0(O, ", ");
2302 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2303 	if (MI->csh->detail) {
2304 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2305 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2306 		MI->flat_insn->detail->arm.op_count++;
2307 	}
2308 	SStream_concat0(O, ", ");
2309 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2310 	if (MI->csh->detail) {
2311 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2312 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2313 		MI->flat_insn->detail->arm.op_count++;
2314 	}
2315 	SStream_concat0(O, "}");
2316 }
2317 
printVectorListFour(MCInst * MI,unsigned OpNum,SStream * O)2318 static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
2319 {
2320 	// Normally, it's not safe to use register enum values directly with
2321 	// addition to get the next register, but for VFP registers, the
2322 	// sort order is guaranteed because they're all of the form D<n>.
2323 	SStream_concat0(O, "{");
2324 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2325 	if (MI->csh->detail) {
2326 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2327 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2328 		MI->flat_insn->detail->arm.op_count++;
2329 	}
2330 	SStream_concat0(O, ", ");
2331 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2332 	if (MI->csh->detail) {
2333 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2334 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2335 		MI->flat_insn->detail->arm.op_count++;
2336 	}
2337 	SStream_concat0(O, ", ");
2338 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2339 	if (MI->csh->detail) {
2340 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2341 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2342 		MI->flat_insn->detail->arm.op_count++;
2343 	}
2344 	SStream_concat0(O, ", ");
2345 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
2346 	if (MI->csh->detail) {
2347 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2348 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
2349 		MI->flat_insn->detail->arm.op_count++;
2350 	}
2351 	SStream_concat0(O, "}");
2352 }
2353 
printVectorListOneAllLanes(MCInst * MI,unsigned OpNum,SStream * O)2354 static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2355 {
2356 	SStream_concat0(O, "{");
2357 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2358 	if (MI->csh->detail) {
2359 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2360 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2361 		MI->flat_insn->detail->arm.op_count++;
2362 	}
2363 	SStream_concat0(O, "[]}");
2364 }
2365 
printVectorListTwoAllLanes(MCInst * MI,unsigned OpNum,SStream * O,MCRegisterInfo * MRI)2366 static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
2367 		SStream *O, MCRegisterInfo *MRI)
2368 {
2369 	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2370 	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
2371 	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
2372 	SStream_concat0(O, "{");
2373 	printRegName(MI->csh, O, Reg0);
2374 	if (MI->csh->detail) {
2375 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2376 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2377 		MI->flat_insn->detail->arm.op_count++;
2378 	}
2379 	SStream_concat0(O, "[], ");
2380 	printRegName(MI->csh, O, Reg1);
2381 	if (MI->csh->detail) {
2382 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2383 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2384 		MI->flat_insn->detail->arm.op_count++;
2385 	}
2386 	SStream_concat0(O, "[]}");
2387 }
2388 
printVectorListThreeAllLanes(MCInst * MI,unsigned OpNum,SStream * O)2389 static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2390 {
2391 	// Normally, it's not safe to use register enum values directly with
2392 	// addition to get the next register, but for VFP registers, the
2393 	// sort order is guaranteed because they're all of the form D<n>.
2394 	SStream_concat0(O, "{");
2395 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2396 	if (MI->csh->detail) {
2397 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2398 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2399 		MI->flat_insn->detail->arm.op_count++;
2400 	}
2401 	SStream_concat0(O, "[], ");
2402 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2403 	if (MI->csh->detail) {
2404 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2405 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2406 		MI->flat_insn->detail->arm.op_count++;
2407 	}
2408 	SStream_concat0(O, "[], ");
2409 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2410 	if (MI->csh->detail) {
2411 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2412 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2413 		MI->flat_insn->detail->arm.op_count++;
2414 	}
2415 	SStream_concat0(O, "[]}");
2416 }
2417 
printVectorListFourAllLanes(MCInst * MI,unsigned OpNum,SStream * O)2418 static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
2419 {
2420 	// Normally, it's not safe to use register enum values directly with
2421 	// addition to get the next register, but for VFP registers, the
2422 	// sort order is guaranteed because they're all of the form D<n>.
2423 	SStream_concat0(O, "{");
2424 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2425 	if (MI->csh->detail) {
2426 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2427 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2428 		MI->flat_insn->detail->arm.op_count++;
2429 	}
2430 	SStream_concat0(O, "[], ");
2431 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
2432 	if (MI->csh->detail) {
2433 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2434 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
2435 		MI->flat_insn->detail->arm.op_count++;
2436 	}
2437 	SStream_concat0(O, "[], ");
2438 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2439 	if (MI->csh->detail) {
2440 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2441 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2442 		MI->flat_insn->detail->arm.op_count++;
2443 	}
2444 	SStream_concat0(O, "[], ");
2445 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
2446 	if (MI->csh->detail) {
2447 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2448 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
2449 		MI->flat_insn->detail->arm.op_count++;
2450 	}
2451 	SStream_concat0(O, "[]}");
2452 }
2453 
printVectorListTwoSpacedAllLanes(MCInst * MI,unsigned OpNum,SStream * O,MCRegisterInfo * MRI)2454 static void printVectorListTwoSpacedAllLanes(MCInst *MI,
2455 		unsigned OpNum, SStream *O, MCRegisterInfo *MRI)
2456 {
2457 	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2458 	unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
2459 	unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
2460 	SStream_concat0(O, "{");
2461 	printRegName(MI->csh, O, Reg0);
2462 	if (MI->csh->detail) {
2463 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2464 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
2465 		MI->flat_insn->detail->arm.op_count++;
2466 	}
2467 	SStream_concat0(O, "[], ");
2468 	printRegName(MI->csh, O, Reg1);
2469 	if (MI->csh->detail) {
2470 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2471 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
2472 		MI->flat_insn->detail->arm.op_count++;
2473 	}
2474 	SStream_concat0(O, "[]}");
2475 }
2476 
printVectorListThreeSpacedAllLanes(MCInst * MI,unsigned OpNum,SStream * O)2477 static void printVectorListThreeSpacedAllLanes(MCInst *MI,
2478 		unsigned OpNum, SStream *O)
2479 {
2480 	// Normally, it's not safe to use register enum values directly with
2481 	// addition to get the next register, but for VFP registers, the
2482 	// sort order is guaranteed because they're all of the form D<n>.
2483 	SStream_concat0(O, "{");
2484 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2485 	if (MI->csh->detail) {
2486 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2487 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2488 		MI->flat_insn->detail->arm.op_count++;
2489 	}
2490 	SStream_concat0(O, "[], ");
2491 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2492 	if (MI->csh->detail) {
2493 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2494 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2495 		MI->flat_insn->detail->arm.op_count++;
2496 	}
2497 	SStream_concat0(O, "[], ");
2498 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
2499 	if (MI->csh->detail) {
2500 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2501 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
2502 		MI->flat_insn->detail->arm.op_count++;
2503 	}
2504 	SStream_concat0(O, "[]}");
2505 }
2506 
printVectorListFourSpacedAllLanes(MCInst * MI,unsigned OpNum,SStream * O)2507 static void printVectorListFourSpacedAllLanes(MCInst *MI,
2508 		unsigned OpNum, SStream *O)
2509 {
2510 	// Normally, it's not safe to use register enum values directly with
2511 	// addition to get the next register, but for VFP registers, the
2512 	// sort order is guaranteed because they're all of the form D<n>.
2513 	SStream_concat0(O, "{");
2514 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2515 	if (MI->csh->detail) {
2516 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2517 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2518 		MI->flat_insn->detail->arm.op_count++;
2519 	}
2520 	SStream_concat0(O, "[], ");
2521 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2522 	if (MI->csh->detail) {
2523 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2524 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2525 		MI->flat_insn->detail->arm.op_count++;
2526 	}
2527 	SStream_concat0(O, "[], ");
2528 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
2529 	if (MI->csh->detail) {
2530 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2531 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
2532 		MI->flat_insn->detail->arm.op_count++;
2533 	}
2534 	SStream_concat0(O, "[], ");
2535 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
2536 	if (MI->csh->detail) {
2537 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2538 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
2539 		MI->flat_insn->detail->arm.op_count++;
2540 	}
2541 	SStream_concat0(O, "[]}");
2542 }
2543 
printVectorListThreeSpaced(MCInst * MI,unsigned OpNum,SStream * O)2544 static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
2545 {
2546 	// Normally, it's not safe to use register enum values directly with
2547 	// addition to get the next register, but for VFP registers, the
2548 	// sort order is guaranteed because they're all of the form D<n>.
2549 	SStream_concat0(O, "{");
2550 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2551 	if (MI->csh->detail) {
2552 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2553 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2554 		MI->flat_insn->detail->arm.op_count++;
2555 	}
2556 	SStream_concat0(O, ", ");
2557 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2558 	if (MI->csh->detail) {
2559 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2560 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2561 		MI->flat_insn->detail->arm.op_count++;
2562 	}
2563 	SStream_concat0(O, ", ");
2564 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
2565 	if (MI->csh->detail) {
2566 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2567 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
2568 		MI->flat_insn->detail->arm.op_count++;
2569 	}
2570 	SStream_concat0(O, "}");
2571 }
2572 
printVectorListFourSpaced(MCInst * MI,unsigned OpNum,SStream * O)2573 static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
2574 {
2575 	// Normally, it's not safe to use register enum values directly with
2576 	// addition to get the next register, but for VFP registers, the
2577 	// sort order is guaranteed because they're all of the form D<n>.
2578 	SStream_concat0(O, "{");
2579 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
2580 	if (MI->csh->detail) {
2581 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2582 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
2583 		MI->flat_insn->detail->arm.op_count++;
2584 	}
2585 	SStream_concat0(O, ", ");
2586 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
2587 	if (MI->csh->detail) {
2588 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2589 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
2590 		MI->flat_insn->detail->arm.op_count++;
2591 	}
2592 	SStream_concat0(O, ", ");
2593 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
2594 	if (MI->csh->detail) {
2595 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2596 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
2597 		MI->flat_insn->detail->arm.op_count++;
2598 	}
2599 	SStream_concat0(O, ", ");
2600 	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
2601 	if (MI->csh->detail) {
2602 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2603 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
2604 		MI->flat_insn->detail->arm.op_count++;
2605 	}
2606 	SStream_concat0(O, "}");
2607 }
2608 
ARM_addVectorDataType(MCInst * MI,arm_vectordata_type vd)2609 void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)
2610 {
2611 	if (MI->csh->detail) {
2612 		MI->flat_insn->detail->arm.vector_data = vd;
2613 	}
2614 }
2615 
ARM_addVectorDataSize(MCInst * MI,int size)2616 void ARM_addVectorDataSize(MCInst *MI, int size)
2617 {
2618 	if (MI->csh->detail) {
2619 		MI->flat_insn->detail->arm.vector_size = size;
2620 	}
2621 }
2622 
ARM_addReg(MCInst * MI,int reg)2623 void ARM_addReg(MCInst *MI, int reg)
2624 {
2625 	if (MI->csh->detail) {
2626 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
2627 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
2628 		MI->flat_insn->detail->arm.op_count++;
2629 	}
2630 }
2631 
ARM_addUserMode(MCInst * MI)2632 void ARM_addUserMode(MCInst *MI)
2633 {
2634 	if (MI->csh->detail) {
2635 		MI->flat_insn->detail->arm.usermode = true;
2636 	}
2637 }
2638 
ARM_addSysReg(MCInst * MI,arm_sysreg reg)2639 void ARM_addSysReg(MCInst *MI, arm_sysreg reg)
2640 {
2641 	if (MI->csh->detail) {
2642 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG;
2643 		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
2644 		MI->flat_insn->detail->arm.op_count++;
2645 	}
2646 }
2647 
2648 #endif
2649