1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Atmel Corporation 4 * Bo Shen <voice.shen@atmel.com> 5 * 6 * Copyright (C) 2015 Atmel Corporation 7 * Wenyou Yang <wenyou.yang@atmel.com> 8 */ 9 10 #ifndef __ATMEL_MPDDRC_H__ 11 #define __ATMEL_MPDDRC_H__ 12 13 struct atmel_mpddrc_config { 14 u32 mr; 15 u32 rtr; 16 u32 cr; 17 u32 tpr0; 18 u32 tpr1; 19 u32 tpr2; 20 u32 md; 21 }; 22 23 /* 24 * Only define the needed register in mpddr 25 * If other register needed, will add them later 26 */ 27 struct atmel_mpddr { 28 u32 mr; /* 0x00: Mode Register */ 29 u32 rtr; /* 0x04: Refresh Timer Register */ 30 u32 cr; /* 0x08: Configuration Register */ 31 u32 tpr0; /* 0x0c: Timing Parameter 0 Register */ 32 u32 tpr1; /* 0x10: Timing Parameter 1 Register */ 33 u32 tpr2; /* 0x14: Timing Parameter 2 Register */ 34 u32 reserved; /* 0x18: Reserved */ 35 u32 lpr; /* 0x1c: Low-power Register */ 36 u32 md; /* 0x20: Memory Device Register */ 37 u32 reserved1; /* 0x24: Reserved */ 38 u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/ 39 u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */ 40 u32 tim_cal; /* 0x30: Timing Calibration Register */ 41 u32 io_calibr; /* 0x34: IO Calibration */ 42 u32 ocms; /* 0x38: OCMS Register */ 43 u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */ 44 u32 ocms_key2; /* 0x40: OCMS KEY2 Register */ 45 u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */ 46 u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */ 47 u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */ 48 u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */ 49 u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */ 50 u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */ 51 u32 rd_data_path; /* 0x5c: Read Datapath Register */ 52 u32 reserved2[33]; 53 u32 wpmr; /* 0xe4: Write Protection Mode Register */ 54 u32 wpsr; /* 0xe8: Write Protection Status Register */ 55 u32 reserved3[4]; 56 u32 version; /* 0xfc: IP version */ 57 }; 58 59 60 int ddr2_init(const unsigned int base, 61 const unsigned int ram_address, 62 const struct atmel_mpddrc_config *mpddr_value); 63 64 int ddr3_init(const unsigned int base, 65 const unsigned int ram_address, 66 const struct atmel_mpddrc_config *mpddr_value); 67 68 /* Bit field in mode register */ 69 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 70 #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 71 #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 72 #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 73 #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 74 #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 75 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 76 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 77 78 /* Bit field in configuration register */ 79 #define ATMEL_MPDDRC_CR_NC_MASK 0x3 80 #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 81 #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 82 #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 83 #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 84 #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 85 #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 86 #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 87 #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 88 #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 89 #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 90 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 91 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 92 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 93 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 94 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 95 #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 96 #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 97 #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 98 #define ATMEL_MPDDRC_CR_ZQ_INIT (0x0 << 10) 99 #define ATMEL_MPDDRC_CR_ZQ_LONG (0x1 << 10) 100 #define ATMEL_MPDDRC_CR_ZQ_SHORT (0x2 << 10) 101 #define ATMEL_MPDDRC_CR_ZQ_RESET (0x3 << 10) 102 #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 103 #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 104 #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 105 #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 106 #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 107 #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 108 #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 109 110 /* Bit field in timing parameter 0 register */ 111 #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 112 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 113 #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 114 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 115 #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 116 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 117 #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 118 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 119 #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 120 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 121 #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 122 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 123 #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 124 #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 125 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 126 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 127 #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 128 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 129 130 /* Bit field in timing parameter 1 register */ 131 #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 132 #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 133 #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 134 #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 135 #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 136 #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 137 #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 138 #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 139 140 /* Bit field in timing parameter 2 register */ 141 #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 142 #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 143 #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 144 #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 145 #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 146 #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 147 #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 148 #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 149 #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 150 #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 151 152 /* Bit field in Memory Device Register */ 153 #define ATMEL_MPDDRC_MD_SDR_SDRAM 0x0 154 #define ATMEL_MPDDRC_MD_LP_SDR_SDRAM 0x1 155 #define ATMEL_MPDDRC_MD_DDR_SDRAM 0x2 156 #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 157 #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 158 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 159 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 160 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 161 #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 162 #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 163 164 /* Bit field in I/O Calibration Register */ 165 #define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7 166 167 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1 168 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2 169 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3 170 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4 171 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6 172 #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7 173 174 #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2 175 #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3 176 #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4 177 #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6 178 #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7 179 180 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 181 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 182 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 183 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 184 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 185 186 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 187 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 188 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 189 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 190 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 191 192 #define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8) 193 #define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8) 194 195 #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16) 196 #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16) 197 #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20) 198 #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20) 199 200 #define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4) 201 202 /* Bit field in Read Data Path Register */ 203 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3 204 #define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0 205 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1 206 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 207 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 208 209 #endif 210