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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _MV_DDR_PLAT_H
7 #define _MV_DDR_PLAT_H
8 
9 #define MAX_INTERFACE_NUM		1
10 #define MAX_BUS_NUM			5
11 #define DDR_IF_CTRL_SUBPHYS_NUM		3
12 
13 #define DFS_LOW_FREQ_VALUE		120
14 #define SDRAM_CS_SIZE			0xfffffff	/* FIXME: implement a function for cs size for each platform */
15 
16 #define INTER_REGS_BASE			SOC_REGS_PHY_BASE
17 #define AP_INT_REG_START_ADDR		0xd0000000
18 #define AP_INT_REG_END_ADDR		0xd0100000
19 
20 /* Controler bus divider 1 for 32 bit, 2 for 64 bit */
21 #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER	1
22 
23 /* Tune internal training params values */
24 #define TUNE_TRAINING_PARAMS_CK_DELAY		160
25 #define TUNE_TRAINING_PARAMS_PHYREG3VAL		0xA
26 #define TUNE_TRAINING_PARAMS_PRI_DATA		123
27 #define TUNE_TRAINING_PARAMS_NRI_DATA		123
28 #define TUNE_TRAINING_PARAMS_PRI_CTRL		74
29 #define TUNE_TRAINING_PARAMS_NRI_CTRL		74
30 #define TUNE_TRAINING_PARAMS_P_ODT_DATA		45
31 #define TUNE_TRAINING_PARAMS_N_ODT_DATA		45
32 #define TUNE_TRAINING_PARAMS_P_ODT_CTRL		45
33 #define TUNE_TRAINING_PARAMS_N_ODT_CTRL		45
34 #define TUNE_TRAINING_PARAMS_DIC		0x2
35 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS	0x120012
36 #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS	0x10000
37 #define TUNE_TRAINING_PARAMS_RTT_NOM		0x44
38 
39 #define TUNE_TRAINING_PARAMS_RTT_WR_1CS		0x0   /*off*/
40 #define TUNE_TRAINING_PARAMS_RTT_WR_2CS		0x0   /*off*/
41 
42 #define MARVELL_BOARD				MARVELL_BOARD_ID_BASE
43 
44 
45 #define REG_DEVICE_SAR1_ADDR			0xe4204
46 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET	17
47 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK	0x1f
48 #define DEVICE_SAMPLE_AT_RESET2_REG		0x18604
49 
50 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET	0
51 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ	0
52 #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ	1
53 
54 /* DRAM Windows */
55 #define REG_XBAR_WIN_5_CTRL_ADDR		0x20050
56 #define REG_XBAR_WIN_5_BASE_ADDR		0x20054
57 
58 /* DRAM Windows */
59 #define REG_XBAR_WIN_4_CTRL_ADDR                0x20040
60 #define REG_XBAR_WIN_4_BASE_ADDR                0x20044
61 #define REG_XBAR_WIN_4_REMAP_ADDR               0x20048
62 #define REG_XBAR_WIN_7_REMAP_ADDR               0x20078
63 #define REG_XBAR_WIN_16_CTRL_ADDR               0x200d0
64 #define REG_XBAR_WIN_16_BASE_ADDR               0x200d4
65 #define REG_XBAR_WIN_16_REMAP_ADDR              0x200dc
66 #define REG_XBAR_WIN_19_CTRL_ADDR               0x200e8
67 
68 #define REG_FASTPATH_WIN_BASE_ADDR(win)         (0x20180 + (0x8 * win))
69 #define REG_FASTPATH_WIN_CTRL_ADDR(win)         (0x20184 + (0x8 * win))
70 
71 #define CPU_CONFIGURATION_REG(id)	(0x21800 + (id * 0x100))
72 #define CPU_MRVL_ID_OFFSET		0x10
73 #define SAR1_CPU_CORE_MASK		0x00000018
74 #define SAR1_CPU_CORE_OFFSET		3
75 
76 /* SatR defined too change topology busWidth and ECC configuration */
77 #define DDR_SATR_CONFIG_MASK_WIDTH		0x8
78 #define DDR_SATR_CONFIG_MASK_ECC		0x10
79 #define DDR_SATR_CONFIG_MASK_ECC_PUP		0x20
80 
81 #define	REG_SAMPLE_RESET_HIGH_ADDR		0x18600
82 
83 #define MV_BOARD_REFCLK_25MHZ			25000000
84 #define MV_BOARD_REFCLK				MV_BOARD_REFCLK_25MHZ
85 
86 #define MAX_DQ_NUM				40
87 
88 /* dram line buffer registers */
89 #define DLB_CTRL_REG			0x1700
90 #define DLB_EN_OFFS			0
91 #define DLB_EN_MASK			0x1
92 #define DLB_EN_ENA			1
93 #define DLB_EN_DIS			0
94 #define WR_COALESCE_EN_OFFS		2
95 #define WR_COALESCE_EN_MASK		0x1
96 #define WR_COALESCE_EN_ENA		1
97 #define WR_COALESCE_EN_DIS		0
98 #define AXI_PREFETCH_EN_OFFS		3
99 #define AXI_PREFETCH_EN_MASK		0x1
100 #define AXI_PREFETCH_EN_ENA		1
101 #define AXI_PREFETCH_EN_DIS		0
102 #define MBUS_PREFETCH_EN_OFFS		4
103 #define MBUS_PREFETCH_EN_MASK		0x1
104 #define MBUS_PREFETCH_EN_ENA		1
105 #define MBUS_PREFETCH_EN_DIS		0
106 #define PREFETCH_NXT_LN_SZ_TRIG_OFFS	6
107 #define PREFETCH_NXT_LN_SZ_TRIG_MASK	0x1
108 #define PREFETCH_NXT_LN_SZ_TRIG_ENA	1
109 #define PREFETCH_NXT_LN_SZ_TRIG_DIS	0
110 
111 #define DLB_BUS_OPT_WT_REG		0x1704
112 #define DLB_AGING_REG			0x1708
113 #define DLB_EVICTION_CTRL_REG		0x170c
114 #define DLB_EVICTION_TIMERS_REG		0x1710
115 #define DLB_USER_CMD_REG		0x1714
116 #define DLB_WTS_DIFF_CS_REG		0x1770
117 #define DLB_WTS_DIFF_BG_REG		0x1774
118 #define DLB_WTS_SAME_BG_REG		0x1778
119 #define DLB_WTS_CMDS_REG		0x177c
120 #define DLB_WTS_ATTR_PRIO_REG		0x1780
121 #define DLB_QUEUE_MAP_REG		0x1784
122 #define DLB_SPLIT_REG			0x1788
123 
124 /* Subphy result control per byte registers */
125 #define RESULT_CONTROL_BYTE_PUP_0_REG		0x1830
126 #define RESULT_CONTROL_BYTE_PUP_1_REG		0x1834
127 #define RESULT_CONTROL_BYTE_PUP_2_REG		0x1838
128 #define RESULT_CONTROL_BYTE_PUP_3_REG		0x183c
129 #define RESULT_CONTROL_BYTE_PUP_4_REG		0x18b0
130 
131 /* Subphy result control per bit registers */
132 #define RESULT_CONTROL_PUP_0_BIT_0_REG		0x18b4
133 #define RESULT_CONTROL_PUP_0_BIT_1_REG		0x18b8
134 #define RESULT_CONTROL_PUP_0_BIT_2_REG		0x18bc
135 #define RESULT_CONTROL_PUP_0_BIT_3_REG		0x18c0
136 #define RESULT_CONTROL_PUP_0_BIT_4_REG		0x18c4
137 #define RESULT_CONTROL_PUP_0_BIT_5_REG		0x18c8
138 #define RESULT_CONTROL_PUP_0_BIT_6_REG		0x18cc
139 #define RESULT_CONTROL_PUP_0_BIT_7_REG		0x18f0
140 
141 #define RESULT_CONTROL_PUP_1_BIT_0_REG		0x18f4
142 #define RESULT_CONTROL_PUP_1_BIT_1_REG		0x18f8
143 #define RESULT_CONTROL_PUP_1_BIT_2_REG		0x18fc
144 #define RESULT_CONTROL_PUP_1_BIT_3_REG		0x1930
145 #define RESULT_CONTROL_PUP_1_BIT_4_REG		0x1934
146 #define RESULT_CONTROL_PUP_1_BIT_5_REG		0x1938
147 #define RESULT_CONTROL_PUP_1_BIT_6_REG		0x193c
148 #define RESULT_CONTROL_PUP_1_BIT_7_REG		0x19b0
149 
150 #define RESULT_CONTROL_PUP_2_BIT_0_REG		0x19b4
151 #define RESULT_CONTROL_PUP_2_BIT_1_REG		0x19b8
152 #define RESULT_CONTROL_PUP_2_BIT_2_REG		0x19bc
153 #define RESULT_CONTROL_PUP_2_BIT_3_REG		0x19c0
154 #define RESULT_CONTROL_PUP_2_BIT_4_REG		0x19c4
155 #define RESULT_CONTROL_PUP_2_BIT_5_REG		0x19c8
156 #define RESULT_CONTROL_PUP_2_BIT_6_REG		0x19cc
157 #define RESULT_CONTROL_PUP_2_BIT_7_REG		0x19f0
158 
159 #define RESULT_CONTROL_PUP_3_BIT_0_REG		0x19f4
160 #define RESULT_CONTROL_PUP_3_BIT_1_REG		0x19f8
161 #define RESULT_CONTROL_PUP_3_BIT_2_REG		0x19fc
162 #define RESULT_CONTROL_PUP_3_BIT_3_REG		0x1a30
163 #define RESULT_CONTROL_PUP_3_BIT_4_REG		0x1a34
164 #define RESULT_CONTROL_PUP_3_BIT_5_REG		0x1a38
165 #define RESULT_CONTROL_PUP_3_BIT_6_REG		0x1a3c
166 #define RESULT_CONTROL_PUP_3_BIT_7_REG		0x1ab0
167 
168 #define RESULT_CONTROL_PUP_4_BIT_0_REG		0x1ab4
169 #define RESULT_CONTROL_PUP_4_BIT_1_REG		0x1ab8
170 #define RESULT_CONTROL_PUP_4_BIT_2_REG		0x1abc
171 #define RESULT_CONTROL_PUP_4_BIT_3_REG		0x1ac0
172 #define RESULT_CONTROL_PUP_4_BIT_4_REG		0x1ac4
173 #define RESULT_CONTROL_PUP_4_BIT_5_REG		0x1ac8
174 #define RESULT_CONTROL_PUP_4_BIT_6_REG		0x1acc
175 #define RESULT_CONTROL_PUP_4_BIT_7_REG		0x1af0
176 
177 /* CPU */
178 #define REG_BOOTROM_ROUTINE_ADDR		0x182d0
179 #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS	12
180 
181 /* Matrix enables DRAM modes (bus width/ECC) per boardId */
182 #define TOPOLOGY_UPDATE_32BIT			0
183 #define TOPOLOGY_UPDATE_32BIT_ECC		1
184 #define TOPOLOGY_UPDATE_16BIT			2
185 #define TOPOLOGY_UPDATE_16BIT_ECC		3
186 #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3		4
187 #define TOPOLOGY_UPDATE { \
188 		/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
189 		{1, 1, 1, 1, 1},	/* RD_NAS_68XX_ID */ \
190 		{1, 1, 1, 1, 1},	/* DB_68XX_ID	  */ \
191 		{1, 0, 1, 0, 1},	/* RD_AP_68XX_ID  */ \
192 		{1, 0, 1, 0, 1},	/* DB_AP_68XX_ID  */ \
193 		{1, 0, 1, 0, 1},	/* DB_GP_68XX_ID  */ \
194 		{0, 0, 1, 1, 0},	/* DB_BP_6821_ID  */ \
195 		{1, 1, 1, 1, 1}		/* DB_AMC_6820_ID */ \
196 	};
197 
198 enum {
199 	CPU_1066MHZ_DDR_400MHZ,
200 	CPU_RESERVED_DDR_RESERVED0,
201 	CPU_667MHZ_DDR_667MHZ,
202 	CPU_800MHZ_DDR_800MHZ,
203 	CPU_RESERVED_DDR_RESERVED1,
204 	CPU_RESERVED_DDR_RESERVED2,
205 	CPU_RESERVED_DDR_RESERVED3,
206 	LAST_FREQ
207 };
208 
209 /* struct used for DLB configuration array */
210 struct dlb_config {
211 	u32 reg_addr;
212 	u32 reg_data;
213 };
214 
215 #define ACTIVE_INTERFACE_MASK			0x1
216 
217 extern u32 dmin_phy_reg_table[][2];
218 extern u16 odt_slope[];
219 extern u16 odt_intercept[];
220 
221 int mv_ddr_pre_training_soc_config(const char *ddr_type);
222 int mv_ddr_post_training_soc_config(const char *ddr_type);
223 void mv_ddr_mem_scrubbing(void);
224 
225 void mv_ddr_odpg_enable(void);
226 void mv_ddr_odpg_disable(void);
227 void mv_ddr_odpg_done_clr(void);
228 int mv_ddr_is_odpg_done(u32 count);
229 void mv_ddr_training_enable(void);
230 int mv_ddr_is_training_done(u32 count, u32 *result);
231 u32 mv_ddr_dm_pad_get(void);
232 int mv_ddr_pre_training_fixup(void);
233 int mv_ddr_post_training_fixup(void);
234 int mv_ddr_manual_cal_do(void);
235 int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size);
236 #endif /* _MV_DDR_PLAT_H */
237