1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012,2015 Stephen Warren 4 */ 5 6 #ifndef _BCM2835_MBOX_H 7 #define _BCM2835_MBOX_H 8 9 #include <linux/compiler.h> 10 11 /* 12 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") 13 * and the ARM CPU. The ARM CPU is often thought of as the main CPU. 14 * However, the VideoCore actually controls the initial SoC boot, and hides 15 * much of the hardware behind a protocol. This protocol is transported 16 * using the SoC's mailbox hardware module. 17 * 18 * The mailbox hardware supports passing 32-bit values back and forth. 19 * Presumably by software convention of the firmware, the bottom 4 bits of the 20 * value are used to indicate a logical channel, and the upper 28 bits are the 21 * actual payload. Various channels exist using these simple raw messages. See 22 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an 23 * example, the messages on the power management channel are a bitmask of 24 * devices whose power should be enabled. 25 * 26 * The property mailbox channel passes messages that contain the (16-byte 27 * aligned) ARM physical address of a memory buffer. This buffer is passed to 28 * the VC for processing, is modified in-place by the VC, and the address then 29 * passed back to the ARM CPU as the response mailbox message to indicate 30 * request completion. The buffers have a generic and extensible format; each 31 * buffer contains a standard header, a list of "tags", and a terminating zero 32 * entry. Each tag contains an ID indicating its type, and length fields for 33 * generic parsing. With some limitations, an arbitrary set of tags may be 34 * combined together into a single message buffer. This file defines structs 35 * representing the header and many individual tag layouts and IDs. 36 */ 37 38 /* Raw mailbox HW */ 39 40 #ifndef CONFIG_BCM2835 41 #define BCM2835_MBOX_PHYSADDR 0x3f00b880 42 #else 43 #define BCM2835_MBOX_PHYSADDR 0x2000b880 44 #endif 45 46 struct bcm2835_mbox_regs { 47 u32 read; 48 u32 rsvd0[5]; 49 u32 status; 50 u32 config; 51 u32 write; 52 }; 53 54 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 55 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 56 57 /* Lower 4-bits are channel ID */ 58 #define BCM2835_CHAN_MASK 0xf 59 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ 60 (chan & BCM2835_CHAN_MASK)) 61 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) 62 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) 63 64 /* Property mailbox buffer structures */ 65 66 #define BCM2835_MBOX_PROP_CHAN 8 67 68 /* All message buffers must start with this header */ 69 struct bcm2835_mbox_hdr { 70 u32 buf_size; 71 u32 code; 72 }; 73 74 #define BCM2835_MBOX_REQ_CODE 0 75 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 76 77 #define BCM2835_MBOX_INIT_HDR(_m_) { \ 78 memset((_m_), 0, sizeof(*(_m_))); \ 79 (_m_)->hdr.buf_size = sizeof(*(_m_)); \ 80 (_m_)->hdr.code = 0; \ 81 (_m_)->end_tag = 0; \ 82 } 83 84 /* 85 * A message buffer contains a list of tags. Each tag must also start with 86 * a standardized header. 87 */ 88 struct bcm2835_mbox_tag_hdr { 89 u32 tag; 90 u32 val_buf_size; 91 u32 val_len; 92 }; 93 94 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ 95 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 96 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 97 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ 98 } 99 100 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ 101 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ 102 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ 103 (_t_)->tag_hdr.val_len = 0; \ 104 } 105 106 /* When responding, the VC sets this bit in val_len to indicate a response */ 107 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 108 109 /* 110 * Below we define the ID and struct for many possible tags. This header only 111 * defines individual tag structs, not entire message structs, since in 112 * general an arbitrary set of tags may be combined into a single message. 113 * Clients of the mbox API are expected to define their own overall message 114 * structures by combining the header, a set of tags, and a terminating 115 * entry. For example, 116 * 117 * struct msg { 118 * struct bcm2835_mbox_hdr hdr; 119 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; 120 * ... perhaps other tags here ... 121 * u32 end_tag; 122 * }; 123 */ 124 125 #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 126 127 struct bcm2835_mbox_tag_get_board_rev { 128 struct bcm2835_mbox_tag_hdr tag_hdr; 129 union { 130 struct { 131 } req; 132 struct { 133 u32 rev; 134 } resp; 135 } body; 136 }; 137 138 #define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 139 140 struct bcm2835_mbox_tag_get_mac_address { 141 struct bcm2835_mbox_tag_hdr tag_hdr; 142 union { 143 struct { 144 } req; 145 struct { 146 u8 mac[6]; 147 u8 pad[2]; 148 } resp; 149 } body; 150 }; 151 152 #define BCM2835_MBOX_TAG_GET_BOARD_SERIAL 0x00010004 153 154 struct bcm2835_mbox_tag_get_board_serial { 155 struct bcm2835_mbox_tag_hdr tag_hdr; 156 union { 157 struct __packed { 158 u64 serial; 159 } resp; 160 } body; 161 }; 162 163 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 164 165 struct bcm2835_mbox_tag_get_arm_mem { 166 struct bcm2835_mbox_tag_hdr tag_hdr; 167 union { 168 struct { 169 } req; 170 struct { 171 u32 mem_base; 172 u32 mem_size; 173 } resp; 174 } body; 175 }; 176 177 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0 178 #define BCM2835_MBOX_POWER_DEVID_UART0 1 179 #define BCM2835_MBOX_POWER_DEVID_UART1 2 180 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3 181 #define BCM2835_MBOX_POWER_DEVID_I2C0 4 182 #define BCM2835_MBOX_POWER_DEVID_I2C1 5 183 #define BCM2835_MBOX_POWER_DEVID_I2C2 6 184 #define BCM2835_MBOX_POWER_DEVID_SPI 7 185 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8 186 187 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0) 188 /* Device doesn't exist */ 189 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1) 190 191 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001 192 193 struct bcm2835_mbox_tag_get_power_state { 194 struct bcm2835_mbox_tag_hdr tag_hdr; 195 union { 196 struct { 197 u32 device_id; 198 } req; 199 struct { 200 u32 device_id; 201 u32 state; 202 } resp; 203 } body; 204 }; 205 206 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001 207 208 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0) 209 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1) 210 211 struct bcm2835_mbox_tag_set_power_state { 212 struct bcm2835_mbox_tag_hdr tag_hdr; 213 union { 214 struct { 215 u32 device_id; 216 u32 state; 217 } req; 218 struct { 219 u32 device_id; 220 u32 state; 221 } resp; 222 } body; 223 }; 224 225 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 226 227 #define BCM2835_MBOX_CLOCK_ID_EMMC 1 228 #define BCM2835_MBOX_CLOCK_ID_UART 2 229 #define BCM2835_MBOX_CLOCK_ID_ARM 3 230 #define BCM2835_MBOX_CLOCK_ID_CORE 4 231 #define BCM2835_MBOX_CLOCK_ID_V3D 5 232 #define BCM2835_MBOX_CLOCK_ID_H264 6 233 #define BCM2835_MBOX_CLOCK_ID_ISP 7 234 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8 235 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9 236 #define BCM2835_MBOX_CLOCK_ID_PWM 10 237 238 struct bcm2835_mbox_tag_get_clock_rate { 239 struct bcm2835_mbox_tag_hdr tag_hdr; 240 union { 241 struct { 242 u32 clock_id; 243 } req; 244 struct { 245 u32 clock_id; 246 u32 rate_hz; 247 } resp; 248 } body; 249 }; 250 251 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 252 253 struct bcm2835_mbox_tag_allocate_buffer { 254 struct bcm2835_mbox_tag_hdr tag_hdr; 255 union { 256 struct { 257 u32 alignment; 258 } req; 259 struct { 260 u32 fb_address; 261 u32 fb_size; 262 } resp; 263 } body; 264 }; 265 266 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 267 268 struct bcm2835_mbox_tag_release_buffer { 269 struct bcm2835_mbox_tag_hdr tag_hdr; 270 union { 271 struct { 272 } req; 273 struct { 274 } resp; 275 } body; 276 }; 277 278 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 279 280 struct bcm2835_mbox_tag_blank_screen { 281 struct bcm2835_mbox_tag_hdr tag_hdr; 282 union { 283 struct { 284 /* bit 0 means on, other bots reserved */ 285 u32 state; 286 } req; 287 struct { 288 u32 state; 289 } resp; 290 } body; 291 }; 292 293 /* Physical means output signal */ 294 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 295 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 296 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 297 298 struct bcm2835_mbox_tag_physical_w_h { 299 struct bcm2835_mbox_tag_hdr tag_hdr; 300 union { 301 /* req not used for get */ 302 struct { 303 u32 width; 304 u32 height; 305 } req; 306 struct { 307 u32 width; 308 u32 height; 309 } resp; 310 } body; 311 }; 312 313 /* Virtual means display buffer */ 314 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 315 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 316 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 317 318 struct bcm2835_mbox_tag_virtual_w_h { 319 struct bcm2835_mbox_tag_hdr tag_hdr; 320 union { 321 /* req not used for get */ 322 struct { 323 u32 width; 324 u32 height; 325 } req; 326 struct { 327 u32 width; 328 u32 height; 329 } resp; 330 } body; 331 }; 332 333 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 334 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 335 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 336 337 struct bcm2835_mbox_tag_depth { 338 struct bcm2835_mbox_tag_hdr tag_hdr; 339 union { 340 /* req not used for get */ 341 struct { 342 u32 bpp; 343 } req; 344 struct { 345 u32 bpp; 346 } resp; 347 } body; 348 }; 349 350 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 351 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005 352 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 353 354 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0 355 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1 356 357 struct bcm2835_mbox_tag_pixel_order { 358 struct bcm2835_mbox_tag_hdr tag_hdr; 359 union { 360 /* req not used for get */ 361 struct { 362 u32 order; 363 } req; 364 struct { 365 u32 order; 366 } resp; 367 } body; 368 }; 369 370 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 371 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 372 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 373 374 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 375 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 376 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 377 378 struct bcm2835_mbox_tag_alpha_mode { 379 struct bcm2835_mbox_tag_hdr tag_hdr; 380 union { 381 /* req not used for get */ 382 struct { 383 u32 alpha; 384 } req; 385 struct { 386 u32 alpha; 387 } resp; 388 } body; 389 }; 390 391 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 392 393 struct bcm2835_mbox_tag_pitch { 394 struct bcm2835_mbox_tag_hdr tag_hdr; 395 union { 396 struct { 397 } req; 398 struct { 399 u32 pitch; 400 } resp; 401 } body; 402 }; 403 404 /* Offset of display window within buffer */ 405 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 406 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 407 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 408 409 struct bcm2835_mbox_tag_virtual_offset { 410 struct bcm2835_mbox_tag_hdr tag_hdr; 411 union { 412 /* req not used for get */ 413 struct { 414 u32 x; 415 u32 y; 416 } req; 417 struct { 418 u32 x; 419 u32 y; 420 } resp; 421 } body; 422 }; 423 424 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a 425 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a 426 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a 427 428 struct bcm2835_mbox_tag_overscan { 429 struct bcm2835_mbox_tag_hdr tag_hdr; 430 union { 431 /* req not used for get */ 432 struct { 433 u32 top; 434 u32 bottom; 435 u32 left; 436 u32 right; 437 } req; 438 struct { 439 u32 top; 440 u32 bottom; 441 u32 left; 442 u32 right; 443 } resp; 444 } body; 445 }; 446 447 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b 448 449 struct bcm2835_mbox_tag_get_palette { 450 struct bcm2835_mbox_tag_hdr tag_hdr; 451 union { 452 struct { 453 } req; 454 struct { 455 u32 data[1024]; 456 } resp; 457 } body; 458 }; 459 460 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b 461 462 struct bcm2835_mbox_tag_test_palette { 463 struct bcm2835_mbox_tag_hdr tag_hdr; 464 union { 465 struct { 466 u32 offset; 467 u32 num_entries; 468 u32 data[256]; 469 } req; 470 struct { 471 u32 is_invalid; 472 } resp; 473 } body; 474 }; 475 476 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b 477 478 struct bcm2835_mbox_tag_set_palette { 479 struct bcm2835_mbox_tag_hdr tag_hdr; 480 union { 481 struct { 482 u32 offset; 483 u32 num_entries; 484 u32 data[256]; 485 } req; 486 struct { 487 u32 is_invalid; 488 } resp; 489 } body; 490 }; 491 492 /* 493 * Pass a raw u32 message to the VC, and receive a raw u32 back. 494 * 495 * Returns 0 for success, any other value for error. 496 */ 497 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); 498 499 /* 500 * Pass a complete property-style buffer to the VC, and wait until it has 501 * been processed. 502 * 503 * This function expects a pointer to the mbox_hdr structure in an attempt 504 * to ensure some degree of type safety. However, some number of tags and 505 * a termination value are expected to immediately follow the header in 506 * memory, as required by the property protocol. 507 * 508 * Each struct bcm2835_mbox_hdr passed must be allocated with 509 * ALLOC_CACHE_ALIGN_BUFFER(x, y, z) to ensure proper cache flush/invalidate. 510 * 511 * Returns 0 for success, any other value for error. 512 */ 513 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); 514 515 #endif 516