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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * arch/arm/include/asm/arch-rmobile/rcar-base.h
4  *
5  * Copyright (C) 2013,2014 Renesas Electronics Corporation
6  */
7 
8 #ifndef __ASM_ARCH_RCAR_BASE_H
9 #define __ASM_ARCH_RCAR_BASE_H
10 
11 /*
12  * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
13  */
14 #define RWDT_BASE		0xE6020000
15 #define SWDT_BASE		0xE6030000
16 #define LBSC_BASE		0xFEC00200
17 #define DBSC3_0_BASE		0xE6790000
18 #define DBSC3_1_BASE		0xE67A0000
19 #define TMU_BASE		0xE61E0000
20 #define GPIO5_BASE		0xE6055000
21 #define SH_QSPI_BASE		0xE6B10000
22 
23 /* SCIF */
24 #define SCIF0_BASE		0xE6E60000
25 #define SCIF1_BASE		0xE6E68000
26 #define SCIF2_BASE		0xE6E58000
27 #define SCIF3_BASE		0xE6EA8000
28 #define SCIF4_BASE		0xE6EE0000
29 #define SCIF5_BASE		0xE6EE8000
30 #define SCIFA0_BASE		0xE6C40000
31 #define SCIFA1_BASE		0xE6C50000
32 #define SCIFA2_BASE		0xE6C60000
33 
34 /* Module stop status register */
35 #define MSTPSR0			0xE6150030
36 #define MSTPSR1			0xE6150038
37 #define MSTPSR2			0xE6150040
38 #define MSTPSR3			0xE6150048
39 #define MSTPSR4			0xE615004C
40 #define MSTPSR5			0xE615003C
41 #define MSTPSR7			0xE61501C4
42 #define MSTPSR8			0xE61509A0
43 #define MSTPSR9			0xE61509A4
44 #define MSTPSR10		0xE61509A8
45 #define MSTPSR11		0xE61509AC
46 
47 /* Realtime module stop control register */
48 #define RMSTPCR0		0xE6150110
49 #define RMSTPCR1		0xE6150114
50 #define RMSTPCR2		0xE6150118
51 #define RMSTPCR3		0xE615011C
52 #define RMSTPCR4		0xE6150120
53 #define RMSTPCR5		0xE6150124
54 #define RMSTPCR7		0xE615012C
55 #define RMSTPCR8		0xE6150980
56 #define RMSTPCR9		0xE6150984
57 #define RMSTPCR10		0xE6150988
58 #define RMSTPCR11		0xE615098C
59 
60 /* System module stop control register */
61 #define SMSTPCR0		0xE6150130
62 #define SMSTPCR1		0xE6150134
63 #define SMSTPCR2		0xE6150138
64 #define SMSTPCR3		0xE615013C
65 #define SMSTPCR4		0xE6150140
66 #define SMSTPCR5		0xE6150144
67 #define SMSTPCR7		0xE615014C
68 #define SMSTPCR8		0xE6150990
69 #define SMSTPCR9		0xE6150994
70 #define SMSTPCR10		0xE6150998
71 #define SMSTPCR11		0xE615099C
72 
73 /*
74  * SH-I2C
75  * Ch2 and ch3 are different address. These are defined
76  * in the header of each SoCs.
77  */
78 #define CONFIG_SYS_I2C_SH_BASE0	0xE6500000
79 #define CONFIG_SYS_I2C_SH_BASE1	0xE6510000
80 
81 /* RCAR-I2C */
82 #define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
83 #define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
84 #define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
85 #define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
86 
87 /* SDHI */
88 #define CONFIG_SYS_SH_SDHI0_BASE	0xEE100000
89 
90 #define S3C_BASE		0xE6784000
91 #define S3C_INT_BASE		0xE6784A00
92 #define S3C_MEDIA_BASE		0xE6784B00
93 
94 #define S3C_QOS_DCACHE_BASE	0xE6784BDC
95 #define S3C_QOS_CCI0_BASE	0xE6784C00
96 #define S3C_QOS_CCI1_BASE	0xE6784C24
97 #define S3C_QOS_MXI_BASE	0xE6784C48
98 #define S3C_QOS_AXI_BASE	0xE6784C6C
99 
100 #define DBSC3_0_QOS_R0_BASE	0xE6791000
101 #define DBSC3_0_QOS_R1_BASE	0xE6791100
102 #define DBSC3_0_QOS_R2_BASE	0xE6791200
103 #define DBSC3_0_QOS_R3_BASE	0xE6791300
104 #define DBSC3_0_QOS_R4_BASE	0xE6791400
105 #define DBSC3_0_QOS_R5_BASE	0xE6791500
106 #define DBSC3_0_QOS_R6_BASE	0xE6791600
107 #define DBSC3_0_QOS_R7_BASE	0xE6791700
108 #define DBSC3_0_QOS_R8_BASE	0xE6791800
109 #define DBSC3_0_QOS_R9_BASE	0xE6791900
110 #define DBSC3_0_QOS_R10_BASE	0xE6791A00
111 #define DBSC3_0_QOS_R11_BASE	0xE6791B00
112 #define DBSC3_0_QOS_R12_BASE	0xE6791C00
113 #define DBSC3_0_QOS_R13_BASE	0xE6791D00
114 #define DBSC3_0_QOS_R14_BASE	0xE6791E00
115 #define DBSC3_0_QOS_R15_BASE	0xE6791F00
116 #define DBSC3_0_QOS_W0_BASE	0xE6792000
117 #define DBSC3_0_QOS_W1_BASE	0xE6792100
118 #define DBSC3_0_QOS_W2_BASE	0xE6792200
119 #define DBSC3_0_QOS_W3_BASE	0xE6792300
120 #define DBSC3_0_QOS_W4_BASE	0xE6792400
121 #define DBSC3_0_QOS_W5_BASE	0xE6792500
122 #define DBSC3_0_QOS_W6_BASE	0xE6792600
123 #define DBSC3_0_QOS_W7_BASE	0xE6792700
124 #define DBSC3_0_QOS_W8_BASE	0xE6792800
125 #define DBSC3_0_QOS_W9_BASE	0xE6792900
126 #define DBSC3_0_QOS_W10_BASE	0xE6792A00
127 #define DBSC3_0_QOS_W11_BASE	0xE6792B00
128 #define DBSC3_0_QOS_W12_BASE	0xE6792C00
129 #define DBSC3_0_QOS_W13_BASE	0xE6792D00
130 #define DBSC3_0_QOS_W14_BASE	0xE6792E00
131 #define DBSC3_0_QOS_W15_BASE	0xE6792F00
132 #define DBSC3_0_DBADJ2		0xE67900C8
133 
134 #define CCI_400_MAXOT_1		0xF0091110
135 #define CCI_400_MAXOT_2		0xF0092110
136 #define CCI_400_QOSCNTL_1	0xF009110C
137 #define CCI_400_QOSCNTL_2	0xF009210C
138 
139 #define	MXI_BASE		0xFE960000
140 #define	MXI_QOS_BASE		0xFE960300
141 
142 #define SYS_AXI_SYX64TO128_BASE	0xFF800300
143 #define SYS_AXI_AVB_BASE	0xFF800340
144 #define SYS_AXI_AX2M_BASE	0xFF800380
145 #define SYS_AXI_CC50_BASE	0xFF8003C0
146 #define SYS_AXI_CCI_BASE	0xFF800440
147 #define SYS_AXI_CS_BASE		0xFF800480
148 #define SYS_AXI_DDM_BASE	0xFF8004C0
149 #define SYS_AXI_ETH_BASE	0xFF800500
150 #define SYS_AXI_G2D_BASE	0xFF800540
151 #define SYS_AXI_IMP0_BASE	0xFF800580
152 #define SYS_AXI_IMP1_BASE	0xFF8005C0
153 #define SYS_AXI_IMUX0_BASE	0xFF800600
154 #define SYS_AXI_IMUX1_BASE	0xFF800640
155 #define SYS_AXI_IMUX2_BASE	0xFF800680
156 #define SYS_AXI_LBS_BASE	0xFF8006C0
157 #define SYS_AXI_MMUDS_BASE	0xFF800700
158 #define SYS_AXI_MMUM_BASE	0xFF800740
159 #define SYS_AXI_MMUR_BASE	0xFF800780
160 #define SYS_AXI_MMUS0_BASE	0xFF8007C0
161 #define SYS_AXI_MMUS1_BASE	0xFF800800
162 #define SYS_AXI_MPXM_BASE	0xFF800840
163 #define SYS_AXI_MTSB0_BASE	0xFF800880
164 #define SYS_AXI_MTSB1_BASE	0xFF8008C0
165 #define SYS_AXI_PCI_BASE	0xFF800900
166 #define SYS_AXI_RTX_BASE	0xFF800940
167 #define SYS_AXI_SAT0_BASE	0xFF800980
168 #define SYS_AXI_SAT1_BASE	0xFF8009C0
169 #define SYS_AXI_SDM0_BASE	0xFF800A00
170 #define SYS_AXI_SDM1_BASE	0xFF800A40
171 #define SYS_AXI_SDS0_BASE	0xFF800A80
172 #define SYS_AXI_SDS1_BASE	0xFF800AC0
173 #define SYS_AXI_TRAB_BASE	0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
174 #define SYS_AXI_UDM0_BASE	0xFF800B80
175 #define SYS_AXI_UDM1_BASE	0xFF800BC0
176 #define SYS_AXI_USB20_BASE	0xFF800C00
177 #define SYS_AXI_USB21_BASE	0xFF800C40
178 #define SYS_AXI_USB22_BASE	0xFF800C80
179 #define SYS_AXI_USB30_BASE	0xFF800CC0
180 #define SYS_AXI_ADM_BASE	0xFF800D00
181 #define SYS_AXI_ADS_BASE	0xFF800D40
182 #define SYS_AXI_SYX_BASE	0xFF800FB8
183 
184 #define SYS_AXI_AXI64TO128W_BASE	0xFF801300
185 #define SYS_AXI_AVBW_BASE	0xFF801340
186 #define SYS_AXI_CC50W_BASE	0xFF8013C0
187 #define SYS_AXI_CCIW_BASE	0xFF801440
188 #define SYS_AXI_CSW_BASE	0xFF801480
189 #define SYS_AXI_G2DW_BASE	0xFF801540
190 #define SYS_AXI_IMUX0W_BASE	0xFF801600
191 #define SYS_AXI_IMUX1W_BASE	0xFF801640
192 #define SYS_AXI_IMUX2W_BASE	0xFF801680
193 #define SYS_AXI_LBSW_BASE	0xFF8016C0
194 #define SYS_AXI_RTXW_BASE	0xFF801940
195 #define SYS_AXI_SDM0W_BASE	0xFF801A00
196 #define SYS_AXI_SDM1W_BASE	0xFF801A40
197 #define SYS_AXI_SDS0W_BASE	0xFF801A80
198 #define SYS_AXI_SDS1W_BASE	0xFF801AC0
199 #define SYS_AXI_TRABW_BASE	0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
200 #define SYS_AXI_UDM0W_BASE	0xFF801B80
201 #define SYS_AXI_UDM1W_BASE	0xFF801BC0
202 #define SYS_AXI_ADMW_BASE	0xFF801D00
203 #define SYS_AXI_ADSW_BASE	0xFF801D40
204 #define SYS_AXI_SYXW_BASE	0xFF801FB8
205 
206 #define RT_AXI_SHX_BASE		0xFF810100
207 #define RT_AXI_DBG_BASE		0xFF810140 /* R8A7791 only */
208 #define RT_AXI_RDM_BASE		0xFF810180 /* R8A7791 only */
209 #define RT_AXI_RDS_BASE		0xFF8101C0
210 #define RT_AXI_RTX64TO128_BASE	0xFF810200
211 #define RT_AXI_STPRO_BASE	0xFF810240
212 #define RT_AXI_SY2RT_BASE	0xFF810280 /* R8A7791 only */
213 #define RT_AXI_RT_BASE		0xFF810FC0
214 #define RT_AXI_SHXW_BASE	0xFF811100
215 #define RT_AXI_DBGW_BASE	0xFF811140
216 #define RT_AXI_RTX64TO128W_BASE	0xFF811200
217 #define RT_AXI_RTW_BASE		0xFF811FC0
218 
219 #define MP_AXI_ADSP_BASE	0xFF820100
220 #define MP_AXI_ASDS0_BASE	0xFF8201C0
221 #define MP_AXI_ASDS1_BASE	0xFF820200
222 #define MP_AXI_MLP_BASE		0xFF820240
223 #define MP_AXI_MMUMP_BASE	0xFF820280
224 #define MP_AXI_SPU_BASE		0xFF8202C0
225 #define MP_AXI_SPUC_BASE	0xFF820300
226 
227 #define SYS_AXI256_AXI128TO256_BASE	0xFF860100
228 #define SYS_AXI256_SYX_BASE	0xFF860140
229 #define SYS_AXI256_AXM_BASE	0xFF860140
230 #define SYS_AXI256_MPX_BASE	0xFF860180
231 #define SYS_AXI256_MXI_BASE	0xFF8601C0
232 #define SYS_AXI256_IMP0_BASE	0xFF860580
233 #define SYS_AXI256_SY2_BASE	0xFF860FC0
234 #define SYS_AXI256_AXI128TO256W_BASE	0xFF861100
235 #define SYS_AXI256_AXMW_BASE	0xFF861140
236 #define SYS_AXI256_MXIW_BASE	0xFF8611C0
237 #define SYS_AXI256_IMP0W_BASE	0xFF861580
238 #define SYS_AXI256_SY2W_BASE	0xFF861FC0
239 
240 #define CCI_AXI_MMUS0_BASE	0xFF880100
241 #define CCI_AXI_SYX2_BASE	0xFF880140
242 #define CCI_AXI_MMUR_BASE	0xFF880180
243 #define CCI_AXI_MMUDS_BASE	0xFF8801C0
244 #define CCI_AXI_MMUM_BASE	0xFF880200
245 #define CCI_AXI_MXI_BASE	0xFF880240
246 #define CCI_AXI_MMUS1_BASE	0xFF880280
247 #define CCI_AXI_MMUMP_BASE	0xFF8802C0
248 
249 #define MEDIA_AXI_MXR_BASE	0xFE960080 /* R8A7791 only */
250 #define MEDIA_AXI_MXW_BASE	0xFE9600C0 /* R8A7791 only */
251 #define MEDIA_AXI_JPR_BASE	0xFE964100
252 #define MEDIA_AXI_JPW_BASE	0xFE966100
253 #define MEDIA_AXI_GCU0R_BASE	0xFE964140
254 #define MEDIA_AXI_GCU0W_BASE	0xFE966140
255 #define MEDIA_AXI_GCU1R_BASE	0xFE964180
256 #define MEDIA_AXI_GCU1W_BASE	0xFE966180
257 #define MEDIA_AXI_TDMR_BASE	0xFE964500
258 #define MEDIA_AXI_TDMW_BASE	0xFE966500
259 #define MEDIA_AXI_VSP0CR_BASE	0xFE964540
260 #define MEDIA_AXI_VSP0CW_BASE	0xFE966540
261 #define MEDIA_AXI_VSP1CR_BASE	0xFE964580
262 #define MEDIA_AXI_VSP1CW_BASE	0xFE966580
263 #define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
264 #define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
265 #define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
266 #define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
267 #define MEDIA_AXI_FDP0R_BASE	0xFE964D40
268 #define MEDIA_AXI_FDP0W_BASE	0xFE966D40
269 #define MEDIA_AXI_IMSR_BASE	0xFE964D80
270 #define MEDIA_AXI_IMSW_BASE	0xFE966D80
271 #define MEDIA_AXI_VSP1R_BASE	0xFE965100
272 #define MEDIA_AXI_VSP1W_BASE	0xFE967100
273 #define MEDIA_AXI_FDP1R_BASE	0xFE965140
274 #define MEDIA_AXI_FDP1W_BASE	0xFE967140
275 #define MEDIA_AXI_IMRR_BASE	0xFE965180
276 #define MEDIA_AXI_IMRW_BASE	0xFE967180
277 #define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
278 #define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
279 #define MEDIA_AXI_DU1R_BASE	0xFE9655C0
280 #define MEDIA_AXI_DU1W_BASE	0xFE9675C0
281 #define MEDIA_AXI_VCP0CR_BASE	0xFE965900
282 #define MEDIA_AXI_VCP0CW_BASE	0xFE967900
283 #define MEDIA_AXI_VCP0VR_BASE	0xFE965940
284 #define MEDIA_AXI_VCP0VW_BASE	0xFE967940
285 #define MEDIA_AXI_VPC0R_BASE	0xFE965980
286 #define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
287 #define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
288 #define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
289 #define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
290 #define MEDIA_AXI_VPC1R_BASE	0xFE965D80
291 
292 #if defined (CONFIG_R8A7792)
293 #define MEDIA_AXI_VCTU0R_BASE	0xFE964500 /* R8A7792 */
294 #define MEDIA_AXI_VCTU0W_BASE	0xFE966500
295 #define MEDIA_AXI_VDCTU0R_BASE	0xFE964540
296 #define MEDIA_AXI_VDCTU0W_BASE	0xFE966540
297 #define MEDIA_AXI_VDCTU1R_BASE	0xFE964580
298 #define MEDIA_AXI_VDCTU1W_BASE	0xFE966580
299 #define MEDIA_AXI_VIN0W_BASE	0xFE967580
300 #define MEDIA_AXI_VIN1W_BASE	0xFE966D80
301 #define MEDIA_AXI_RDRW_BASE	0xFE9675C0
302 #define MEDIA_AXI_IMS01R_BASE	0xFE965500
303 #define MEDIA_AXI_IMS01W_BASE	0xFE967500
304 #define MEDIA_AXI_IMS23R_BASE	0xFE965540 /* FIXME */
305 #define MEDIA_AXI_IMS23W_BASE	0xFE967540
306 #define MEDIA_AXI_IMS45R_BASE	0xFE964D00
307 #define MEDIA_AXI_IMS45W_BASE	0xFE966D00
308 #define MEDIA_AXI_ROTCE4R_BASE	0xFE965100
309 #define MEDIA_AXI_ROTCE4W_BASE	0xFE967100
310 #define MEDIA_AXI_ROTVLC4R_BASE	0xFE965140
311 #define MEDIA_AXI_ROTVLC4W_BASE	0xFE965140
312 #define MEDIA_AXI_VSPD0R_BASE	0xFE964900
313 #define MEDIA_AXI_VSPD0W_BASE	0xFE966900
314 #define MEDIA_AXI_VSPD1R_BASE	0xFE964940
315 #define MEDIA_AXI_VSPD1W_BASE	0xFE966940
316 #define MEDIA_AXI_DU0R_BASE	0xFE964980
317 #define MEDIA_AXI_DU0W_BASE	0xFE966980
318 #define MEDIA_AXI_VSP0R_BASE	0xFE9649C0
319 #define MEDIA_AXI_VSP0W_BASE	0xFE9669C0
320 #define MEDIA_AXI_ROTCE0R_BASE	0xFE965900
321 #define MEDIA_AXI_ROTCE0W_BASE	0xFE967900
322 #define MEDIA_AXI_ROTVLC0R_BASE	0xFE965940
323 #define MEDIA_AXI_ROTVLC0W_BASE	0xFE967940
324 #define MEDIA_AXI_ROTCE1R_BASE	0xFE965980
325 #define MEDIA_AXI_ROTCE1W_BASE	0xFE967980
326 #define MEDIA_AXI_ROTVLC1R_BASE	0xFE9659C0
327 #define MEDIA_AXI_ROTVLC1W_BASE	0xFE9679C0
328 #define MEDIA_AXI_ROTCE2R_BASE	0xFE965D00
329 #define MEDIA_AXI_ROTCE2W_BASE	0xFE967D00
330 #define MEDIA_AXI_ROTVLC2R_BASE	0xFE965D40
331 #define MEDIA_AXI_ROTVLC2W_BASE	0xFE967D40
332 #define MEDIA_AXI_ROTCE3R_BASE	0xFE965D80
333 #define MEDIA_AXI_ROTCE3W_BASE	0xFE967D80
334 #define MEDIA_AXI_ROTVLC3R_BASE	0xFE965DC0
335 #define MEDIA_AXI_ROTVLC3W_BASE	0xFE967DC0
336 #else	/* R8A7792 */
337 #define MEDIA_AXI_VIN0W_BASE	0xFE966900
338 #define MEDIA_AXI_VSPD0R_BASE	0xFE965500
339 #define MEDIA_AXI_VSPD0W_BASE	0xFE967500
340 #define MEDIA_AXI_VSPD1R_BASE	0xFE965540
341 #define MEDIA_AXI_VSPD1W_BASE	0xFE967540
342 #define MEDIA_AXI_DU0R_BASE	0xFE965580
343 #define MEDIA_AXI_DU0W_BASE	0xFE967580
344 #define MEDIA_AXI_VSP0R_BASE	0xFE964D00
345 #define MEDIA_AXI_VSP0W_BASE	0xFE966D00
346 #endif	/* R8A7792 */
347 
348 
349 #define SYS_AXI_AVBDMSCR	0xFF802000
350 #define SYS_AXI_SYX2DMSCR	0xFF802004
351 #define SYS_AXI_AX2MDMSCR	0xFF802004
352 #define SYS_AXI_CC50DMSCR	0xFF802008
353 #define SYS_AXI_CC51DMSCR	0xFF80200C
354 #define SYS_AXI_CCIDMSCR	0xFF802010
355 #define SYS_AXI_CSDMSCR		0xFF802014
356 #define SYS_AXI_DDMDMSCR	0xFF802018
357 #define SYS_AXI_ETHDMSCR	0xFF80201C
358 #define SYS_AXI_G2DDMSCR	0xFF802020
359 #define SYS_AXI_IMP0DMSCR	0xFF802024
360 #define SYS_AXI_IMP1DMSCR	0xFF802028
361 #define SYS_AXI_LBSDMSCR	0xFF80202C
362 #define SYS_AXI_MMUDSDMSCR	0xFF802030
363 #define SYS_AXI_MMUMXDMSCR	0xFF802034
364 #define SYS_AXI_MMURDDMSCR	0xFF802038
365 #define SYS_AXI_MMUS0DMSCR	0xFF80203C
366 #define SYS_AXI_MMUS1DMSCR	0xFF802040
367 #define SYS_AXI_MPXDMSCR	0xFF802044
368 #define SYS_AXI_MTSB0DMSCR	0xFF802048
369 #define SYS_AXI_MTSB1DMSCR	0xFF80204C
370 #define SYS_AXI_PCIDMSCR	0xFF802050
371 #define SYS_AXI_RTXDMSCR	0xFF802054
372 #define SYS_AXI_SAT0DMSCR	0xFF802058
373 #define SYS_AXI_SAT1DMSCR	0xFF80205C
374 #define SYS_AXI_SDM0DMSCR	0xFF802060
375 #define SYS_AXI_SDM1DMSCR	0xFF802064
376 #define SYS_AXI_SDS0DMSCR	0xFF802068
377 #define SYS_AXI_SDS1DMSCR	0xFF80206C
378 #define SYS_AXI_ETRABDMSCR	0xFF802070
379 #define SYS_AXI_ETRKFDMSCR	0xFF802074
380 #define SYS_AXI_UDM0DMSCR	0xFF802078
381 #define SYS_AXI_UDM1DMSCR	0xFF80207C
382 #define SYS_AXI_USB20DMSCR	0xFF802080
383 #define SYS_AXI_USB21DMSCR	0xFF802084
384 #define SYS_AXI_USB22DMSCR	0xFF802088
385 #define SYS_AXI_USB30DMSCR	0xFF80208C
386 #define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
387 #define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
388 #define SYS_AXI_AVBSLVDMSCR	0xFF802108
389 #define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
390 #define SYS_AXI_AX2SLVDMSCR	0xFF80210C
391 #define SYS_AXI_ETHSLVDMSCR	0xFF802110
392 #define SYS_AXI_GICSLVDMSCR	0xFF802114
393 #define SYS_AXI_IMPSLVDMSCR	0xFF802118
394 #define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
395 #define SYS_AXI_IMX1SLVDMSCR	0xFF802120
396 #define SYS_AXI_IMX2SLVDMSCR	0xFF802124
397 #define SYS_AXI_LBSSLVDMSCR	0xFF802128
398 #define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
399 #define SYS_AXI_MMC1SLVDMSCR	0xFF802130
400 #define SYS_AXI_MPXSLVDMSCR	0xFF802134
401 #define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
402 #define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
403 #define SYS_AXI_MXTSLVDMSCR	0xFF802140
404 #define SYS_AXI_PCISLVDMSCR	0xFF802144
405 #define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
406 #define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
407 #define SYS_AXI_RTXSLVDMSCR	0xFF802150
408 #define SYS_AXI_SAPC1SLVDMSCR	0xFF802154
409 #define SYS_AXI_SAPC2SLVDMSCR	0xFF802158
410 #define SYS_AXI_SAPC3SLVDMSCR	0xFF80215C
411 #define SYS_AXI_SAPC65SLVDMSCR	0xFF802160
412 #define SYS_AXI_SAPC8SLVDMSCR	0xFF802164
413 #define SYS_AXI_SAT0SLVDMSCR	0xFF802168
414 #define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
415 #define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
416 #define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
417 #define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
418 #define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
419 #define SYS_AXI_SGXSLVDMSCR	0xFF802180
420 #define SYS_AXI_SGXSLV1SLVDMSCR	0xFF802184
421 #define SYS_AXI_STBSLVDMSCR	0xFF802188
422 #define SYS_AXI_STMSLVDMSCR	0xFF80218C
423 #define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR	0xFF802190
424 #define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
425 #define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
426 #define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
427 #define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
428 #define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
429 #define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
430 #define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
431 #define SYS_AXI_UTLBDSSLVDMSCR	0xFF8021B0
432 #define SYS_AXI_UTLBS0SLVDMSCR	0xFF8021B4
433 #define SYS_AXI_UTLBS1SLVDMSCR	0xFF8021B8
434 #define	SYS_AXI_ROT0DMSCR	0xFF802320
435 #define	SYS_AXI_ROT1DMSCR	0xFF802324
436 #define	SYS_AXI_ROT2DMSCR	0xFF802328
437 #define	SYS_AXI_ROT3DMSCR	0xFF80232C
438 #define	SYS_AXI_ROT4DMSCR	0xFF802330
439 #define	SYS_AXI_IMUX3SLVDMSCR	0xFF802334
440 #define	SYS_AXI_STBR0SLVDMSCR	0xFF803200
441 #define	SYS_AXI_STBR0PSLVDMSCR	0xFF803204
442 #define	SYS_AXI_STBR0XSLVDMSCR	0xFF803208
443 #define	SYS_AXI_STBR1SLVDMSCR	0xFF803210
444 #define	SYS_AXI_STBR1PSLVDMSCR	0xFF803214
445 #define	SYS_AXI_STBR1XSLVDMSCR	0xFF803218
446 #define	SYS_AXI_STBR2SLVDMSCR	0xFF803220
447 #define	SYS_AXI_STBR2PSLVDMSCR	0xFF803224
448 #define	SYS_AXI_STBR2XSLVDMSCR	0xFF803228
449 #define	SYS_AXI_STBR3SLVDMSCR	0xFF803230
450 #define	SYS_AXI_STBR3PSLVDMSCR	0xFF803234
451 #define	SYS_AXI_STBR3XSLVDMSCR	0xFF803238
452 #define	SYS_AXI_STBR4SLVDMSCR	0xFF803240
453 #define	SYS_AXI_STBR4PSLVDMSCR	0xFF803244
454 #define	SYS_AXI_STBR4XSLVDMSCR	0xFF803248
455 #define	SYS_AXI_ADM_DMSCR	0xFF803260
456 #define	SYS_AXI_ADS_DMSCR	0xFF803264
457 
458 #define RT_AXI_CBMDMSCR		0xFF812000
459 #define RT_AXI_DBDMSCR		0xFF812004
460 #define RT_AXI_RDMDMSCR		0xFF812008
461 #define RT_AXI_RDSDMSCR		0xFF81200C
462 #define RT_AXI_STRDMSCR		0xFF812010
463 #define RT_AXI_SY2RTDMSCR	0xFF812014
464 #define RT_AXI_CBSSLVDMSCR	0xFF812100
465 #define RT_AXI_DBSSLVDMSCR	0xFF812104
466 #define RT_AXI_RTAP1SLVDMSCR	0xFF812108
467 #define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
468 #define RT_AXI_RTAP3SLVDMSCR	0xFF812110
469 #define RT_AXI_RT2SYSLVDMSCR	0xFF812114
470 #define RT_AXI_A128TO64SLVDMSCR	0xFF812118
471 #define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
472 #define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
473 #define RT_AXI_UTLBRSLVDMSCR	0xFF812128
474 
475 #define MP_AXI_ADSPDMSCR	0xFF822000
476 #define MP_AXI_ASDM0DMSCR	0xFF822004
477 #define MP_AXI_ASDM1DMSCR	0xFF822008
478 #define MP_AXI_ASDS0DMSCR	0xFF82200C
479 #define MP_AXI_ASDS1DMSCR	0xFF822010
480 #define MP_AXI_MLPDMSCR		0xFF822014
481 #define MP_AXI_MMUMPDMSCR	0xFF822018
482 #define MP_AXI_SPUDMSCR		0xFF82201C
483 #define MP_AXI_SPUCDMSCR	0xFF822020
484 #define MP_AXI_SY2MPDMSCR	0xFF822024
485 #define MP_AXI_ADSPSLVDMSCR	0xFF822100
486 #define MP_AXI_MLMSLVDMSCR	0xFF822104
487 #define MP_AXI_MPAP4SLVDMSCR	0xFF822108
488 #define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
489 #define MP_AXI_MPAP6SLVDMSCR	0xFF822110
490 #define MP_AXI_MPAP7SLVDMSCR	0xFF822114
491 #define MP_AXI_MP2SYSLVDMSCR	0xFF822118
492 #define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
493 #define MP_AXI_MPXAPSLVDMSCR	0xFF822124
494 #define MP_AXI_SPUSLVDMSCR	0xFF822128
495 #define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
496 
497 #define ADM_AXI_ASDM0DMSCR	0xFF842000
498 #define ADM_AXI_ASDM1DMSCR	0xFF842004
499 #define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
500 #define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
501 #define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
502 
503 #define	DM_AXI_DMAXICONF	0xFF850000
504 #define	DM_AXI_DMAPBCONF	0xFF850004
505 #define	DM_AXI_DMADMCONF	0xFF850020
506 #define	DM_AXI_DMSDM0CONF	0xFF850024
507 #define	DM_AXI_DMSDM1CONF	0xFF850028
508 #define	DM_AXI_DMQSPAPSLVCONF	0xFF850030
509 #define	DM_AXI_RAPD4SLVCONF	0xFF850034
510 #define	DM_AXI_SAPD4SLVCONF	0xFF85003C
511 #define	DM_AXI_SAPD5SLVCONF	0xFF850040
512 #define	DM_AXI_SAPD6SLVCONF	0xFF850044
513 #define	DM_AXI_SAPD65DSLVCONF	0xFF850048
514 #define	DM_AXI_SDAP0SLVCONF	0xFF85004C
515 #define	DM_AXI_MAPD2SLVCONF	0xFF850050
516 #define	DM_AXI_MAPD3SLVCONF	0xFF850054
517 #define	DM_AXI_DMXXDEFAULTSLAVESLVCONF	0xFF850058
518 #define	DM_AXI_DMADMRQOSCONF	0xFF850100
519 #define	DM_AXI_DMADMRQOSCTSET0	0xFF850104
520 #define	DM_AXI_DMADMRQOSREQCTR	0xFF850114
521 #define	DM_AXI_DMADMRQOSQON	0xFF850124
522 #define	DM_AXI_DMADMRQOSIN	0xFF850128
523 #define	DM_AXI_DMADMRQOSSTAT	0xFF85012C
524 #define	DM_AXI_DMSDM0RQOSCONF	0xFF850140
525 #define	DM_AXI_DMSDM0RQOSCTSET0	0xFF850144
526 #define	DM_AXI_DMSDM0RQOSREQCTR	0xFF850154
527 #define	DM_AXI_DMSDM0RQOSQON	0xFF850164
528 #define	DM_AXI_DMSDM0RQOSIN	0xFF850168
529 #define	DM_AXI_DMSDM0RQOSSTAT	0xFF85016C
530 #define	DM_AXI_DMSDM1RQOSCONF	0xFF850180
531 #define	DM_AXI_DMSDM1RQOSCTSET0	0xFF850184
532 #define	DM_AXI_DMSDM1RQOSREQCTR	0xFF850194
533 #define	DM_AXI_DMSDM1RQOSQON	0xFF8501A4
534 #define	DM_AXI_DMSDM1RQOSIN	0xFF8501A8
535 #define	DM_AXI_DMSDM1RQOSSTAT	0xFF8501AC
536 #define	DM_AXI_DMRQOSCTSET1	0xFF850FC0
537 #define	DM_AXI_DMRQOSCTSET2	0xFF850FC4
538 #define	DM_AXI_DMRQOSCTSET3	0xFF850FC8
539 #define	DM_AXI_DMRQOSTHRES0	0xFF850FCC
540 #define	DM_AXI_DMRQOSTHRES1	0xFF850FD0
541 #define	DM_AXI_DMRQOSTHRES2	0xFF850FD4
542 #define	DM_AXI_DMADMWQOSCONF	0xFF851100
543 #define	DM_AXI_DMADMWQOSCTSET0	0xFF851104
544 #define	DM_AXI_DMADMWQOSREQCTR	0xFF851114
545 #define	DM_AXI_DMADMWQOSQON	0xFF851124
546 #define	DM_AXI_DMADMWQOSIN	0xFF851128
547 #define	DM_AXI_DMADMWQOSSTAT	0xFF85112C
548 #define	DM_AXI_DMSDM0WQOSCONF	0xFF851140
549 #define	DM_AXI_DMSDM0WQOSCTSET0	0xFF851144
550 #define	DM_AXI_DMSDM0WQOSREQCTR	0xFF851154
551 #define	DM_AXI_DMSDM0WQOSQON	0xFF851164
552 #define	DM_AXI_DMSDM0WQOSIN	0xFF851168
553 #define	DM_AXI_DMSDM0WQOSSTAT	0xFF85116C
554 #define	DM_AXI_DMSDM1WQOSCONF	0xFF851180
555 #define	DM_AXI_DMSDM1WQOSCTSET0	0xFF851184
556 #define	DM_AXI_DMSDM1WQOSREQCTR	0xFF851194
557 #define	DM_AXI_DMSDM1WQOSQON	0xFF8511A4
558 #define	DM_AXI_DMSDM1WQOSIN	0xFF8511A8
559 #define	DM_AXI_DMSDM1WQOSSTAT	0xFF8511AC
560 #define	DM_AXI_DMWQOSCTSET1	0xFF851FC0
561 #define	DM_AXI_DMWQOSCTSET2	0xFF851FC4
562 #define	DM_AXI_DMWQOSCTSET3	0xFF851FC8
563 #define	DM_AXI_DMWQOSTHRES0	0xFF851FCC
564 #define	DM_AXI_DMWQOSTHRES1	0xFF851FD0
565 #define	DM_AXI_DMWQOSTHRES2	0xFF851FD4
566 
567 #define DM_AXI_RDMDMSCR		0xFF852000
568 #define DM_AXI_SDM0DMSCR	0xFF852004
569 #define DM_AXI_SDM1DMSCR	0xFF852008
570 #if defined(CONFIG_R8A7792)
571 #define	DM_AXI_DMQSPAPSLVDMSCR	0xFF852104
572 #define	DM_AXI_RAPD4SLVDMSCR	0xFF852108
573 #define	DM_AXI_SAPD4SLVDMSCR	0xFF852110
574 #define	DM_AXI_SAPD5SLVDMSCR	0xFF852114
575 #define	DM_AXI_SAPD6SLVDMSCR	0xFF852118
576 #define	DM_AXI_SAPD65DSLVDMSCR	0xFF85211C
577 #define	DM_AXI_SDAP0SLVDMSCR	0xFF852120
578 #define	DM_AXI_MAPD2SLVDMSCR	0xFF852124
579 #define	DM_AXI_MAPD3SLVDMSCR	0xFF852128
580 #define	DM_AXI_DMXXDEFAULTSLAVESLVDMSCR	0xFF85212C
581 #define	DM_AXI_DMXREGDMSENN	0xFF852200
582 #else
583 #define DM_AXI_MMAP0SLVDMSCR	0xFF852100
584 #define DM_AXI_MMAP1SLVDMSCR	0xFF852104
585 #define DM_AXI_QSPAPSLVDMSCR	0xFF852108
586 #define DM_AXI_RAP4SLVDMSCR	0xFF85210C
587 #define DM_AXI_RAP5SLVDMSCR	0xFF852110
588 #define DM_AXI_SAP4SLVDMSCR	0xFF852114
589 #define DM_AXI_SAP5SLVDMSCR	0xFF852118
590 #define DM_AXI_SAP6SLVDMSCR	0xFF85211C
591 #define DM_AXI_SAP65SLVDMSCR	0xFF852120
592 #define DM_AXI_SDAP0SLVDMSCR	0xFF852124
593 #define DM_AXI_SDAP1SLVDMSCR	0xFF852128
594 #define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
595 #define DM_AXI_SDAP3SLVDMSCR	0xFF852130
596 #endif
597 
598 #define SYS_AXI256_SYXDMSCR	0xFF862000
599 #define SYS_AXI256_MPXDMSCR	0xFF862004
600 #define SYS_AXI256_MXIDMSCR	0xFF862008
601 #define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
602 #define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
603 #define SYS_AXI256_SYXSLVDMSCR	0xFF862108
604 #define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
605 #define SYS_AXI256_S3CSLVDMSCR	0xFF862110
606 
607 #define MXT_SYXDMSCR		0xFF872000
608 #if defined(CONFIG_R8A7792)
609 #define	MXT_IMRSLVDMSCR		0xFF872110
610 #define	MXT_VINSLVDMSCR		0xFF872114
611 #define	MXT_VSP1SLVDMSCR	0xFF87211C
612 #define	MXT_VSPD0SLVDMSCR	0xFF872120
613 #define	MXT_VSPD1SLVDMSCR	0xFF872124
614 #define	MXT_MAP1SLVDMSCR	0xFF872128
615 #define	MXT_MAP2SLVDMSCR	0xFF87212C
616 #define	MXT_MAP2BSLVDMSCR	0xFF872134
617 #else	/* R8A7792 */
618 #define MXT_CMM0SLVDMSCR	0xFF872100
619 #define MXT_CMM1SLVDMSCR	0xFF872104
620 #define MXT_CMM2SLVDMSCR	0xFF872108
621 #define MXT_FDPSLVDMSCR		0xFF87210C
622 #define MXT_IMRSLVDMSCR		0xFF872110
623 #define MXT_VINSLVDMSCR		0xFF872114
624 #define MXT_VPC0SLVDMSCR	0xFF872118
625 #define MXT_VPC1SLVDMSCR	0xFF87211C
626 #define MXT_VSP0SLVDMSCR	0xFF872120
627 #define MXT_VSP1SLVDMSCR	0xFF872124
628 #define MXT_VSPD0SLVDMSCR	0xFF872128
629 #define MXT_VSPD1SLVDMSCR	0xFF87212C
630 #define MXT_MAP1SLVDMSCR	0xFF872130
631 #define MXT_MAP2SLVDMSCR	0xFF872134
632 #endif	/* R8A7792 */
633 
634 /* DMS Register (MXI) */
635 #if defined(CONFIG_R8A7792)
636 #define	MXI_JPURDMSCR		0xFE964200
637 #define	MXI_JPUWDMSCR		0xFE966200
638 #define	MXI_VCTU0RDMSCR		0xFE964600
639 #define	MXI_VCTU0WDMSCR		0xFE966600
640 #define	MXI_VDCTU0RDMSCR	0xFE964604
641 #define	MXI_VDCTU0WDMSCR	0xFE966604
642 #define	MXI_VDCTU1RDMSCR	0xFE964608
643 #define	MXI_VDCTU1WDMSCR	0xFE966608
644 #define	MXI_VIN0WDMSCR		0xFE967608
645 #define	MXI_VIN1WDMSCR		0xFE966E08
646 #define	MXI_RDRWDMSCR		0xFE96760C
647 #define	MXI_IMS01RDMSCR		0xFE965600
648 #define	MXI_IMS01WDMSCR		0xFE967600
649 #define	MXI_IMS23RDMSCR		0xFE965604
650 #define	MXI_IMS23WDMSCR		0xFE967604
651 #define	MXI_IMS45RDMSCR		0xFE964E00
652 #define	MXI_IMS45WDMSCR		0xFE966E00
653 #define	MXI_IMRRDMSCR		0xFE964E04
654 #define	MXI_IMRWDMSCR		0xFE966E04
655 #define	MXI_ROTCE4RDMSCR	0xFE965200
656 #define	MXI_ROTCE4WDMSCR	0xFE967200
657 #define	MXI_ROTVLC4RDMSCR	0xFE965204
658 #define	MXI_ROTVLC4WDMSCR	0xFE967204
659 #define	MXI_VSPD0RDMSCR		0xFE964A00
660 #define	MXI_VSPD0WDMSCR		0xFE966A00
661 #define	MXI_VSPD1RDMSCR		0xFE964A04
662 #define	MXI_VSPD1WDMSCR		0xFE966A04
663 #define	MXI_DU0RDMSCR		0xFE964A08
664 #define	MXI_DU0WDMSCR		0xFE966A08
665 #define	MXI_VSP0RDMSCR		0xFE964A0C
666 #define	MXI_VSP0WDMSCR		0xFE966A0C
667 #define	MXI_ROTCE0RDMSCR	0xFE965A00
668 #define	MXI_ROTCE0WDMSCR	0xFE967A00
669 #define	MXI_ROTVLC0RDMSCR	0xFE965A04
670 #define	MXI_ROTVLC0WDMSCR	0xFE967A04
671 #define	MXI_ROTCE1RDMSCR	0xFE965A08
672 #define	MXI_ROTCE1WDMSCR	0xFE967A08
673 #define	MXI_ROTVLC1RDMSCR	0xFE965A0C
674 #define	MXI_ROTVLC1WDMSCR	0xFE967A0C
675 #define	MXI_ROTCE2RDMSCR	0xFE965E00
676 #define	MXI_ROTCE2WDMSCR	0xFE967E00
677 #define	MXI_ROTVLC2RDMSCR	0xFE965E04
678 #define	MXI_ROTVLC2WDMSCR	0xFE967E04
679 #define	MXI_ROTCE3RDMSCR	0xFE965E08
680 #define	MXI_ROTCE3WDMSCR	0xFE967E08
681 #define	MXI_ROTVLC3RDMSCR	0xFE965E0C
682 #define	MXI_ROTVLC3WDMSCR	0xFE967E0C
683 #endif	/* R8A7792 */
684 
685 #define CCI_AXI_MMUS0DMSCR	0xFF882000
686 #define CCI_AXI_SYX2DMSCR	0xFF882004
687 #define CCI_AXI_MMURDMSCR	0xFF882008
688 #define CCI_AXI_MMUDSDMSCR	0xFF88200C
689 #define CCI_AXI_MMUMDMSCR	0xFF882010
690 #define CCI_AXI_MXIDMSCR	0xFF882014
691 #define CCI_AXI_MMUS1DMSCR	0xFF882018
692 #define CCI_AXI_MMUMPDMSCR	0xFF88201C
693 #define CCI_AXI_DVMDMSCR	0xFF882020
694 #define CCI_AXI_CCISLVDMSCR	0xFF882100
695 
696 #define CCI_AXI_IPMMUIDVMCR	0xFF880400
697 #define CCI_AXI_IPMMURDVMCR	0xFF880404
698 #define CCI_AXI_IPMMUS0DVMCR	0xFF880408
699 #define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
700 #define CCI_AXI_IPMMUMPDVMCR	0xFF880410
701 #define CCI_AXI_IPMMUDSDVMCR	0xFF880414
702 #define CCI_AXI_AX2ADDRMASK	0xFF88041C
703 
704 #define PLL0CR			0xE61500D8
705 #define PLL0_STC_MASK		0x7F000000
706 #define PLL0_STC_BIT		24
707 #define PLLECR			0xE61500D0
708 #define PLL0ST			0x100
709 
710 #ifndef __ASSEMBLY__
711 #include <asm/types.h>
712 
713 /* RWDT */
714 struct rcar_rwdt {
715 	u32 rwtcnt;	/* 0x00 */
716 	u32 rwtcsra;	/* 0x04 */
717 	u16 rwtcsrb;	/* 0x08 */
718 };
719 
720 /* SWDT */
721 struct rcar_swdt {
722 	u32 swtcnt;	/* 0x00 */
723 	u32 swtcsra;	/* 0x04 */
724 	u16 swtcsrb;	/* 0x08 */
725 };
726 
727 /* LBSC */
728 struct rcar_lbsc {
729 	u32 cs0ctrl;
730 	u32 cs1ctrl;
731 	u32 ecs0ctrl;
732 	u32 ecs1ctrl;
733 	u32 ecs2ctrl;
734 	u32 ecs3ctrl;
735 	u32 ecs4ctrl;
736 	u32 ecs5ctrl;
737 	u32 dummy0[4];	/* 0x20 .. 0x2C */
738 	u32 cswcr0;
739 	u32 cswcr1;
740 	u32 ecswcr0;
741 	u32 ecswcr1;
742 	u32 ecswcr2;
743 	u32 ecswcr3;
744 	u32 ecswcr4;
745 	u32 ecswcr5;
746 	u32 exdmawcr0;
747 	u32 exdmawcr1;
748 	u32 exdmawcr2;
749 	u32 dummy1[9];	/* 0x5C .. 0x7C */
750 	u32 cspwcr0;
751 	u32 cspwcr1;
752 	u32 ecspwcr0;
753 	u32 ecspwcr1;
754 	u32 ecspwcr2;
755 	u32 ecspwcr3;
756 	u32 ecspwcr4;
757 	u32 ecspwcr5;
758 	u32 exwtsync;
759 	u32 dummy2[3];	/* 0xA4 .. 0xAC */
760 	u32 cs0bstctl;
761 	u32 cs0btph;
762 	u32 dummy3[2];	/* 0xB8 .. 0xBC */
763 	u32 cs1gdst;
764 	u32 ecs0gdst;
765 	u32 ecs1gdst;
766 	u32 ecs2gdst;
767 	u32 ecs3gdst;
768 	u32 ecs4gdst;
769 	u32 ecs5gdst;
770 	u32 dummy4[5];	/* 0xDC .. 0xEC */
771 	u32 exdmaset0;
772 	u32 exdmaset1;
773 	u32 exdmaset2;
774 	u32 dummy5[5];	/* 0xFC .. 0x10C */
775 	u32 exdmcr0;
776 	u32 exdmcr1;
777 	u32 exdmcr2;
778 	u32 dummy6[5];	/* 0x11C .. 0x12C */
779 	u32 bcintsr;
780 	u32 bcintcr;
781 	u32 bcintmr;
782 	u32 dummy7;	/* 0x13C */
783 	u32 exbatlv;
784 	u32 exwtsts;
785 	u32 dummy8[14];	/* 0x148 .. 0x17C */
786 	u32 atacsctrl;
787 	u32 dummy9[15]; /* 0x184 .. 0x1BC */
788 	u32 exbct;
789 	u32 extct;
790 };
791 
792 /* DBSC3 */
793 struct rcar_dbsc3 {
794 	u32 dummy0[3];	/* 0x00 .. 0x08 */
795 	u32 dbstate1;
796 	u32 dbacen;
797 	u32 dbrfen;
798 	u32 dbcmd;
799 	u32 dbwait;
800 	u32 dbkind;
801 	u32 dbconf0;
802 	u32 dummy1[2];	/* 0x28 .. 0x2C */
803 	u32 dbphytype;
804 	u32 dummy2[3];	/* 0x34 .. 0x3C */
805 	u32 dbtr0;
806 	u32 dbtr1;
807 	u32 dbtr2;
808 	u32 dummy3;	/* 0x4C */
809 	u32 dbtr3;
810 	u32 dbtr4;
811 	u32 dbtr5;
812 	u32 dbtr6;
813 	u32 dbtr7;
814 	u32 dbtr8;
815 	u32 dbtr9;
816 	u32 dbtr10;
817 	u32 dbtr11;
818 	u32 dbtr12;
819 	u32 dbtr13;
820 	u32 dbtr14;
821 	u32 dbtr15;
822 	u32 dbtr16;
823 	u32 dbtr17;
824 	u32 dbtr18;
825 	u32 dbtr19;
826 	u32 dummy4[7];	/* 0x94 .. 0xAC */
827 	u32 dbbl;
828 	u32 dummy5[3];	/* 0xB4 .. 0xBC */
829 	u32 dbadj0;
830 	u32 dummy6;	/* 0xC4 */
831 	u32 dbadj2;
832 	u32 dummy7[5];	/* 0xCC .. 0xDC */
833 	u32 dbrfcnf0;
834 	u32 dbrfcnf1;
835 	u32 dbrfcnf2;
836 	u32 dummy8[2];	/* 0xEC .. 0xF0 */
837 	u32 dbcalcnf;
838 	u32 dbcaltr;
839 	u32 dummy9;	/* 0xFC */
840 	u32 dbrnk0;
841 	u32 dummy10[31];	/* 0x104 .. 0x17C */
842 	u32 dbpdncnf;
843 	u32 dummy11[47];	/* 0x184 ..0x23C */
844 	u32 dbdfistat;
845 	u32 dbdficnt;
846 	u32 dummy12[14];	/* 0x248 .. 0x27C */
847 	u32 dbpdlck;
848 	u32 dummy13[3];	/* 0x284 .. 0x28C */
849 	u32 dbpdrga;
850 	u32 dummy14[3];	/* 0x294 .. 0x29C */
851 	u32 dbpdrgd;
852 	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
853 	u32 dbbs0cnt1;
854 	u32 dummy16[30];	/* 0x308 .. 0x37C */
855 	u32 dbwt0cnf0;
856 	u32 dbwt0cnf1;
857 	u32 dbwt0cnf2;
858 	u32 dbwt0cnf3;
859 	u32 dbwt0cnf4;
860 	u32 dummy17[27];	/* 0x394 .. 0x3FC */
861 	u32 dbeccmode;
862 	u32 dummy18[3];		/* 0x404 .. 0x40C */
863 	u32 dbeccarea0;
864 	u32 dbeccarea1;
865 	u32 dbeccarea2;
866 	u32 dbeccarea3;
867 	u32 dummy19[4];		/* 0x420 .. 0x42C */
868 	u32 dbeccintenable;
869 	u32 dbeccintdetect;
870 	u32 dummy20[22];	/* 0x438 .. 0x48C */
871 	u32 dbeccmodulcnt;
872 	u32 dummy21[27];	/* 0x494 .. 0x4FC */
873 	u32 dbschecnt0;
874 	u32 dummy22[63];	/* 0x504 .. 0x5FC */
875 	u32 dbreradr0;
876 	u32 dbreblane0;
877 	u32 dbrerid0;
878 	u32 dbrerinfo0;
879 	u32 dbureradr0;
880 	u32 dbureblane0;
881 	u32 dburerid0;
882 	u32 dburerinfo0;
883 	u32 dbreradr1;
884 	u32 dbreblane1;
885 	u32 dbrerid1;
886 	u32 dbrerinfo1;
887 	u32 dbureradr1;
888 	u32 dbureblane1;
889 	u32 dburerid1;
890 	u32 dburerinfo1;
891 	u32 dbreradr2;
892 	u32 dbreblane2;
893 	u32 dbrerid2;
894 	u32 dbrerinfo2;
895 	u32 dbureradr2;
896 	u32 dbureblane2;
897 	u32 dburerid2;
898 	u32 dburerinfo2;
899 	u32 dbreradr3;
900 	u32 dbreblane3;
901 	u32 dbrerid3;
902 	u32 dbrerinfo3;
903 	u32 dbureradr3;
904 	u32 dbureblane3;
905 	u32 dburerid3;
906 	u32 dburerinfo3;
907 	u32 dummy23[160];	/* 0x680 .. 0x8FC */
908 	u32 dbpccr;
909 	u32 dbpeier;
910 	u32 dbpeisr;
911 	u32 dummy24;
912 	u32 dbwdpesr0;
913 	u32 dbwspesr0;
914 	u32 dbpwear0;
915 	u32 dbpweid0;
916 	u32 dbpweinfo0;
917 	u32 dummy25[3];		/* 0x924 .. 0x92C */
918 	u32 dbwdpesr1;
919 	u32 dbwspesr1;
920 	u32 dbpwear1;
921 	u32 dbpweid1;
922 	u32 dbpweinfo1;
923 	u32 dummy26[3];		/* 0x944 .. 0x94C */
924 	u32 dbwdpesr2;
925 	u32 dbwspesr2;
926 	u32 dbpwear2;
927 	u32 dbpweid2;
928 	u32 dbpweinfo2;
929 	u32 dummy27[3];		/* 0x964 .. 0x96C */
930 	u32 dbwdpesr3;
931 	u32 dbwspesr3;
932 	u32 dbpwear3;
933 	u32 dbpweid3;
934 	u32 dbpweinfo3;
935 };
936 
937 /* GPIO */
938 struct rcar_gpio {
939 	u32 iointsel;
940 	u32 inoutsel;
941 	u32 outdt;
942 	u32 indt;
943 	u32 intdt;
944 	u32 intclr;
945 	u32 intmsk;
946 	u32 posneg;
947 	u32 edglevel;
948 	u32 filonoff;
949 	u32 intmsks;
950 	u32 mskclrs;
951 	u32 outdtsel;
952 	u32 outdth;
953 	u32 outdtl;
954 	u32 bothedge;
955 };
956 
957 /* S3C(QoS) */
958 struct rcar_s3c {
959 	u32 s3cexcladdmsk;
960 	u32 s3cexclidmsk;
961 	u32 s3cadsplcr;
962 	u32 s3cmaar;
963 	u32 s3carcr11;
964 	u32 s3crorr;
965 	u32 s3cworr;
966 	u32 s3carcr22;
967 	u32 dummy1[2];	/* 0x20 .. 0x24 */
968 	u32 s3cmctr;
969 	u32 dummy2;	/* 0x2C */
970 	u32 cconf0;
971 	u32 cconf1;
972 	u32 cconf2;
973 	u32 cconf3;
974 };
975 
976 struct rcar_s3c_qos {
977 	u32 s3cqos0;
978 	u32 s3cqos1;
979 	u32 s3cqos2;
980 	u32 s3cqos3;
981 	u32 s3cqos4;
982 	u32 s3cqos5;
983 	u32 s3cqos6;
984 	u32 s3cqos7;
985 	u32 s3cqos8;
986 };
987 
988 /* DBSC(QoS) */
989 struct rcar_dbsc3_qos {
990 	u32 dblgcnt;
991 	u32 dbtmval0;
992 	u32 dbtmval1;
993 	u32 dbtmval2;
994 	u32 dbtmval3;
995 	u32 dbrqctr;
996 	u32 dbthres0;
997 	u32 dbthres1;
998 	u32 dbthres2;
999 	u32 dummy0;	/* 0x24 */
1000 	u32 dblgqon;
1001 };
1002 
1003 /* MXI(QoS) */
1004 struct rcar_mxi {
1005 	u32 mxsaar0;
1006 	u32 mxsaar1;
1007 	u32 dummy0[7];	/* 0x08 .. 0x20 */
1008 	u32 mxaxiracr;	/* R8a7790 only */
1009 	u32 mxs3cracr;
1010 	u32 dummy1[2];	/* 0x2C .. 0x30 */
1011 	u32 mxaxiwacr;	/* R8a7790 only */
1012 	u32 mxs3cwacr;
1013 	u32 dummy2;	/* 0x3C */
1014 	u32 mxrtcr;
1015 	u32 mxwtcr;
1016 	u32 mxaxirtcr;	/* R8a7792 only */
1017 	u32 mxaxiwtcr;
1018 	u32 mxs3crtcr;
1019 	u32 mxs3cwtcr;
1020 };
1021 
1022 struct rcar_mxi_qos {
1023 	u32 vspdu0;
1024 	u32 vspdu1;
1025 	u32 du0;
1026 	u32 du1;
1027 };
1028 
1029 /* AXI(QoS) */
1030 struct rcar_axi_qos {
1031 	u32 qosconf;
1032 	u32 qosctset0;
1033 	u32 qosctset1;
1034 	u32 qosctset2;
1035 	u32 qosctset3;
1036 	u32 qosreqctr;
1037 	u32 qosthres0;
1038 	u32 qosthres1;
1039 	u32 qosthres2;
1040 	u32 qosqon;
1041 	u32 qosin;
1042 };
1043 
1044 #endif
1045 
1046 #endif /* __ASM_ARCH_RCAR_BASE_H */
1047