1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> 4 */ 5 6 #ifndef _CLOCK_MANAGER_GEN5_H_ 7 #define _CLOCK_MANAGER_GEN5_H_ 8 9 #ifndef __ASSEMBLER__ 10 11 struct cm_config { 12 /* main group */ 13 u32 main_vco_base; 14 u32 mpuclk; 15 u32 mainclk; 16 u32 dbgatclk; 17 u32 mainqspiclk; 18 u32 mainnandsdmmcclk; 19 u32 cfg2fuser0clk; 20 u32 maindiv; 21 u32 dbgdiv; 22 u32 tracediv; 23 u32 l4src; 24 25 /* peripheral group */ 26 u32 peri_vco_base; 27 u32 emac0clk; 28 u32 emac1clk; 29 u32 perqspiclk; 30 u32 pernandsdmmcclk; 31 u32 perbaseclk; 32 u32 s2fuser1clk; 33 u32 perdiv; 34 u32 gpiodiv; 35 u32 persrc; 36 37 /* sdram pll group */ 38 u32 sdram_vco_base; 39 u32 ddrdqsclk; 40 u32 ddr2xdqsclk; 41 u32 ddrdqclk; 42 u32 s2fuser2clk; 43 44 /* altera group */ 45 u32 altera_grp_mpuclk; 46 }; 47 48 struct socfpga_clock_manager_main_pll { 49 u32 vco; 50 u32 misc; 51 u32 mpuclk; 52 u32 mainclk; 53 u32 dbgatclk; 54 u32 mainqspiclk; 55 u32 mainnandsdmmcclk; 56 u32 cfgs2fuser0clk; 57 u32 en; 58 u32 maindiv; 59 u32 dbgdiv; 60 u32 tracediv; 61 u32 l4src; 62 u32 stat; 63 u32 _pad_0x38_0x40[2]; 64 }; 65 66 struct socfpga_clock_manager_per_pll { 67 u32 vco; 68 u32 misc; 69 u32 emac0clk; 70 u32 emac1clk; 71 u32 perqspiclk; 72 u32 pernandsdmmcclk; 73 u32 perbaseclk; 74 u32 s2fuser1clk; 75 u32 en; 76 u32 div; 77 u32 gpiodiv; 78 u32 src; 79 u32 stat; 80 u32 _pad_0x34_0x40[3]; 81 }; 82 83 struct socfpga_clock_manager_sdr_pll { 84 u32 vco; 85 u32 ctrl; 86 u32 ddrdqsclk; 87 u32 ddr2xdqsclk; 88 u32 ddrdqclk; 89 u32 s2fuser2clk; 90 u32 en; 91 u32 stat; 92 }; 93 94 struct socfpga_clock_manager_altera { 95 u32 mpuclk; 96 u32 mainclk; 97 }; 98 99 struct socfpga_clock_manager { 100 u32 ctrl; 101 u32 bypass; 102 u32 inter; 103 u32 intren; 104 u32 dbctrl; 105 u32 stat; 106 u32 _pad_0x18_0x3f[10]; 107 struct socfpga_clock_manager_main_pll main_pll; 108 struct socfpga_clock_manager_per_pll per_pll; 109 struct socfpga_clock_manager_sdr_pll sdr_pll; 110 struct socfpga_clock_manager_altera altera; 111 u32 _pad_0xe8_0x200[70]; 112 }; 113 114 /* Clock speed accessors */ 115 unsigned long cm_get_mpu_clk_hz(void); 116 unsigned long cm_get_sdram_clk_hz(void); 117 unsigned int cm_get_l4_sp_clk_hz(void); 118 unsigned int cm_get_mmc_controller_clk_hz(void); 119 unsigned int cm_get_qspi_controller_clk_hz(void); 120 unsigned int cm_get_spi_controller_clk_hz(void); 121 const unsigned int cm_get_osc_clk_hz(const int osc); 122 const unsigned int cm_get_f2s_per_ref_clk_hz(void); 123 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); 124 125 /* Clock configuration accessors */ 126 int cm_basic_init(const struct cm_config * const cfg); 127 const struct cm_config * const cm_get_default_config(void); 128 #endif /* __ASSEMBLER__ */ 129 130 #define LOCKED_MASK \ 131 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ 132 CLKMGR_INTER_PERPLLLOCKED_MASK | \ 133 CLKMGR_INTER_MAINPLLLOCKED_MASK) 134 135 #define CLKMGR_CTRL_SAFEMODE BIT(0) 136 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0 137 138 #define CLKMGR_BYPASS_PERPLLSRC BIT(4) 139 #define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 140 #define CLKMGR_BYPASS_PERPLL BIT(3) 141 #define CLKMGR_BYPASS_PERPLL_OFFSET 3 142 #define CLKMGR_BYPASS_SDRPLLSRC BIT(2) 143 #define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 144 #define CLKMGR_BYPASS_SDRPLL BIT(1) 145 #define CLKMGR_BYPASS_SDRPLL_OFFSET 1 146 #define CLKMGR_BYPASS_MAINPLL BIT(0) 147 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0 148 149 #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(3) 150 #define CLKMGR_INTER_PERPLLLOST_MASK BIT(4) 151 #define CLKMGR_INTER_SDRPLLLOST_MASK BIT(5) 152 #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(6) 153 #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(7) 154 #define CLKMGR_INTER_SDRPLLLOCKED_MASK BIT(8) 155 156 #define CLKMGR_STAT_BUSY BIT(0) 157 158 /* Main PLL */ 159 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0) 160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 161 #define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 162 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 163 #define CLKMGR_MAINPLLGRP_VCO_EN BIT(1) 164 #define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 165 #define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 166 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 167 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 168 #define CLKMGR_MAINPLLGRP_VCO_PWRDN BIT(2) 169 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 170 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 171 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d 172 173 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 174 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff 175 176 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 177 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff 178 179 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 180 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff 181 182 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 183 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff 184 185 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 186 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff 187 188 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 189 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff 190 191 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2) 192 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK BIT(4) 193 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK BIT(5) 194 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK BIT(6) 195 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK BIT(7) 196 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(9) 197 198 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 199 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 200 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 201 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c 202 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 203 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 204 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 205 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 206 207 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 208 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 209 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 210 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c 211 212 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 213 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 214 215 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP BIT(0) 216 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 217 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP BIT(1) 218 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 219 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 220 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 221 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 222 223 /* Per PLL */ 224 #define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 225 #define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 226 #define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 227 #define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 228 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 229 #define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 230 #define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 231 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 232 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d 233 #define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 234 #define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 235 236 #define CLKMGR_VCO_SSRC_EOSC1 0x0 237 #define CLKMGR_VCO_SSRC_EOSC2 0x1 238 #define CLKMGR_VCO_SSRC_F2S 0x2 239 240 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 241 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff 242 243 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 244 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff 245 246 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 247 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff 248 249 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 250 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff 251 252 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 253 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff 254 255 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 256 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff 257 258 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 259 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 260 261 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 262 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 263 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 264 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 265 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 266 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 267 #define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 268 #define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 269 270 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 271 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff 272 273 #define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 274 #define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c 275 #define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 276 #define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 277 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 278 #define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 279 #define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 280 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 281 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 282 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2 283 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0 284 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 285 #define CLKMGR_QSPI_CLK_SRC_PER 0x2 286 287 /* SDR PLL */ 288 #define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 289 #define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 290 #define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 291 #define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 292 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL BIT(24) 293 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 294 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 295 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 296 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK BIT(31) 297 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d 298 #define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 299 #define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 300 301 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 302 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff 303 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 304 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 305 306 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 307 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff 308 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 309 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 310 311 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 312 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff 313 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 314 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 315 316 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 317 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff 318 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 319 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 320 321 #endif /* _CLOCK_MANAGER_GEN5_H_ */ 322