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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2005
4  * ARM Ltd.
5  * Peter Pearse, <Peter.Pearse@arm.com>
6  * Configuration for ARM Core Modules.
7  * No standalonw port yet available
8  * - this file is included by both integratorap.h & integratorcp.h
9  */
10 
11 #ifndef __ARMCOREMODULE_H
12 #define __ARMCOREMODULE_H
13 
14 #define CM_BASE			0x10000000
15 
16 /* CM registers common to all CMs */
17 /* Note that observed values after reboot into the ARM Boot Monitor
18    have been used as defaults, rather than the POR values */
19 #define OS_CTRL			0x0000000C
20 #define CMMASK_REMAP		0x00000005	/* set remap & led           */
21 #define CMMASK_RESET		0x00000008
22 #define OS_LOCK			0x00000014
23 #define CMVAL_LOCK1		0x0000A000	/* locking value             */
24 #define CMVAL_LOCK2		0x0000005F	/* locking value             */
25 #define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
26 #define OS_SDRAM		0x00000020
27 #define OS_INIT			0x00000024
28 #define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
29 #define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
30 #define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
31 #define CMMASK_LE		0xFFFFFFF7	/* little endian */
32 #define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
33 						/* - observed reset value of */
34 						/*   CM926EJ-S */
35 						/*   CM1136-EJ-S */
36 
37 #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
38 #define CMMASK_INIT_102	0x00000300		/* see CM102xx ref manual */
39 						/* - PLL test clock bypassed */
40 						/* - bus clock ratio 2 */
41 						/* - little endian */
42 						/* - vectors at zero */
43 #endif /* CM1022xx */
44 
45 /* Determine CM characteristics */
46 
47 #undef	CONFIG_CM_MULTIPLE_SSRAM
48 #undef	CONFIG_CM_SPD_DETECT
49 #undef	CONFIG_CM_REMAP
50 #undef	CONFIG_CM_INIT
51 #undef	CONFIG_CM_TCRAM
52 
53 #if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
54 #define	CONFIG_CM_MULTIPLE_SSRAM	/* CM has multiple SSRAM mapping */
55 #endif
56 
57 /* Excalibur core module has reduced functionality */
58 #ifndef	CONFIG_CM922T_XA10
59 #define CONFIG_CM_SPD_DETECT			/* CM supports SPD query      */
60 #define OS_SPD			0x00000100	/* Address of SPD data        */
61 #define CONFIG_CM_REMAP				/* CM supports remapping      */
62 #define CONFIG_CM_INIT				/* CM has initialization reg  */
63 #endif	/* NOT EXCALIBUR */
64 
65 #if defined(CONFIG_CM926EJ_S)   || defined (CONFIG_CM946E_S)	|| \
66     defined(CONFIG_CM966E_S)    || defined (CONFIG_CM1026EJ_S)	|| \
67     defined(CONFIG_CM1136JF_S)
68 #define CONFIG_CM_TCRAM				/* CM has TCRAM  */
69 #endif
70 
71 #ifdef CONFIG_CM_SPD_DETECT
72 #define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
73 #endif
74 
75 #endif /* __ARMCOREMODULE_H */
76