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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Renesas R7780MP board
4  *
5  * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6  * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
7  */
8 
9 #ifndef __R7780RP_H
10 #define __R7780RP_H
11 
12 #define CONFIG_CPU_SH7780	1
13 #define CONFIG_R7780MP		1
14 #define CONFIG_SYS_R7780MP_OLD_FLASH	1
15 #define __LITTLE_ENDIAN__ 1
16 
17 #define CONFIG_DISPLAY_BOARDINFO
18 
19 #define CONFIG_CONS_SCIF0	1
20 
21 #define CONFIG_ENV_OVERWRITE	1
22 
23 #define CONFIG_SYS_SDRAM_BASE		(0x08000000)
24 #define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
25 
26 #define CONFIG_SYS_PBSIZE		256
27 
28 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
29 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
30 
31 /* Flash board support */
32 #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
33 #ifdef CONFIG_SYS_R7780MP_OLD_FLASH
34 /* NOR Flash (S29PL127J60TFI130) */
35 # define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
36 # define CONFIG_SYS_MAX_FLASH_BANKS	(2)
37 # define CONFIG_SYS_MAX_FLASH_SECT	270
38 # define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
39 				CONFIG_SYS_FLASH_BASE + 0x100000,\
40 				CONFIG_SYS_FLASH_BASE + 0x400000,\
41 				CONFIG_SYS_FLASH_BASE + 0x700000, }
42 #else /* CONFIG_SYS_R7780MP_OLD_FLASH */
43 /* NOR Flash (Spantion S29GL256P) */
44 # define CONFIG_SYS_MAX_FLASH_BANKS	(1)
45 # define CONFIG_SYS_MAX_FLASH_SECT		256
46 # define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
47 #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
48 
49 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
50 /* Address of u-boot image in Flash */
51 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
52 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
53 /* Size of DRAM reserved for malloc() use */
54 #define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
55 
56 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
57 #define CONFIG_SYS_RX_ETH_BUFFER	(8)
58 
59 #define CONFIG_SYS_FLASH_CFI
60 #define CONFIG_FLASH_CFI_DRIVER
61 #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
62 #undef  CONFIG_SYS_FLASH_QUIET_TEST
63 /* print 'E' for empty sector on flinfo */
64 #define CONFIG_SYS_FLASH_EMPTY_INFO
65 
66 #define CONFIG_ENV_SECT_SIZE	(256 * 1024)
67 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
68 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
69 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000
70 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
71 
72 /* Board Clock */
73 #define CONFIG_SYS_CLK_FREQ	33333333
74 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
75 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
76 #define CONFIG_SYS_TMU_CLK_DIV		4
77 
78 /* PCI Controller */
79 #if defined(CONFIG_CMD_PCI)
80 #define CONFIG_SH4_PCI
81 #define CONFIG_SH7780_PCI
82 #define CONFIG_SH7780_PCI_LSR	0x07f00001
83 #define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
84 #define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
85 #define CONFIG_PCI_SCAN_SHOW	1
86 #define __mem_pci
87 
88 #define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
89 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
90 #define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
91 
92 #define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
93 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
94 #define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
95 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
96 #define CONFIG_PCI_SYS_BUS  CONFIG_SYS_SDRAM_BASE
97 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
98 #endif /* CONFIG_CMD_PCI */
99 
100 #if defined(CONFIG_CMD_NET)
101 /* AX88796L Support(NE2000 base chip) */
102 #define CONFIG_DRIVER_AX88796L
103 #define CONFIG_DRIVER_NE2000_BASE	0xA4100000
104 #endif
105 
106 /* Compact flash Support */
107 #if defined(CONFIG_IDE)
108 #define CONFIG_IDE_RESET        1
109 #define CONFIG_SYS_PIO_MODE            1
110 #define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
111 #define CONFIG_SYS_IDE_MAXDEVICE       1
112 #define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
113 #define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
114 #define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
115 #define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
116 #define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
117 #define CONFIG_IDE_SWAP_IO
118 #endif /* CONFIG_IDE */
119 
120 #endif /* __R7780RP_H */
121