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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
8 
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
10 
11 /*
12  * This macro should be removed when we no longer care about backwards
13  * compatibility with older operating systems.
14  */
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
16 
17 #include <fsl_ddrc_version.h>
18 
19 /* IP endianness */
20 #define CONFIG_SYS_FSL_IFC_BE
21 #define CONFIG_SYS_FSL_SFP_BE
22 #define CONFIG_SYS_FSL_SEC_MON_BE
23 
24 #if defined(CONFIG_ARCH_MPC8548)
25 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
26 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
27 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
28 #define CONFIG_SYS_FSL_RMU
29 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
30 
31 #elif defined(CONFIG_ARCH_MPC8568)
32 #define QE_MURAM_SIZE			0x10000UL
33 #define MAX_QE_RISC			2
34 #define QE_NUM_OF_SNUM			28
35 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
36 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
37 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
38 #define CONFIG_SYS_FSL_RMU
39 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
40 
41 #elif defined(CONFIG_ARCH_MPC8569)
42 #define QE_MURAM_SIZE			0x20000UL
43 #define MAX_QE_RISC			4
44 #define QE_NUM_OF_SNUM			46
45 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
46 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
47 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
48 #define CONFIG_SYS_FSL_RMU
49 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
50 
51 #elif defined(CONFIG_ARCH_P1010)
52 #define CONFIG_FSL_SDHC_V2_3
53 #define CONFIG_TSECV2
54 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
55 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
56 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
57 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
58 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
59 #define CONFIG_ESDHC_HC_BLK_ADDR
60 
61 /* P1011 is single core version of P1020 */
62 #elif defined(CONFIG_ARCH_P1011)
63 #define CONFIG_TSECV2
64 #define CONFIG_FSL_PCIE_DISABLE_ASPM
65 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
66 
67 #elif defined(CONFIG_ARCH_P1020)
68 #define CONFIG_TSECV2
69 #define CONFIG_FSL_PCIE_DISABLE_ASPM
70 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
71 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
72 #endif
73 
74 #elif defined(CONFIG_ARCH_P1021)
75 #define CONFIG_TSECV2
76 #define CONFIG_FSL_PCIE_DISABLE_ASPM
77 #define QE_MURAM_SIZE			0x6000UL
78 #define MAX_QE_RISC			1
79 #define QE_NUM_OF_SNUM			28
80 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
81 
82 #elif defined(CONFIG_ARCH_P1022)
83 #define CONFIG_TSECV2
84 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
85 
86 #elif defined(CONFIG_ARCH_P1023)
87 #define CONFIG_SYS_NUM_FMAN		1
88 #define CONFIG_SYS_NUM_FM1_DTSEC	2
89 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
90 #define CONFIG_SYS_QMAN_NUM_PORTALS	3
91 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
92 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
93 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
94 
95 /* P1024 is lower end variant of P1020 */
96 #elif defined(CONFIG_ARCH_P1024)
97 #define CONFIG_TSECV2
98 #define CONFIG_FSL_PCIE_DISABLE_ASPM
99 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
100 
101 /* P1025 is lower end variant of P1021 */
102 #elif defined(CONFIG_ARCH_P1025)
103 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
104 #define CONFIG_TSECV2
105 #define CONFIG_FSL_PCIE_DISABLE_ASPM
106 #define QE_MURAM_SIZE			0x6000UL
107 #define MAX_QE_RISC			1
108 #define QE_NUM_OF_SNUM			28
109 
110 #elif defined(CONFIG_ARCH_P2020)
111 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
112 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
113 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
114 #define CONFIG_SYS_FSL_RMU
115 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
116 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
117 
118 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
119 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
120 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
121 #define CONFIG_SYS_NUM_FMAN		1
122 #define CONFIG_SYS_NUM_FM1_DTSEC	5
123 #define CONFIG_SYS_NUM_FM1_10GEC	1
124 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
125 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
126 #define CONFIG_SYS_FSL_TBCLK_DIV	32
127 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
128 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
129 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
130 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
131 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
132 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
133 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
134 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
135 
136 #elif defined(CONFIG_ARCH_P3041)
137 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
138 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
139 #define CONFIG_SYS_NUM_FMAN		1
140 #define CONFIG_SYS_NUM_FM1_DTSEC	5
141 #define CONFIG_SYS_NUM_FM1_10GEC	1
142 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
143 #define CONFIG_SYS_FSL_TBCLK_DIV	32
144 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
145 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
146 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
147 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
148 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
149 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
150 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
151 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
152 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
153 
154 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
155 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
156 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
157 #define CONFIG_SYS_NUM_FMAN		2
158 #define CONFIG_SYS_NUM_FM1_DTSEC	4
159 #define CONFIG_SYS_NUM_FM2_DTSEC	4
160 #define CONFIG_SYS_NUM_FM1_10GEC	1
161 #define CONFIG_SYS_NUM_FM2_10GEC	1
162 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
163 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
164 #define CONFIG_SYS_FSL_TBCLK_DIV	16
165 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
166 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
167 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
168 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
169 #define CONFIG_SYS_FSL_RMU
170 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
171 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
172 
173 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
174 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
175 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
176 #define CONFIG_SYS_NUM_FMAN		1
177 #define CONFIG_SYS_NUM_FM1_DTSEC	5
178 #define CONFIG_SYS_NUM_FM1_10GEC	1
179 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
180 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
181 #define CONFIG_SYS_FSL_TBCLK_DIV	32
182 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
183 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
184 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
185 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
186 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
187 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
188 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
189 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
190 
191 #elif defined(CONFIG_ARCH_P5040)
192 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
193 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
194 #define CONFIG_SYS_NUM_FMAN		2
195 #define CONFIG_SYS_NUM_FM1_DTSEC	5
196 #define CONFIG_SYS_NUM_FM1_10GEC	1
197 #define CONFIG_SYS_NUM_FM2_DTSEC	5
198 #define CONFIG_SYS_NUM_FM2_10GEC	1
199 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
200 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
201 #define CONFIG_SYS_FSL_TBCLK_DIV	16
202 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
203 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
204 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
205 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
206 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
207 
208 #elif defined(CONFIG_ARCH_BSC9131)
209 #define CONFIG_FSL_SDHC_V2_3
210 #define CONFIG_TSECV2
211 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
212 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
213 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
214 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
215 #define CONFIG_NAND_FSL_IFC
216 #define CONFIG_ESDHC_HC_BLK_ADDR
217 
218 #elif defined(CONFIG_ARCH_BSC9132)
219 #define CONFIG_FSL_SDHC_V2_3
220 #define CONFIG_TSECV2
221 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
222 #define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
223 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
224 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
225 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
226 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
227 #define CONFIG_NAND_FSL_IFC
228 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
229 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
230 #define CONFIG_ESDHC_HC_BLK_ADDR
231 
232 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
233 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
234 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
235 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
236 #ifdef CONFIG_ARCH_T4240
237 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
238 #define CONFIG_SYS_NUM_FM1_DTSEC	8
239 #define CONFIG_SYS_NUM_FM1_10GEC	2
240 #define CONFIG_SYS_NUM_FM2_DTSEC	8
241 #define CONFIG_SYS_NUM_FM2_10GEC	2
242 #else
243 #define CONFIG_SYS_NUM_FM1_DTSEC	6
244 #define CONFIG_SYS_NUM_FM1_10GEC	1
245 #define CONFIG_SYS_NUM_FM2_DTSEC	8
246 #define CONFIG_SYS_NUM_FM2_10GEC	1
247 #if defined(CONFIG_ARCH_T4160)
248 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 1 }
249 #endif
250 #endif
251 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
252 #define CONFIG_SYS_FSL_SRDS_1
253 #define CONFIG_SYS_FSL_SRDS_2
254 #define CONFIG_SYS_FSL_SRDS_3
255 #define CONFIG_SYS_FSL_SRDS_4
256 #define CONFIG_SYS_NUM_FMAN		2
257 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
258 #define CONFIG_SYS_PME_CLK		0
259 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
260 #define CONFIG_SYS_FMAN_V3
261 #define CONFIG_SYS_FM1_CLK		3
262 #define CONFIG_SYS_FM2_CLK		3
263 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
264 #define CONFIG_SYS_FSL_TBCLK_DIV	16
265 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
266 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
267 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
268 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
269 #define CONFIG_SYS_FSL_SRIO_LIODN
270 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
271 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
272 #define CONFIG_SYS_FSL_SFP_VER_3_0
273 #define CONFIG_SYS_FSL_PCI_VER_3_X
274 
275 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
276 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
277 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
278 #define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
279 #define CONFIG_PPC_CLUSTER_START	0 /*Start index of ppc clusters*/
280 #define CONFIG_DSP_CLUSTER_START	1 /*Start index of dsp clusters*/
281 #define CONFIG_SYS_FSL_SRDS_1
282 #define CONFIG_SYS_FSL_SRDS_2
283 #define CONFIG_SYS_MAPLE
284 #define CONFIG_SYS_CPRI
285 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
286 #define CONFIG_SYS_NUM_FMAN		1
287 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
288 #define CONFIG_SYS_FM1_CLK		0
289 #define CONFIG_SYS_CPRI_CLK		3
290 #define CONFIG_SYS_ULB_CLK		4
291 #define CONFIG_SYS_ETVPE_CLK		1
292 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
293 #define CONFIG_SYS_FMAN_V3
294 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
295 #define CONFIG_SYS_FSL_TBCLK_DIV	16
296 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
297 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
298 #define CONFIG_SYS_FSL_SFP_VER_3_0
299 
300 #ifdef CONFIG_ARCH_B4860
301 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
302 #define CONFIG_MAX_DSP_CPUS		12
303 #define CONFIG_NUM_DSP_CPUS		6
304 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS	2
305 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
306 #define CONFIG_SYS_NUM_FM1_DTSEC	6
307 #define CONFIG_SYS_NUM_FM1_10GEC	2
308 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
309 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
310 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
311 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
312 #define CONFIG_SYS_FSL_SRIO_LIODN
313 #else
314 #define CONFIG_MAX_DSP_CPUS		2
315 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS	1
316 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
317 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
318 #define CONFIG_SYS_NUM_FM1_DTSEC	4
319 #define CONFIG_SYS_NUM_FM1_10GEC	0
320 #endif
321 
322 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
323 #define CONFIG_E5500
324 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
325 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
326 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
327 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
328 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
329 #define CONFIG_SYS_FSL_SRDS_1
330 #define CONFIG_SYS_NUM_FMAN		1
331 #define CONFIG_SYS_NUM_FM1_DTSEC	5
332 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
333 #define CONFIG_PME_PLAT_CLK_DIV		2
334 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
335 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
336 #define CONFIG_SYS_FMAN_V3
337 #define CONFIG_FM_PLAT_CLK_DIV	1
338 #define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
339 #define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
340 					    per rcw field value */
341 #define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
342 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
343 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
344 #define CONFIG_SYS_FSL_TBCLK_DIV	16
345 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
346 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
347 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
348 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
349 #define QE_MURAM_SIZE			0x6000UL
350 #define MAX_QE_RISC			1
351 #define QE_NUM_OF_SNUM			28
352 #define CONFIG_SYS_FSL_SFP_VER_3_0
353 
354 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
355 #define CONFIG_E5500
356 #define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
357 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
358 #define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
359 #define CONFIG_SYS_FMAN_V3
360 #define CONFIG_SYS_FSL_NUM_CC_PLL	2
361 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
362 #define CONFIG_SYS_FSL_SRDS_1
363 #define CONFIG_SYS_NUM_FMAN		1
364 #define CONFIG_SYS_NUM_FM1_DTSEC	4
365 #define CONFIG_SYS_NUM_FM1_10GEC	1
366 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
367 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
368 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
369 #define CONFIG_SYS_FM1_CLK		0
370 #define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
371 					    per rcw field value */
372 #define CONFIG_QBMAN_CLK_DIV		1
373 #define CONFIG_SYS_FM_MURAM_SIZE	0x30000
374 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
375 #define CONFIG_SYS_FSL_TBCLK_DIV	16
376 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
377 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
378 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
380 #define QE_MURAM_SIZE			0x6000UL
381 #define MAX_QE_RISC			1
382 #define QE_NUM_OF_SNUM			28
383 #define CONFIG_SYS_FSL_SFP_VER_3_0
384 
385 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
386 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
387 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
388 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
389 #define CONFIG_SYS_FSL_QMAN_V3
390 #define CONFIG_SYS_NUM_FMAN		1
391 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
392 #define CONFIG_SYS_FSL_SRDS_1
393 #define CONFIG_SYS_FSL_PCI_VER_3_X
394 #if defined(CONFIG_ARCH_T2080)
395 #define CONFIG_SYS_NUM_FM1_DTSEC	8
396 #define CONFIG_SYS_NUM_FM1_10GEC	4
397 #define CONFIG_SYS_FSL_SRDS_2
398 #define CONFIG_SYS_FSL_SRIO_LIODN
399 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
400 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
401 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
402 #elif defined(CONFIG_ARCH_T2081)
403 #define CONFIG_SYS_NUM_FM1_DTSEC	6
404 #define CONFIG_SYS_NUM_FM1_10GEC	2
405 #endif
406 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
407 #define CONFIG_PME_PLAT_CLK_DIV		1
408 #define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
409 #define CONFIG_SYS_FM1_CLK		0
410 #define CONFIG_SYS_SDHC_CLK		1/* Select SDHC CLK begining from PLL2
411 					    per rcw field value */
412 #define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
413 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
414 #define CONFIG_SYS_FMAN_V3
415 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
416 #define CONFIG_SYS_FSL_TBCLK_DIV	16
417 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
418 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
419 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
420 #define CONFIG_SYS_FSL_SFP_VER_3_0
421 #define CONFIG_SYS_FSL_ISBC_VER		2
422 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
423 #define CONFIG_SYS_FSL_SFP_VER_3_0
424 
425 
426 #elif defined(CONFIG_ARCH_C29X)
427 #define CONFIG_FSL_SDHC_V2_3
428 #define CONFIG_TSECV2_1
429 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
430 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
431 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
432 
433 #endif
434 
435 #if !defined(CONFIG_ARCH_C29X)
436 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
437 #endif
438 
439 #endif /* _ASM_MPC85xx_CONFIG_H_ */
440