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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * ColdFire Internal Memory Map and Defines
4  *
5  * Copyright 2004-2012 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8 
9 #ifndef __IMMAP_H
10 #define __IMMAP_H
11 
12 #if defined(CONFIG_MCF520x)
13 #include <asm/immap_520x.h>
14 #include <asm/m520x.h>
15 
16 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
17 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
18 
19 /* Timer */
20 #ifdef CONFIG_MCFTMR
21 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
22 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
23 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
24 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
25 #define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
26 #define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
27 #define CONFIG_SYS_TMRINTR_PRI		(6)
28 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
29 #endif
30 
31 #ifdef CONFIG_MCFPIT
32 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
33 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
34 #define CONFIG_SYS_PIT_PRESCALE	(6)
35 #endif
36 
37 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
38 #define CONFIG_SYS_NUM_IRQS		(128)
39 #endif				/* CONFIG_M520x */
40 
41 #ifdef CONFIG_M52277
42 #include <asm/immap_5227x.h>
43 #include <asm/m5227x.h>
44 
45 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
46 
47 #define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
48 
49 #ifdef CONFIG_LCD
50 #define	CONFIG_SYS_LCD_BASE		(MMAP_LCD)
51 #endif
52 
53 /* Timer */
54 #ifdef CONFIG_MCFTMR
55 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
56 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
57 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
58 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
59 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
60 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
61 #define CONFIG_SYS_TMRINTR_PRI		(6)
62 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
63 #endif
64 
65 #ifdef CONFIG_MCFPIT
66 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
67 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
68 #define CONFIG_SYS_PIT_PRESCALE	(6)
69 #endif
70 
71 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
72 #define CONFIG_SYS_NUM_IRQS		(128)
73 #endif				/* CONFIG_M52277 */
74 
75 #ifdef CONFIG_M5235
76 #include <asm/immap_5235.h>
77 #include <asm/m5235.h>
78 
79 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
80 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
81 
82 /* Timer */
83 #ifdef CONFIG_MCFTMR
84 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
85 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
86 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
87 #define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
88 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
89 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
90 #define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
91 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
92 #endif
93 
94 #ifdef CONFIG_MCFPIT
95 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
96 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
97 #define CONFIG_SYS_PIT_PRESCALE	(6)
98 #endif
99 
100 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
101 #define CONFIG_SYS_NUM_IRQS		(128)
102 #endif				/* CONFIG_M5235 */
103 
104 #ifdef CONFIG_M5249
105 #include <asm/immap_5249.h>
106 #include <asm/m5249.h>
107 
108 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
109 
110 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
111 #define CONFIG_SYS_NUM_IRQS		(64)
112 
113 /* Timer */
114 #ifdef CONFIG_MCFTMR
115 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
116 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
117 #define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
118 #define CONFIG_SYS_TMRINTR_NO		(31)
119 #define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
120 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
121 #define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
122 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
123 #endif
124 #endif				/* CONFIG_M5249 */
125 
126 #ifdef CONFIG_M5253
127 #include <asm/immap_5253.h>
128 #include <asm/m5249.h>
129 #include <asm/m5253.h>
130 
131 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
132 
133 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
134 #define CONFIG_SYS_NUM_IRQS		(64)
135 
136 /* Timer */
137 #ifdef CONFIG_MCFTMR
138 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
139 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
140 #define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
141 #define CONFIG_SYS_TMRINTR_NO		(27)
142 #define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
143 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
144 #define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
145 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
146 #endif
147 #endif				/* CONFIG_M5253 */
148 
149 #ifdef CONFIG_M5271
150 #include <asm/immap_5271.h>
151 #include <asm/m5271.h>
152 
153 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
154 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
155 
156 /* Timer */
157 #ifdef CONFIG_MCFTMR
158 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
159 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
160 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
161 #define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
162 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
163 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
164 #define CONFIG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
165 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
166 #endif
167 
168 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
169 #define CONFIG_SYS_NUM_IRQS		(128)
170 #endif				/* CONFIG_M5271 */
171 
172 #ifdef CONFIG_M5272
173 #include <asm/immap_5272.h>
174 #include <asm/m5272.h>
175 
176 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
177 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
178 
179 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
180 #define CONFIG_SYS_NUM_IRQS		(64)
181 
182 /* Timer */
183 #ifdef CONFIG_MCFTMR
184 #define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
185 #define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
186 #define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
187 #define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
188 #define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
189 #define CONFIG_SYS_TMRINTR_PEND	(0)
190 #define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
191 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
192 #endif
193 #endif				/* CONFIG_M5272 */
194 
195 #ifdef CONFIG_M5275
196 #include <asm/immap_5275.h>
197 #include <asm/m5275.h>
198 
199 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
200 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
201 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
202 
203 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
204 #define CONFIG_SYS_NUM_IRQS		(192)
205 
206 /* Timer */
207 #ifdef CONFIG_MCFTMR
208 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
209 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
210 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
211 #define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
212 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
213 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
214 #define CONFIG_SYS_TMRINTR_PRI		(0x1E)
215 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
216 #endif
217 #endif				/* CONFIG_M5275 */
218 
219 #ifdef CONFIG_M5282
220 #include <asm/immap_5282.h>
221 #include <asm/m5282.h>
222 
223 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
224 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
225 
226 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
227 #define CONFIG_SYS_NUM_IRQS		(128)
228 
229 /* Timer */
230 #ifdef CONFIG_MCFTMR
231 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
232 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
233 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
234 #define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
235 #define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
236 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
237 #define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
238 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
239 #endif
240 #endif				/* CONFIG_M5282 */
241 
242 #ifdef CONFIG_M5307
243 #include <asm/immap_5307.h>
244 #include <asm/m5307.h>
245 
246 #define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
247 					(CONFIG_SYS_UART_PORT * 0x40))
248 #define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
249 #define CONFIG_SYS_NUM_IRQS             (64)
250 
251 /* Timer */
252 #ifdef CONFIG_MCFTMR
253 #define CONFIG_SYS_UDELAY_BASE          (MMAP_DTMR0)
254 #define CONFIG_SYS_TMR_BASE             (MMAP_DTMR1)
255 #define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
256 					(CONFIG_SYS_INTR_BASE))->ipr)
257 #define CONFIG_SYS_TMRINTR_NO           (31)
258 #define CONFIG_SYS_TMRINTR_MASK		(0x00000400)
259 #define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
260 #define CONFIG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
261 					MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
262 #define CONFIG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
263 #endif
264 #endif                          /* CONFIG_M5307 */
265 
266 #if defined(CONFIG_MCF5301x)
267 #include <asm/immap_5301x.h>
268 #include <asm/m5301x.h>
269 
270 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
271 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
272 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
273 
274 #define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
275 
276 /* Timer */
277 #ifdef CONFIG_MCFTMR
278 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
279 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
280 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
281 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
282 #define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
283 #define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
284 #define CONFIG_SYS_TMRINTR_PRI		(6)
285 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
286 #endif
287 
288 #ifdef CONFIG_MCFPIT
289 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
290 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
291 #define CONFIG_SYS_PIT_PRESCALE	(6)
292 #endif
293 
294 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
295 #define CONFIG_SYS_NUM_IRQS		(128)
296 #endif				/* CONFIG_M5301x */
297 
298 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
299 #include <asm/immap_5329.h>
300 #include <asm/m5329.h>
301 
302 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
303 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
304 #define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
305 
306 /* Timer */
307 #ifdef CONFIG_MCFTMR
308 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
309 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
310 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
311 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
312 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
313 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
314 #define CONFIG_SYS_TMRINTR_PRI		(6)
315 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
316 #endif
317 
318 #ifdef CONFIG_MCFPIT
319 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
320 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
321 #define CONFIG_SYS_PIT_PRESCALE	(6)
322 #endif
323 
324 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
325 #define CONFIG_SYS_NUM_IRQS		(128)
326 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
327 
328 #if defined(CONFIG_M54418)
329 #include <asm/immap_5441x.h>
330 #include <asm/m5441x.h>
331 
332 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
333 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
334 
335 #if (CONFIG_SYS_UART_PORT < 4)
336 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
337 					(CONFIG_SYS_UART_PORT * 0x4000))
338 #else
339 #define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
340 					((CONFIG_SYS_UART_PORT - 4) * 0x4000))
341 #endif
342 
343 #define MMAP_DSPI			MMAP_DSPI0
344 #define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
345 
346 /* Timer */
347 #ifdef CONFIG_MCFTMR
348 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
349 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
350 #define CONFIG_SYS_TMRPND_REG	(((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
351 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
352 #define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
353 #define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
354 #define CONFIG_SYS_TMRINTR_PRI		(6)
355 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
356 #endif
357 
358 #ifdef CONFIG_MCFPIT
359 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
360 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
361 #define CONFIG_SYS_PIT_PRESCALE	(6)
362 #endif
363 
364 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
365 #define CONFIG_SYS_NUM_IRQS		(128)
366 
367 #endif				/* CONFIG_M54418 */
368 
369 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
370 #include <asm/immap_5445x.h>
371 #include <asm/m5445x.h>
372 
373 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
374 #if defined(CONFIG_M54455EVB)
375 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
376 #endif
377 
378 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
379 
380 #define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
381 
382 /* Timer */
383 #ifdef CONFIG_MCFTMR
384 #define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
385 #define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
386 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
387 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
388 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
389 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
390 #define CONFIG_SYS_TMRINTR_PRI		(6)
391 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
392 #endif
393 
394 #ifdef CONFIG_MCFPIT
395 #define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
396 #define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
397 #define CONFIG_SYS_PIT_PRESCALE	(6)
398 #endif
399 
400 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
401 #define CONFIG_SYS_NUM_IRQS		(128)
402 
403 #ifdef CONFIG_PCI
404 #define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
405 #define CONFIG_SYS_PCI_BAR5		(CONFIG_SYS_SDRAM_BASE)
406 #define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
407 #define CONFIG_SYS_PCI_TBATR5		(CONFIG_SYS_SDRAM_BASE)
408 #endif
409 #endif				/* CONFIG_M54451 || CONFIG_M54455 */
410 
411 #ifdef CONFIG_M547x
412 #include <asm/immap_547x_8x.h>
413 #include <asm/m547x_8x.h>
414 
415 #ifdef CONFIG_FSLDMAFEC
416 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
417 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
418 
419 #define FEC0_RX_TASK		0
420 #define FEC0_TX_TASK		1
421 #define FEC0_RX_PRIORITY	6
422 #define FEC0_TX_PRIORITY	7
423 #define FEC0_RX_INIT		16
424 #define FEC0_TX_INIT		17
425 #define FEC1_RX_TASK		2
426 #define FEC1_TX_TASK		3
427 #define FEC1_RX_PRIORITY	6
428 #define FEC1_TX_PRIORITY	7
429 #define FEC1_RX_INIT		30
430 #define FEC1_TX_INIT		31
431 #endif
432 
433 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
434 
435 #ifdef CONFIG_SLTTMR
436 #define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
437 #define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
438 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
439 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
440 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
441 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
442 #define CONFIG_SYS_TMRINTR_PRI		(0x1E)
443 #define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
444 #endif
445 
446 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
447 #define CONFIG_SYS_NUM_IRQS		(128)
448 
449 #ifdef CONFIG_PCI
450 #define CONFIG_SYS_PCI_BAR0		(0x40000000)
451 #define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
452 #define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
453 #define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
454 #endif
455 #endif				/* CONFIG_M547x */
456 
457 #ifdef CONFIG_M548x
458 #include <asm/immap_547x_8x.h>
459 #include <asm/m547x_8x.h>
460 
461 #ifdef CONFIG_FSLDMAFEC
462 #define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
463 #define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
464 
465 #define FEC0_RX_TASK		0
466 #define FEC0_TX_TASK		1
467 #define FEC0_RX_PRIORITY	6
468 #define FEC0_TX_PRIORITY	7
469 #define FEC0_RX_INIT		16
470 #define FEC0_TX_INIT		17
471 #define FEC1_RX_TASK		2
472 #define FEC1_TX_TASK		3
473 #define FEC1_RX_PRIORITY	6
474 #define FEC1_TX_PRIORITY	7
475 #define FEC1_RX_INIT		30
476 #define FEC1_TX_INIT		31
477 #endif
478 
479 #define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
480 
481 /* Timer */
482 #ifdef CONFIG_SLTTMR
483 #define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
484 #define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
485 #define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
486 #define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
487 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
488 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
489 #define CONFIG_SYS_TMRINTR_PRI		(0x1E)
490 #define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
491 #endif
492 
493 #define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
494 #define CONFIG_SYS_NUM_IRQS		(128)
495 
496 #ifdef CONFIG_PCI
497 #define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
498 #define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
499 #define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
500 #define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
501 #endif
502 #endif				/* CONFIG_M548x */
503 
504 #endif				/* __IMMAP_H */
505