1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
4 *
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
10 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
11 *
12 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
13 */
14
15 #define CONFIG_USB_PXA25X_SMALL
16 #define DRIVER_NAME "pxa25x_udc_linux"
17 #define ARCH_HAS_PREFETCH
18
19 #include <common.h>
20 #include <errno.h>
21 #include <asm/byteorder.h>
22 #include <asm/system.h>
23 #include <asm/mach-types.h>
24 #include <asm/unaligned.h>
25 #include <linux/compat.h>
26 #include <malloc.h>
27 #include <asm/io.h>
28 #include <asm/arch/pxa.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <usb/lin_gadget_compat.h>
33 #include <asm/arch/pxa-regs.h>
34
35 #include "pxa25x_udc.h"
36
37 /*
38 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
39 * series processors. The UDC for the IXP 4xx series is very similar.
40 * There are fifteen endpoints, in addition to ep0.
41 *
42 * Such controller drivers work with a gadget driver. The gadget driver
43 * returns descriptors, implements configuration and data protocols used
44 * by the host to interact with this device, and allocates endpoints to
45 * the different protocol interfaces. The controller driver virtualizes
46 * usb hardware so that the gadget drivers will be more portable.
47 *
48 * This UDC hardware wants to implement a bit too much USB protocol, so
49 * it constrains the sorts of USB configuration change events that work.
50 * The errata for these chips are misleading; some "fixed" bugs from
51 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
52 *
53 * Note that the UDC hardware supports DMA (except on IXP) but that's
54 * not used here. IN-DMA (to host) is simple enough, when the data is
55 * suitably aligned (16 bytes) ... the network stack doesn't do that,
56 * other software can. OUT-DMA is buggy in most chip versions, as well
57 * as poorly designed (data toggle not automatic). So this driver won't
58 * bother using DMA. (Mostly-working IN-DMA support was available in
59 * kernels before 2.6.23, but was never enabled or well tested.)
60 */
61
62 #define DRIVER_VERSION "18-August-2012"
63 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
64
65 static const char driver_name[] = "pxa25x_udc";
66 static const char ep0name[] = "ep0";
67
68 /* Watchdog */
start_watchdog(struct pxa25x_udc * udc)69 static inline void start_watchdog(struct pxa25x_udc *udc)
70 {
71 debug("Started watchdog\n");
72 udc->watchdog.base = get_timer(0);
73 udc->watchdog.running = 1;
74 }
75
stop_watchdog(struct pxa25x_udc * udc)76 static inline void stop_watchdog(struct pxa25x_udc *udc)
77 {
78 udc->watchdog.running = 0;
79 debug("Stopped watchdog\n");
80 }
81
test_watchdog(struct pxa25x_udc * udc)82 static inline void test_watchdog(struct pxa25x_udc *udc)
83 {
84 if (!udc->watchdog.running)
85 return;
86
87 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
88 udc->watchdog.period);
89
90 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
91 stop_watchdog(udc);
92 udc->watchdog.function(udc);
93 }
94 }
95
udc_watchdog(struct pxa25x_udc * dev)96 static void udc_watchdog(struct pxa25x_udc *dev)
97 {
98 uint32_t udccs0 = readl(&dev->regs->udccs[0]);
99
100 debug("Fired up udc_watchdog\n");
101
102 local_irq_disable();
103 if (dev->ep0state == EP0_STALL
104 && (udccs0 & UDCCS0_FST) == 0
105 && (udccs0 & UDCCS0_SST) == 0) {
106 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
107 debug("ep0 re-stall\n");
108 start_watchdog(dev);
109 }
110 local_irq_enable();
111 }
112
113 #ifdef DEBUG
114
115 static const char * const state_name[] = {
116 "EP0_IDLE",
117 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
118 "EP0_END_XFER", "EP0_STALL"
119 };
120
121 static void
dump_udccr(const char * label)122 dump_udccr(const char *label)
123 {
124 u32 udccr = readl(&UDC_REGS->udccr);
125 debug("%s %02X =%s%s%s%s%s%s%s%s\n",
126 label, udccr,
127 (udccr & UDCCR_REM) ? " rem" : "",
128 (udccr & UDCCR_RSTIR) ? " rstir" : "",
129 (udccr & UDCCR_SRM) ? " srm" : "",
130 (udccr & UDCCR_SUSIR) ? " susir" : "",
131 (udccr & UDCCR_RESIR) ? " resir" : "",
132 (udccr & UDCCR_RSM) ? " rsm" : "",
133 (udccr & UDCCR_UDA) ? " uda" : "",
134 (udccr & UDCCR_UDE) ? " ude" : "");
135 }
136
137 static void
dump_udccs0(const char * label)138 dump_udccs0(const char *label)
139 {
140 u32 udccs0 = readl(&UDC_REGS->udccs[0]);
141
142 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
143 label, state_name[the_controller->ep0state], udccs0,
144 (udccs0 & UDCCS0_SA) ? " sa" : "",
145 (udccs0 & UDCCS0_RNE) ? " rne" : "",
146 (udccs0 & UDCCS0_FST) ? " fst" : "",
147 (udccs0 & UDCCS0_SST) ? " sst" : "",
148 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
149 (udccs0 & UDCCS0_FTF) ? " ftf" : "",
150 (udccs0 & UDCCS0_IPR) ? " ipr" : "",
151 (udccs0 & UDCCS0_OPR) ? " opr" : "");
152 }
153
154 static void
dump_state(struct pxa25x_udc * dev)155 dump_state(struct pxa25x_udc *dev)
156 {
157 u32 tmp;
158 unsigned i;
159
160 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
161 state_name[dev->ep0state],
162 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
163 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
164 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
165 dump_udccr("udccr");
166 if (dev->has_cfr) {
167 tmp = readl(&UDC_REGS->udccfr);
168 debug("udccfr %02X =%s%s\n", tmp,
169 (tmp & UDCCFR_AREN) ? " aren" : "",
170 (tmp & UDCCFR_ACM) ? " acm" : "");
171 }
172
173 if (!dev->driver) {
174 debug("no gadget driver bound\n");
175 return;
176 } else
177 debug("ep0 driver '%s'\n", "ether");
178
179 dump_udccs0("udccs0");
180 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
181 dev->stats.write.bytes, dev->stats.write.ops,
182 dev->stats.read.bytes, dev->stats.read.ops);
183
184 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
185 if (dev->ep[i].desc == NULL)
186 continue;
187 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
188 }
189 }
190
191 #else /* DEBUG */
192
dump_udccr(const char * label)193 static inline void dump_udccr(const char *label) { }
dump_udccs0(const char * label)194 static inline void dump_udccs0(const char *label) { }
dump_state(struct pxa25x_udc * dev)195 static inline void dump_state(struct pxa25x_udc *dev) { }
196
197 #endif /* DEBUG */
198
199 /*
200 * ---------------------------------------------------------------------------
201 * endpoint related parts of the api to the usb controller hardware,
202 * used by gadget driver; and the inner talker-to-hardware core.
203 * ---------------------------------------------------------------------------
204 */
205
206 static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
207 static void nuke(struct pxa25x_ep *, int status);
208
209 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
pullup_off(void)210 static void pullup_off(void)
211 {
212 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
213
214 if (mach->udc_command)
215 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
216 }
217
pullup_on(void)218 static void pullup_on(void)
219 {
220 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
221
222 if (mach->udc_command)
223 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
224 }
225
pio_irq_enable(int bEndpointAddress)226 static void pio_irq_enable(int bEndpointAddress)
227 {
228 bEndpointAddress &= 0xf;
229 if (bEndpointAddress < 8) {
230 clrbits_le32(&the_controller->regs->uicr0,
231 1 << bEndpointAddress);
232 } else {
233 bEndpointAddress -= 8;
234 clrbits_le32(&the_controller->regs->uicr1,
235 1 << bEndpointAddress);
236 }
237 }
238
pio_irq_disable(int bEndpointAddress)239 static void pio_irq_disable(int bEndpointAddress)
240 {
241 bEndpointAddress &= 0xf;
242 if (bEndpointAddress < 8) {
243 setbits_le32(&the_controller->regs->uicr0,
244 1 << bEndpointAddress);
245 } else {
246 bEndpointAddress -= 8;
247 setbits_le32(&the_controller->regs->uicr1,
248 1 << bEndpointAddress);
249 }
250 }
251
udc_set_mask_UDCCR(int mask)252 static inline void udc_set_mask_UDCCR(int mask)
253 {
254 /*
255 * The UDCCR reg contains mask and interrupt status bits,
256 * so using '|=' isn't safe as it may ack an interrupt.
257 */
258 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
259
260 mask &= mask_bits;
261 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
262 }
263
udc_clear_mask_UDCCR(int mask)264 static inline void udc_clear_mask_UDCCR(int mask)
265 {
266 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
267
268 mask = ~mask & mask_bits;
269 clrbits_le32(&the_controller->regs->udccr, ~mask);
270 }
271
udc_ack_int_UDCCR(int mask)272 static inline void udc_ack_int_UDCCR(int mask)
273 {
274 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
275
276 mask &= ~mask_bits;
277 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
278 }
279
280 /*
281 * endpoint enable/disable
282 *
283 * we need to verify the descriptors used to enable endpoints. since pxa25x
284 * endpoint configurations are fixed, and are pretty much always enabled,
285 * there's not a lot to manage here.
286 *
287 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
288 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
289 * for a single interface (with only the default altsetting) and for gadget
290 * drivers that don't halt endpoints (not reset by set_interface). that also
291 * means that if you use ISO, you must violate the USB spec rule that all
292 * iso endpoints must be in non-default altsettings.
293 */
pxa25x_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)294 static int pxa25x_ep_enable(struct usb_ep *_ep,
295 const struct usb_endpoint_descriptor *desc)
296 {
297 struct pxa25x_ep *ep;
298 struct pxa25x_udc *dev;
299
300 ep = container_of(_ep, struct pxa25x_ep, ep);
301 if (!_ep || !desc || ep->desc || _ep->name == ep0name
302 || desc->bDescriptorType != USB_DT_ENDPOINT
303 || ep->bEndpointAddress != desc->bEndpointAddress
304 || ep->fifo_size <
305 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
306 printf("%s, bad ep or descriptor\n", __func__);
307 return -EINVAL;
308 }
309
310 /* xfer types must match, except that interrupt ~= bulk */
311 if (ep->bmAttributes != desc->bmAttributes
312 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
313 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
314 printf("%s, %s type mismatch\n", __func__, _ep->name);
315 return -EINVAL;
316 }
317
318 /* hardware _could_ do smaller, but driver doesn't */
319 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
320 && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
321 != BULK_FIFO_SIZE)
322 || !get_unaligned(&desc->wMaxPacketSize)) {
323 printf("%s, bad %s maxpacket\n", __func__, _ep->name);
324 return -ERANGE;
325 }
326
327 dev = ep->dev;
328 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
329 printf("%s, bogus device state\n", __func__);
330 return -ESHUTDOWN;
331 }
332
333 ep->desc = desc;
334 ep->stopped = 0;
335 ep->pio_irqs = 0;
336 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
337
338 /* flush fifo (mostly for OUT buffers) */
339 pxa25x_ep_fifo_flush(_ep);
340
341 /* ... reset halt state too, if we could ... */
342
343 debug("enabled %s\n", _ep->name);
344 return 0;
345 }
346
pxa25x_ep_disable(struct usb_ep * _ep)347 static int pxa25x_ep_disable(struct usb_ep *_ep)
348 {
349 struct pxa25x_ep *ep;
350 unsigned long flags;
351
352 ep = container_of(_ep, struct pxa25x_ep, ep);
353 if (!_ep || !ep->desc) {
354 printf("%s, %s not enabled\n", __func__,
355 _ep ? ep->ep.name : NULL);
356 return -EINVAL;
357 }
358 local_irq_save(flags);
359
360 nuke(ep, -ESHUTDOWN);
361
362 /* flush fifo (mostly for IN buffers) */
363 pxa25x_ep_fifo_flush(_ep);
364
365 ep->desc = NULL;
366 ep->stopped = 1;
367
368 local_irq_restore(flags);
369 debug("%s disabled\n", _ep->name);
370 return 0;
371 }
372
373 /*-------------------------------------------------------------------------*/
374
375 /*
376 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
377 * must still pass correctly initialized endpoints, since other controller
378 * drivers may care about how it's currently set up (dma issues etc).
379 */
380
381 /*
382 * pxa25x_ep_alloc_request - allocate a request data structure
383 */
384 static struct usb_request *
pxa25x_ep_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)385 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
386 {
387 struct pxa25x_request *req;
388
389 req = kzalloc(sizeof(*req), gfp_flags);
390 if (!req)
391 return NULL;
392
393 INIT_LIST_HEAD(&req->queue);
394 return &req->req;
395 }
396
397
398 /*
399 * pxa25x_ep_free_request - deallocate a request data structure
400 */
401 static void
pxa25x_ep_free_request(struct usb_ep * _ep,struct usb_request * _req)402 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
403 {
404 struct pxa25x_request *req;
405
406 req = container_of(_req, struct pxa25x_request, req);
407 WARN_ON(!list_empty(&req->queue));
408 kfree(req);
409 }
410
411 /*-------------------------------------------------------------------------*/
412
413 /*
414 * done - retire a request; caller blocked irqs
415 */
done(struct pxa25x_ep * ep,struct pxa25x_request * req,int status)416 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
417 {
418 unsigned stopped = ep->stopped;
419
420 list_del_init(&req->queue);
421
422 if (likely(req->req.status == -EINPROGRESS))
423 req->req.status = status;
424 else
425 status = req->req.status;
426
427 if (status && status != -ESHUTDOWN)
428 debug("complete %s req %p stat %d len %u/%u\n",
429 ep->ep.name, &req->req, status,
430 req->req.actual, req->req.length);
431
432 /* don't modify queue heads during completion callback */
433 ep->stopped = 1;
434 req->req.complete(&ep->ep, &req->req);
435 ep->stopped = stopped;
436 }
437
438
ep0_idle(struct pxa25x_udc * dev)439 static inline void ep0_idle(struct pxa25x_udc *dev)
440 {
441 dev->ep0state = EP0_IDLE;
442 }
443
444 static int
write_packet(u32 * uddr,struct pxa25x_request * req,unsigned max)445 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
446 {
447 u8 *buf;
448 unsigned length, count;
449
450 debug("%s(): uddr %p\n", __func__, uddr);
451
452 buf = req->req.buf + req->req.actual;
453 prefetch(buf);
454
455 /* how big will this packet be? */
456 length = min(req->req.length - req->req.actual, max);
457 req->req.actual += length;
458
459 count = length;
460 while (likely(count--))
461 writeb(*buf++, uddr);
462
463 return length;
464 }
465
466 /*
467 * write to an IN endpoint fifo, as many packets as possible.
468 * irqs will use this to write the rest later.
469 * caller guarantees at least one packet buffer is ready (or a zlp).
470 */
471 static int
write_fifo(struct pxa25x_ep * ep,struct pxa25x_request * req)472 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
473 {
474 unsigned max;
475
476 max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
477 do {
478 unsigned count;
479 int is_last, is_short;
480
481 count = write_packet(ep->reg_uddr, req, max);
482
483 /* last packet is usually short (or a zlp) */
484 if (unlikely(count != max))
485 is_last = is_short = 1;
486 else {
487 if (likely(req->req.length != req->req.actual)
488 || req->req.zero)
489 is_last = 0;
490 else
491 is_last = 1;
492 /* interrupt/iso maxpacket may not fill the fifo */
493 is_short = unlikely(max < ep->fifo_size);
494 }
495
496 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
497 ep->ep.name, count,
498 is_last ? "/L" : "", is_short ? "/S" : "",
499 req->req.length - req->req.actual, req);
500
501 /*
502 * let loose that packet. maybe try writing another one,
503 * double buffering might work. TSP, TPC, and TFS
504 * bit values are the same for all normal IN endpoints.
505 */
506 writel(UDCCS_BI_TPC, ep->reg_udccs);
507 if (is_short)
508 writel(UDCCS_BI_TSP, ep->reg_udccs);
509
510 /* requests complete when all IN data is in the FIFO */
511 if (is_last) {
512 done(ep, req, 0);
513 if (list_empty(&ep->queue))
514 pio_irq_disable(ep->bEndpointAddress);
515 return 1;
516 }
517
518 /*
519 * TODO experiment: how robust can fifo mode tweaking be?
520 * double buffering is off in the default fifo mode, which
521 * prevents TFS from being set here.
522 */
523
524 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
525 return 0;
526 }
527
528 /*
529 * caller asserts req->pending (ep0 irq status nyet cleared); starts
530 * ep0 data stage. these chips want very simple state transitions.
531 */
532 static inline
ep0start(struct pxa25x_udc * dev,u32 flags,const char * tag)533 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
534 {
535 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
536 writel(USIR0_IR0, &dev->regs->usir0);
537 dev->req_pending = 0;
538 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
539 __func__, tag, readl(&dev->regs->udccs[0]), flags,
540 readl(&dev->regs->usir1), readl(&dev->regs->usir0));
541 }
542
543 static int
write_ep0_fifo(struct pxa25x_ep * ep,struct pxa25x_request * req)544 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
545 {
546 unsigned count;
547 int is_short;
548
549 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
550 ep->dev->stats.write.bytes += count;
551
552 /* last packet "must be" short (or a zlp) */
553 is_short = (count != EP0_FIFO_SIZE);
554
555 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
556 req->req.length - req->req.actual, req);
557
558 if (unlikely(is_short)) {
559 if (ep->dev->req_pending)
560 ep0start(ep->dev, UDCCS0_IPR, "short IN");
561 else
562 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
563
564 count = req->req.length;
565 done(ep, req, 0);
566 ep0_idle(ep->dev);
567
568 /*
569 * This seems to get rid of lost status irqs in some cases:
570 * host responds quickly, or next request involves config
571 * change automagic, or should have been hidden, or ...
572 *
573 * FIXME get rid of all udelays possible...
574 */
575 if (count >= EP0_FIFO_SIZE) {
576 count = 100;
577 do {
578 if ((readl(&ep->dev->regs->udccs[0]) &
579 UDCCS0_OPR) != 0) {
580 /* clear OPR, generate ack */
581 writel(UDCCS0_OPR,
582 &ep->dev->regs->udccs[0]);
583 break;
584 }
585 count--;
586 udelay(1);
587 } while (count);
588 }
589 } else if (ep->dev->req_pending)
590 ep0start(ep->dev, 0, "IN");
591
592 return is_short;
593 }
594
595
596 /*
597 * read_fifo - unload packet(s) from the fifo we use for usb OUT
598 * transfers and put them into the request. caller should have made
599 * sure there's at least one packet ready.
600 *
601 * returns true if the request completed because of short packet or the
602 * request buffer having filled (and maybe overran till end-of-packet).
603 */
604 static int
read_fifo(struct pxa25x_ep * ep,struct pxa25x_request * req)605 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
606 {
607 u32 udccs;
608 u8 *buf;
609 unsigned bufferspace, count, is_short;
610
611 for (;;) {
612 /*
613 * make sure there's a packet in the FIFO.
614 * UDCCS_{BO,IO}_RPC are all the same bit value.
615 * UDCCS_{BO,IO}_RNE are all the same bit value.
616 */
617 udccs = readl(ep->reg_udccs);
618 if (unlikely((udccs & UDCCS_BO_RPC) == 0))
619 break;
620 buf = req->req.buf + req->req.actual;
621 prefetchw(buf);
622 bufferspace = req->req.length - req->req.actual;
623
624 /* read all bytes from this packet */
625 if (likely(udccs & UDCCS_BO_RNE)) {
626 count = 1 + (0x0ff & readl(ep->reg_ubcr));
627 req->req.actual += min(count, bufferspace);
628 } else /* zlp */
629 count = 0;
630 is_short = (count < ep->ep.maxpacket);
631 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
632 ep->ep.name, udccs, count,
633 is_short ? "/S" : "",
634 req, req->req.actual, req->req.length);
635 while (likely(count-- != 0)) {
636 u8 byte = readb(ep->reg_uddr);
637
638 if (unlikely(bufferspace == 0)) {
639 /*
640 * this happens when the driver's buffer
641 * is smaller than what the host sent.
642 * discard the extra data.
643 */
644 if (req->req.status != -EOVERFLOW)
645 printf("%s overflow %d\n",
646 ep->ep.name, count);
647 req->req.status = -EOVERFLOW;
648 } else {
649 *buf++ = byte;
650 bufferspace--;
651 }
652 }
653 writel(UDCCS_BO_RPC, ep->reg_udccs);
654 /* RPC/RSP/RNE could now reflect the other packet buffer */
655
656 /* iso is one request per packet */
657 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
658 if (udccs & UDCCS_IO_ROF)
659 req->req.status = -EHOSTUNREACH;
660 /* more like "is_done" */
661 is_short = 1;
662 }
663
664 /* completion */
665 if (is_short || req->req.actual == req->req.length) {
666 done(ep, req, 0);
667 if (list_empty(&ep->queue))
668 pio_irq_disable(ep->bEndpointAddress);
669 return 1;
670 }
671
672 /* finished that packet. the next one may be waiting... */
673 }
674 return 0;
675 }
676
677 /*
678 * special ep0 version of the above. no UBCR0 or double buffering; status
679 * handshaking is magic. most device protocols don't need control-OUT.
680 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
681 * protocols do use them.
682 */
683 static int
read_ep0_fifo(struct pxa25x_ep * ep,struct pxa25x_request * req)684 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
685 {
686 u8 *buf, byte;
687 unsigned bufferspace;
688
689 buf = req->req.buf + req->req.actual;
690 bufferspace = req->req.length - req->req.actual;
691
692 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
693 byte = (u8)readb(&ep->dev->regs->uddr0);
694
695 if (unlikely(bufferspace == 0)) {
696 /*
697 * this happens when the driver's buffer
698 * is smaller than what the host sent.
699 * discard the extra data.
700 */
701 if (req->req.status != -EOVERFLOW)
702 printf("%s overflow\n", ep->ep.name);
703 req->req.status = -EOVERFLOW;
704 } else {
705 *buf++ = byte;
706 req->req.actual++;
707 bufferspace--;
708 }
709 }
710
711 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
712
713 /* completion */
714 if (req->req.actual >= req->req.length)
715 return 1;
716
717 /* finished that packet. the next one may be waiting... */
718 return 0;
719 }
720
721 /*-------------------------------------------------------------------------*/
722
723 static int
pxa25x_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)724 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
725 {
726 struct pxa25x_request *req;
727 struct pxa25x_ep *ep;
728 struct pxa25x_udc *dev;
729 unsigned long flags;
730
731 req = container_of(_req, struct pxa25x_request, req);
732 if (unlikely(!_req || !_req->complete || !_req->buf
733 || !list_empty(&req->queue))) {
734 printf("%s, bad params\n", __func__);
735 return -EINVAL;
736 }
737
738 ep = container_of(_ep, struct pxa25x_ep, ep);
739 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
740 printf("%s, bad ep\n", __func__);
741 return -EINVAL;
742 }
743
744 dev = ep->dev;
745 if (unlikely(!dev->driver
746 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
747 printf("%s, bogus device state\n", __func__);
748 return -ESHUTDOWN;
749 }
750
751 /*
752 * iso is always one packet per request, that's the only way
753 * we can report per-packet status. that also helps with dma.
754 */
755 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
756 && req->req.length >
757 le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
758 return -EMSGSIZE;
759
760 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
761 _ep->name, _req, _req->length, _req->buf);
762
763 local_irq_save(flags);
764
765 _req->status = -EINPROGRESS;
766 _req->actual = 0;
767
768 /* kickstart this i/o queue? */
769 if (list_empty(&ep->queue) && !ep->stopped) {
770 if (ep->desc == NULL/* ep0 */) {
771 unsigned length = _req->length;
772
773 switch (dev->ep0state) {
774 case EP0_IN_DATA_PHASE:
775 dev->stats.write.ops++;
776 if (write_ep0_fifo(ep, req))
777 req = NULL;
778 break;
779
780 case EP0_OUT_DATA_PHASE:
781 dev->stats.read.ops++;
782 /* messy ... */
783 if (dev->req_config) {
784 debug("ep0 config ack%s\n",
785 dev->has_cfr ? "" : " raced");
786 if (dev->has_cfr)
787 writel(UDCCFR_AREN|UDCCFR_ACM
788 |UDCCFR_MB1,
789 &ep->dev->regs->udccfr);
790 done(ep, req, 0);
791 dev->ep0state = EP0_END_XFER;
792 local_irq_restore(flags);
793 return 0;
794 }
795 if (dev->req_pending)
796 ep0start(dev, UDCCS0_IPR, "OUT");
797 if (length == 0 ||
798 ((readl(
799 &ep->dev->regs->udccs[0])
800 & UDCCS0_RNE) != 0
801 && read_ep0_fifo(ep, req))) {
802 ep0_idle(dev);
803 done(ep, req, 0);
804 req = NULL;
805 }
806 break;
807
808 default:
809 printf("ep0 i/o, odd state %d\n",
810 dev->ep0state);
811 local_irq_restore(flags);
812 return -EL2HLT;
813 }
814 /* can the FIFO can satisfy the request immediately? */
815 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
816 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
817 && write_fifo(ep, req))
818 req = NULL;
819 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
820 && read_fifo(ep, req)) {
821 req = NULL;
822 }
823
824 if (likely(req && ep->desc))
825 pio_irq_enable(ep->bEndpointAddress);
826 }
827
828 /* pio or dma irq handler advances the queue. */
829 if (likely(req != NULL))
830 list_add_tail(&req->queue, &ep->queue);
831 local_irq_restore(flags);
832
833 return 0;
834 }
835
836
837 /*
838 * nuke - dequeue ALL requests
839 */
nuke(struct pxa25x_ep * ep,int status)840 static void nuke(struct pxa25x_ep *ep, int status)
841 {
842 struct pxa25x_request *req;
843
844 /* called with irqs blocked */
845 while (!list_empty(&ep->queue)) {
846 req = list_entry(ep->queue.next,
847 struct pxa25x_request,
848 queue);
849 done(ep, req, status);
850 }
851 if (ep->desc)
852 pio_irq_disable(ep->bEndpointAddress);
853 }
854
855
856 /* dequeue JUST ONE request */
pxa25x_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)857 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
858 {
859 struct pxa25x_ep *ep;
860 struct pxa25x_request *req;
861 unsigned long flags;
862
863 ep = container_of(_ep, struct pxa25x_ep, ep);
864 if (!_ep || ep->ep.name == ep0name)
865 return -EINVAL;
866
867 local_irq_save(flags);
868
869 /* make sure it's actually queued on this endpoint */
870 list_for_each_entry(req, &ep->queue, queue) {
871 if (&req->req == _req)
872 break;
873 }
874 if (&req->req != _req) {
875 local_irq_restore(flags);
876 return -EINVAL;
877 }
878
879 done(ep, req, -ECONNRESET);
880
881 local_irq_restore(flags);
882 return 0;
883 }
884
885 /*-------------------------------------------------------------------------*/
886
pxa25x_ep_set_halt(struct usb_ep * _ep,int value)887 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
888 {
889 struct pxa25x_ep *ep;
890 unsigned long flags;
891
892 ep = container_of(_ep, struct pxa25x_ep, ep);
893 if (unlikely(!_ep
894 || (!ep->desc && ep->ep.name != ep0name))
895 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
896 printf("%s, bad ep\n", __func__);
897 return -EINVAL;
898 }
899 if (value == 0) {
900 /*
901 * this path (reset toggle+halt) is needed to implement
902 * SET_INTERFACE on normal hardware. but it can't be
903 * done from software on the PXA UDC, and the hardware
904 * forgets to do it as part of SET_INTERFACE automagic.
905 */
906 printf("only host can clear %s halt\n", _ep->name);
907 return -EROFS;
908 }
909
910 local_irq_save(flags);
911
912 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
913 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
914 || !list_empty(&ep->queue))) {
915 local_irq_restore(flags);
916 return -EAGAIN;
917 }
918
919 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
920 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
921
922 /* ep0 needs special care */
923 if (!ep->desc) {
924 start_watchdog(ep->dev);
925 ep->dev->req_pending = 0;
926 ep->dev->ep0state = EP0_STALL;
927
928 /* and bulk/intr endpoints like dropping stalls too */
929 } else {
930 unsigned i;
931 for (i = 0; i < 1000; i += 20) {
932 if (readl(ep->reg_udccs) & UDCCS_BI_SST)
933 break;
934 udelay(20);
935 }
936 }
937 local_irq_restore(flags);
938
939 debug("%s halt\n", _ep->name);
940 return 0;
941 }
942
pxa25x_ep_fifo_status(struct usb_ep * _ep)943 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
944 {
945 struct pxa25x_ep *ep;
946
947 ep = container_of(_ep, struct pxa25x_ep, ep);
948 if (!_ep) {
949 printf("%s, bad ep\n", __func__);
950 return -ENODEV;
951 }
952 /* pxa can't report unclaimed bytes from IN fifos */
953 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
954 return -EOPNOTSUPP;
955 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
956 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
957 return 0;
958 else
959 return (readl(ep->reg_ubcr) & 0xfff) + 1;
960 }
961
pxa25x_ep_fifo_flush(struct usb_ep * _ep)962 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
963 {
964 struct pxa25x_ep *ep;
965
966 ep = container_of(_ep, struct pxa25x_ep, ep);
967 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
968 printf("%s, bad ep\n", __func__);
969 return;
970 }
971
972 /* toggle and halt bits stay unchanged */
973
974 /* for OUT, just read and discard the FIFO contents. */
975 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
976 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
977 (void)readb(ep->reg_uddr);
978 return;
979 }
980
981 /* most IN status is the same, but ISO can't stall */
982 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
983 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
984 ? 0 : UDCCS_BI_SST), ep->reg_udccs);
985 }
986
987
988 static struct usb_ep_ops pxa25x_ep_ops = {
989 .enable = pxa25x_ep_enable,
990 .disable = pxa25x_ep_disable,
991
992 .alloc_request = pxa25x_ep_alloc_request,
993 .free_request = pxa25x_ep_free_request,
994
995 .queue = pxa25x_ep_queue,
996 .dequeue = pxa25x_ep_dequeue,
997
998 .set_halt = pxa25x_ep_set_halt,
999 .fifo_status = pxa25x_ep_fifo_status,
1000 .fifo_flush = pxa25x_ep_fifo_flush,
1001 };
1002
1003
1004 /* ---------------------------------------------------------------------------
1005 * device-scoped parts of the api to the usb controller hardware
1006 * ---------------------------------------------------------------------------
1007 */
1008
pxa25x_udc_get_frame(struct usb_gadget * _gadget)1009 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1010 {
1011 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
1012 (readl(&the_controller->regs->ufnrl) & 0xff);
1013 }
1014
pxa25x_udc_wakeup(struct usb_gadget * _gadget)1015 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1016 {
1017 /* host may not have enabled remote wakeup */
1018 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
1019 return -EHOSTUNREACH;
1020 udc_set_mask_UDCCR(UDCCR_RSM);
1021 return 0;
1022 }
1023
1024 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1025 static void udc_enable(struct pxa25x_udc *);
1026 static void udc_disable(struct pxa25x_udc *);
1027
1028 /*
1029 * We disable the UDC -- and its 48 MHz clock -- whenever it's not
1030 * in active use.
1031 */
pullup(struct pxa25x_udc * udc)1032 static int pullup(struct pxa25x_udc *udc)
1033 {
1034 if (udc->pullup)
1035 pullup_on();
1036 else
1037 pullup_off();
1038
1039
1040 int is_active = udc->pullup;
1041 if (is_active) {
1042 if (!udc->active) {
1043 udc->active = 1;
1044 udc_enable(udc);
1045 }
1046 } else {
1047 if (udc->active) {
1048 if (udc->gadget.speed != USB_SPEED_UNKNOWN)
1049 stop_activity(udc, udc->driver);
1050 udc_disable(udc);
1051 udc->active = 0;
1052 }
1053
1054 }
1055 return 0;
1056 }
1057
1058 /* VBUS reporting logically comes from a transceiver */
pxa25x_udc_vbus_session(struct usb_gadget * _gadget,int is_active)1059 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1060 {
1061 struct pxa25x_udc *udc;
1062
1063 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1064 printf("vbus %s\n", is_active ? "supplied" : "inactive");
1065 pullup(udc);
1066 return 0;
1067 }
1068
1069 /* drivers may have software control over D+ pullup */
pxa25x_udc_pullup(struct usb_gadget * _gadget,int is_active)1070 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1071 {
1072 struct pxa25x_udc *udc;
1073
1074 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1075
1076 /* not all boards support pullup control */
1077 if (!udc->mach->udc_command)
1078 return -EOPNOTSUPP;
1079
1080 udc->pullup = (is_active != 0);
1081 pullup(udc);
1082 return 0;
1083 }
1084
1085 /*
1086 * boards may consume current from VBUS, up to 100-500mA based on config.
1087 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1088 * violate USB specs.
1089 */
pxa25x_udc_vbus_draw(struct usb_gadget * _gadget,unsigned mA)1090 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1091 {
1092 return -EOPNOTSUPP;
1093 }
1094
1095 static const struct usb_gadget_ops pxa25x_udc_ops = {
1096 .get_frame = pxa25x_udc_get_frame,
1097 .wakeup = pxa25x_udc_wakeup,
1098 .vbus_session = pxa25x_udc_vbus_session,
1099 .pullup = pxa25x_udc_pullup,
1100 .vbus_draw = pxa25x_udc_vbus_draw,
1101 };
1102
1103 /*-------------------------------------------------------------------------*/
1104
1105 /*
1106 * udc_disable - disable USB device controller
1107 */
udc_disable(struct pxa25x_udc * dev)1108 static void udc_disable(struct pxa25x_udc *dev)
1109 {
1110 /* block all irqs */
1111 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1112 writel(0xff, &dev->regs->uicr0);
1113 writel(0xff, &dev->regs->uicr1);
1114 writel(UFNRH_SIM, &dev->regs->ufnrh);
1115
1116 /* if hardware supports it, disconnect from usb */
1117 pullup_off();
1118
1119 udc_clear_mask_UDCCR(UDCCR_UDE);
1120
1121 ep0_idle(dev);
1122 dev->gadget.speed = USB_SPEED_UNKNOWN;
1123 }
1124
1125 /*
1126 * udc_reinit - initialize software state
1127 */
udc_reinit(struct pxa25x_udc * dev)1128 static void udc_reinit(struct pxa25x_udc *dev)
1129 {
1130 u32 i;
1131
1132 /* device/ep0 records init */
1133 INIT_LIST_HEAD(&dev->gadget.ep_list);
1134 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1135 dev->ep0state = EP0_IDLE;
1136
1137 /* basic endpoint records init */
1138 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1139 struct pxa25x_ep *ep = &dev->ep[i];
1140
1141 if (i != 0)
1142 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1143
1144 ep->desc = NULL;
1145 ep->stopped = 0;
1146 INIT_LIST_HEAD(&ep->queue);
1147 ep->pio_irqs = 0;
1148 }
1149
1150 /* the rest was statically initialized, and is read-only */
1151 }
1152
1153 /*
1154 * until it's enabled, this UDC should be completely invisible
1155 * to any USB host.
1156 */
udc_enable(struct pxa25x_udc * dev)1157 static void udc_enable(struct pxa25x_udc *dev)
1158 {
1159 debug("udc: enabling udc\n");
1160
1161 udc_clear_mask_UDCCR(UDCCR_UDE);
1162
1163 /*
1164 * Try to clear these bits before we enable the udc.
1165 * Do not touch reset ack bit, we would take care of it in
1166 * interrupt handle routine
1167 */
1168 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
1169
1170 ep0_idle(dev);
1171 dev->gadget.speed = USB_SPEED_UNKNOWN;
1172 dev->stats.irqs = 0;
1173
1174 /*
1175 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1176 * - enable UDC
1177 * - if RESET is already in progress, ack interrupt
1178 * - unmask reset interrupt
1179 */
1180 udc_set_mask_UDCCR(UDCCR_UDE);
1181 if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
1182 udc_ack_int_UDCCR(UDCCR_RSTIR);
1183
1184 if (dev->has_cfr /* UDC_RES2 is defined */) {
1185 /*
1186 * pxa255 (a0+) can avoid a set_config race that could
1187 * prevent gadget drivers from configuring correctly
1188 */
1189 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
1190 }
1191
1192 /* enable suspend/resume and reset irqs */
1193 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1194
1195 /* enable ep0 irqs */
1196 clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
1197
1198 /* if hardware supports it, pullup D+ and wait for reset */
1199 pullup_on();
1200 }
1201
clear_ep_state(struct pxa25x_udc * dev)1202 static inline void clear_ep_state(struct pxa25x_udc *dev)
1203 {
1204 unsigned i;
1205
1206 /*
1207 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1208 * fifos, and pending transactions mustn't be continued in any case.
1209 */
1210 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1211 nuke(&dev->ep[i], -ECONNABORTED);
1212 }
1213
handle_ep0(struct pxa25x_udc * dev)1214 static void handle_ep0(struct pxa25x_udc *dev)
1215 {
1216 u32 udccs0 = readl(&dev->regs->udccs[0]);
1217 struct pxa25x_ep *ep = &dev->ep[0];
1218 struct pxa25x_request *req;
1219 union {
1220 struct usb_ctrlrequest r;
1221 u8 raw[8];
1222 u32 word[2];
1223 } u;
1224
1225 if (list_empty(&ep->queue))
1226 req = NULL;
1227 else
1228 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1229
1230 /* clear stall status */
1231 if (udccs0 & UDCCS0_SST) {
1232 nuke(ep, -EPIPE);
1233 writel(UDCCS0_SST, &dev->regs->udccs[0]);
1234 stop_watchdog(dev);
1235 ep0_idle(dev);
1236 }
1237
1238 /* previous request unfinished? non-error iff back-to-back ... */
1239 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1240 nuke(ep, 0);
1241 stop_watchdog(dev);
1242 ep0_idle(dev);
1243 }
1244
1245 switch (dev->ep0state) {
1246 case EP0_IDLE:
1247 /* late-breaking status? */
1248 udccs0 = readl(&dev->regs->udccs[0]);
1249
1250 /* start control request? */
1251 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1252 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1253 int i;
1254
1255 nuke(ep, -EPROTO);
1256
1257 /* read SETUP packet */
1258 for (i = 0; i < 8; i++) {
1259 if (unlikely(!(readl(&dev->regs->udccs[0]) &
1260 UDCCS0_RNE))) {
1261 bad_setup:
1262 debug("SETUP %d!\n", i);
1263 goto stall;
1264 }
1265 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1266 }
1267 if (unlikely((readl(&dev->regs->udccs[0]) &
1268 UDCCS0_RNE) != 0))
1269 goto bad_setup;
1270
1271 got_setup:
1272 debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
1273 u.r.bRequestType, u.r.bRequest,
1274 le16_to_cpu(u.r.wValue),
1275 le16_to_cpu(u.r.wIndex),
1276 le16_to_cpu(u.r.wLength));
1277
1278 /* cope with automagic for some standard requests. */
1279 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1280 == USB_TYPE_STANDARD;
1281 dev->req_config = 0;
1282 dev->req_pending = 1;
1283 switch (u.r.bRequest) {
1284 /* hardware restricts gadget drivers here! */
1285 case USB_REQ_SET_CONFIGURATION:
1286 debug("GOT SET_CONFIGURATION\n");
1287 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1288 /*
1289 * reflect hardware's automagic
1290 * up to the gadget driver.
1291 */
1292 config_change:
1293 dev->req_config = 1;
1294 clear_ep_state(dev);
1295 /*
1296 * if !has_cfr, there's no synch
1297 * else use AREN (later) not SA|OPR
1298 * USIR0_IR0 acts edge sensitive
1299 */
1300 }
1301 break;
1302 /* ... and here, even more ... */
1303 case USB_REQ_SET_INTERFACE:
1304 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1305 /*
1306 * udc hardware is broken by design:
1307 * - altsetting may only be zero;
1308 * - hw resets all interfaces' eps;
1309 * - ep reset doesn't include halt(?).
1310 */
1311 printf("broken set_interface (%d/%d)\n",
1312 le16_to_cpu(u.r.wIndex),
1313 le16_to_cpu(u.r.wValue));
1314 goto config_change;
1315 }
1316 break;
1317 /* hardware was supposed to hide this */
1318 case USB_REQ_SET_ADDRESS:
1319 debug("GOT SET ADDRESS\n");
1320 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1321 ep0start(dev, 0, "address");
1322 return;
1323 }
1324 break;
1325 }
1326
1327 if (u.r.bRequestType & USB_DIR_IN)
1328 dev->ep0state = EP0_IN_DATA_PHASE;
1329 else
1330 dev->ep0state = EP0_OUT_DATA_PHASE;
1331
1332 i = dev->driver->setup(&dev->gadget, &u.r);
1333 if (i < 0) {
1334 /* hardware automagic preventing STALL... */
1335 if (dev->req_config) {
1336 /*
1337 * hardware sometimes neglects to tell
1338 * tell us about config change events,
1339 * so later ones may fail...
1340 */
1341 printf("config change %02x fail %d?\n",
1342 u.r.bRequest, i);
1343 return;
1344 /*
1345 * TODO experiment: if has_cfr,
1346 * hardware didn't ACK; maybe we
1347 * could actually STALL!
1348 */
1349 }
1350 if (0) {
1351 stall:
1352 /* uninitialized when goto stall */
1353 i = 0;
1354 }
1355 debug("protocol STALL, "
1356 "%02x err %d\n",
1357 readl(&dev->regs->udccs[0]), i);
1358
1359 /*
1360 * the watchdog timer helps deal with cases
1361 * where udc seems to clear FST wrongly, and
1362 * then NAKs instead of STALLing.
1363 */
1364 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1365 start_watchdog(dev);
1366 dev->ep0state = EP0_STALL;
1367
1368 /* deferred i/o == no response yet */
1369 } else if (dev->req_pending) {
1370 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1371 || dev->req_std || u.r.wLength))
1372 ep0start(dev, 0, "defer");
1373 else
1374 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1375 }
1376
1377 /* expect at least one data or status stage irq */
1378 return;
1379
1380 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1381 == (UDCCS0_OPR|UDCCS0_SA))) {
1382 unsigned i;
1383
1384 /*
1385 * pxa210/250 erratum 131 for B0/B1 says RNE lies.
1386 * still observed on a pxa255 a0.
1387 */
1388 debug("e131\n");
1389 nuke(ep, -EPROTO);
1390
1391 /* read SETUP data, but don't trust it too much */
1392 for (i = 0; i < 8; i++)
1393 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1394 if ((u.r.bRequestType & USB_RECIP_MASK)
1395 > USB_RECIP_OTHER)
1396 goto stall;
1397 if (u.word[0] == 0 && u.word[1] == 0)
1398 goto stall;
1399 goto got_setup;
1400 } else {
1401 /*
1402 * some random early IRQ:
1403 * - we acked FST
1404 * - IPR cleared
1405 * - OPR got set, without SA (likely status stage)
1406 */
1407 debug("random IRQ %X %X\n", udccs0,
1408 readl(&dev->regs->udccs[0]));
1409 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
1410 &dev->regs->udccs[0]);
1411 }
1412 break;
1413 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1414 if (udccs0 & UDCCS0_OPR) {
1415 debug("ep0in premature status\n");
1416 if (req)
1417 done(ep, req, 0);
1418 ep0_idle(dev);
1419 } else /* irq was IPR clearing */ {
1420 if (req) {
1421 debug("next ep0 in packet\n");
1422 /* this IN packet might finish the request */
1423 (void) write_ep0_fifo(ep, req);
1424 } /* else IN token before response was written */
1425 }
1426 break;
1427 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1428 if (udccs0 & UDCCS0_OPR) {
1429 if (req) {
1430 /* this OUT packet might finish the request */
1431 if (read_ep0_fifo(ep, req))
1432 done(ep, req, 0);
1433 /* else more OUT packets expected */
1434 } /* else OUT token before read was issued */
1435 } else /* irq was IPR clearing */ {
1436 debug("ep0out premature status\n");
1437 if (req)
1438 done(ep, req, 0);
1439 ep0_idle(dev);
1440 }
1441 break;
1442 case EP0_END_XFER:
1443 if (req)
1444 done(ep, req, 0);
1445 /*
1446 * ack control-IN status (maybe in-zlp was skipped)
1447 * also appears after some config change events.
1448 */
1449 if (udccs0 & UDCCS0_OPR)
1450 writel(UDCCS0_OPR, &dev->regs->udccs[0]);
1451 ep0_idle(dev);
1452 break;
1453 case EP0_STALL:
1454 writel(UDCCS0_FST, &dev->regs->udccs[0]);
1455 break;
1456 }
1457
1458 writel(USIR0_IR0, &dev->regs->usir0);
1459 }
1460
handle_ep(struct pxa25x_ep * ep)1461 static void handle_ep(struct pxa25x_ep *ep)
1462 {
1463 struct pxa25x_request *req;
1464 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1465 int completed;
1466 u32 udccs, tmp;
1467
1468 do {
1469 completed = 0;
1470 if (likely(!list_empty(&ep->queue)))
1471 req = list_entry(ep->queue.next,
1472 struct pxa25x_request, queue);
1473 else
1474 req = NULL;
1475
1476 /* TODO check FST handling */
1477
1478 udccs = readl(ep->reg_udccs);
1479 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1480 tmp = UDCCS_BI_TUR;
1481 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1482 tmp |= UDCCS_BI_SST;
1483 tmp &= udccs;
1484 if (likely(tmp))
1485 writel(tmp, ep->reg_udccs);
1486 if (req && likely((udccs & UDCCS_BI_TFS) != 0))
1487 completed = write_fifo(ep, req);
1488
1489 } else { /* irq from RPC (or for ISO, ROF) */
1490 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1491 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1492 else
1493 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1494 tmp &= udccs;
1495 if (likely(tmp))
1496 writel(tmp, ep->reg_udccs);
1497
1498 /* fifos can hold packets, ready for reading... */
1499 if (likely(req))
1500 completed = read_fifo(ep, req);
1501 else
1502 pio_irq_disable(ep->bEndpointAddress);
1503 }
1504 ep->pio_irqs++;
1505 } while (completed);
1506 }
1507
1508 /*
1509 * pxa25x_udc_irq - interrupt handler
1510 *
1511 * avoid delays in ep0 processing. the control handshaking isn't always
1512 * under software control (pxa250c0 and the pxa255 are better), and delays
1513 * could cause usb protocol errors.
1514 */
1515 static struct pxa25x_udc memory;
1516 static int
pxa25x_udc_irq(void)1517 pxa25x_udc_irq(void)
1518 {
1519 struct pxa25x_udc *dev = &memory;
1520 int handled;
1521
1522 test_watchdog(dev);
1523
1524 dev->stats.irqs++;
1525 do {
1526 u32 udccr = readl(&dev->regs->udccr);
1527
1528 handled = 0;
1529
1530 /* SUSpend Interrupt Request */
1531 if (unlikely(udccr & UDCCR_SUSIR)) {
1532 udc_ack_int_UDCCR(UDCCR_SUSIR);
1533 handled = 1;
1534 debug("USB suspend\n");
1535
1536 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1537 && dev->driver
1538 && dev->driver->suspend)
1539 dev->driver->suspend(&dev->gadget);
1540 ep0_idle(dev);
1541 }
1542
1543 /* RESume Interrupt Request */
1544 if (unlikely(udccr & UDCCR_RESIR)) {
1545 udc_ack_int_UDCCR(UDCCR_RESIR);
1546 handled = 1;
1547 debug("USB resume\n");
1548
1549 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1550 && dev->driver
1551 && dev->driver->resume)
1552 dev->driver->resume(&dev->gadget);
1553 }
1554
1555 /* ReSeT Interrupt Request - USB reset */
1556 if (unlikely(udccr & UDCCR_RSTIR)) {
1557 udc_ack_int_UDCCR(UDCCR_RSTIR);
1558 handled = 1;
1559
1560 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
1561 debug("USB reset start\n");
1562
1563 /*
1564 * reset driver and endpoints,
1565 * in case that's not yet done
1566 */
1567 stop_activity(dev, dev->driver);
1568
1569 } else {
1570 debug("USB reset end\n");
1571 dev->gadget.speed = USB_SPEED_FULL;
1572 memset(&dev->stats, 0, sizeof dev->stats);
1573 /* driver and endpoints are still reset */
1574 }
1575
1576 } else {
1577 u32 uicr0 = readl(&dev->regs->uicr0);
1578 u32 uicr1 = readl(&dev->regs->uicr1);
1579 u32 usir0 = readl(&dev->regs->usir0);
1580 u32 usir1 = readl(&dev->regs->usir1);
1581
1582 usir0 = usir0 & ~uicr0;
1583 usir1 = usir1 & ~uicr1;
1584 int i;
1585
1586 if (unlikely(!usir0 && !usir1))
1587 continue;
1588
1589 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
1590
1591 /* control traffic */
1592 if (usir0 & USIR0_IR0) {
1593 dev->ep[0].pio_irqs++;
1594 handle_ep0(dev);
1595 handled = 1;
1596 }
1597
1598 /* endpoint data transfers */
1599 for (i = 0; i < 8; i++) {
1600 u32 tmp = 1 << i;
1601
1602 if (i && (usir0 & tmp)) {
1603 handle_ep(&dev->ep[i]);
1604 setbits_le32(&dev->regs->usir0, tmp);
1605 handled = 1;
1606 }
1607 #ifndef CONFIG_USB_PXA25X_SMALL
1608 if (usir1 & tmp) {
1609 handle_ep(&dev->ep[i+8]);
1610 setbits_le32(&dev->regs->usir1, tmp);
1611 handled = 1;
1612 }
1613 #endif
1614 }
1615 }
1616
1617 /* we could also ask for 1 msec SOF (SIR) interrupts */
1618
1619 } while (handled);
1620 return IRQ_HANDLED;
1621 }
1622
1623 /*-------------------------------------------------------------------------*/
1624
1625 /*
1626 * this uses load-time allocation and initialization (instead of
1627 * doing it at run-time) to save code, eliminate fault paths, and
1628 * be more obviously correct.
1629 */
1630 static struct pxa25x_udc memory = {
1631 .regs = UDC_REGS,
1632
1633 .gadget = {
1634 .ops = &pxa25x_udc_ops,
1635 .ep0 = &memory.ep[0].ep,
1636 .name = driver_name,
1637 },
1638
1639 /* control endpoint */
1640 .ep[0] = {
1641 .ep = {
1642 .name = ep0name,
1643 .ops = &pxa25x_ep_ops,
1644 .maxpacket = EP0_FIFO_SIZE,
1645 },
1646 .dev = &memory,
1647 .reg_udccs = &UDC_REGS->udccs[0],
1648 .reg_uddr = &UDC_REGS->uddr0,
1649 },
1650
1651 /* first group of endpoints */
1652 .ep[1] = {
1653 .ep = {
1654 .name = "ep1in-bulk",
1655 .ops = &pxa25x_ep_ops,
1656 .maxpacket = BULK_FIFO_SIZE,
1657 },
1658 .dev = &memory,
1659 .fifo_size = BULK_FIFO_SIZE,
1660 .bEndpointAddress = USB_DIR_IN | 1,
1661 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1662 .reg_udccs = &UDC_REGS->udccs[1],
1663 .reg_uddr = &UDC_REGS->uddr1,
1664 },
1665 .ep[2] = {
1666 .ep = {
1667 .name = "ep2out-bulk",
1668 .ops = &pxa25x_ep_ops,
1669 .maxpacket = BULK_FIFO_SIZE,
1670 },
1671 .dev = &memory,
1672 .fifo_size = BULK_FIFO_SIZE,
1673 .bEndpointAddress = 2,
1674 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1675 .reg_udccs = &UDC_REGS->udccs[2],
1676 .reg_ubcr = &UDC_REGS->ubcr2,
1677 .reg_uddr = &UDC_REGS->uddr2,
1678 },
1679 #ifndef CONFIG_USB_PXA25X_SMALL
1680 .ep[3] = {
1681 .ep = {
1682 .name = "ep3in-iso",
1683 .ops = &pxa25x_ep_ops,
1684 .maxpacket = ISO_FIFO_SIZE,
1685 },
1686 .dev = &memory,
1687 .fifo_size = ISO_FIFO_SIZE,
1688 .bEndpointAddress = USB_DIR_IN | 3,
1689 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1690 .reg_udccs = &UDC_REGS->udccs[3],
1691 .reg_uddr = &UDC_REGS->uddr3,
1692 },
1693 .ep[4] = {
1694 .ep = {
1695 .name = "ep4out-iso",
1696 .ops = &pxa25x_ep_ops,
1697 .maxpacket = ISO_FIFO_SIZE,
1698 },
1699 .dev = &memory,
1700 .fifo_size = ISO_FIFO_SIZE,
1701 .bEndpointAddress = 4,
1702 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1703 .reg_udccs = &UDC_REGS->udccs[4],
1704 .reg_ubcr = &UDC_REGS->ubcr4,
1705 .reg_uddr = &UDC_REGS->uddr4,
1706 },
1707 .ep[5] = {
1708 .ep = {
1709 .name = "ep5in-int",
1710 .ops = &pxa25x_ep_ops,
1711 .maxpacket = INT_FIFO_SIZE,
1712 },
1713 .dev = &memory,
1714 .fifo_size = INT_FIFO_SIZE,
1715 .bEndpointAddress = USB_DIR_IN | 5,
1716 .bmAttributes = USB_ENDPOINT_XFER_INT,
1717 .reg_udccs = &UDC_REGS->udccs[5],
1718 .reg_uddr = &UDC_REGS->uddr5,
1719 },
1720
1721 /* second group of endpoints */
1722 .ep[6] = {
1723 .ep = {
1724 .name = "ep6in-bulk",
1725 .ops = &pxa25x_ep_ops,
1726 .maxpacket = BULK_FIFO_SIZE,
1727 },
1728 .dev = &memory,
1729 .fifo_size = BULK_FIFO_SIZE,
1730 .bEndpointAddress = USB_DIR_IN | 6,
1731 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1732 .reg_udccs = &UDC_REGS->udccs[6],
1733 .reg_uddr = &UDC_REGS->uddr6,
1734 },
1735 .ep[7] = {
1736 .ep = {
1737 .name = "ep7out-bulk",
1738 .ops = &pxa25x_ep_ops,
1739 .maxpacket = BULK_FIFO_SIZE,
1740 },
1741 .dev = &memory,
1742 .fifo_size = BULK_FIFO_SIZE,
1743 .bEndpointAddress = 7,
1744 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1745 .reg_udccs = &UDC_REGS->udccs[7],
1746 .reg_ubcr = &UDC_REGS->ubcr7,
1747 .reg_uddr = &UDC_REGS->uddr7,
1748 },
1749 .ep[8] = {
1750 .ep = {
1751 .name = "ep8in-iso",
1752 .ops = &pxa25x_ep_ops,
1753 .maxpacket = ISO_FIFO_SIZE,
1754 },
1755 .dev = &memory,
1756 .fifo_size = ISO_FIFO_SIZE,
1757 .bEndpointAddress = USB_DIR_IN | 8,
1758 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1759 .reg_udccs = &UDC_REGS->udccs[8],
1760 .reg_uddr = &UDC_REGS->uddr8,
1761 },
1762 .ep[9] = {
1763 .ep = {
1764 .name = "ep9out-iso",
1765 .ops = &pxa25x_ep_ops,
1766 .maxpacket = ISO_FIFO_SIZE,
1767 },
1768 .dev = &memory,
1769 .fifo_size = ISO_FIFO_SIZE,
1770 .bEndpointAddress = 9,
1771 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1772 .reg_udccs = &UDC_REGS->udccs[9],
1773 .reg_ubcr = &UDC_REGS->ubcr9,
1774 .reg_uddr = &UDC_REGS->uddr9,
1775 },
1776 .ep[10] = {
1777 .ep = {
1778 .name = "ep10in-int",
1779 .ops = &pxa25x_ep_ops,
1780 .maxpacket = INT_FIFO_SIZE,
1781 },
1782 .dev = &memory,
1783 .fifo_size = INT_FIFO_SIZE,
1784 .bEndpointAddress = USB_DIR_IN | 10,
1785 .bmAttributes = USB_ENDPOINT_XFER_INT,
1786 .reg_udccs = &UDC_REGS->udccs[10],
1787 .reg_uddr = &UDC_REGS->uddr10,
1788 },
1789
1790 /* third group of endpoints */
1791 .ep[11] = {
1792 .ep = {
1793 .name = "ep11in-bulk",
1794 .ops = &pxa25x_ep_ops,
1795 .maxpacket = BULK_FIFO_SIZE,
1796 },
1797 .dev = &memory,
1798 .fifo_size = BULK_FIFO_SIZE,
1799 .bEndpointAddress = USB_DIR_IN | 11,
1800 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1801 .reg_udccs = &UDC_REGS->udccs[11],
1802 .reg_uddr = &UDC_REGS->uddr11,
1803 },
1804 .ep[12] = {
1805 .ep = {
1806 .name = "ep12out-bulk",
1807 .ops = &pxa25x_ep_ops,
1808 .maxpacket = BULK_FIFO_SIZE,
1809 },
1810 .dev = &memory,
1811 .fifo_size = BULK_FIFO_SIZE,
1812 .bEndpointAddress = 12,
1813 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1814 .reg_udccs = &UDC_REGS->udccs[12],
1815 .reg_ubcr = &UDC_REGS->ubcr12,
1816 .reg_uddr = &UDC_REGS->uddr12,
1817 },
1818 .ep[13] = {
1819 .ep = {
1820 .name = "ep13in-iso",
1821 .ops = &pxa25x_ep_ops,
1822 .maxpacket = ISO_FIFO_SIZE,
1823 },
1824 .dev = &memory,
1825 .fifo_size = ISO_FIFO_SIZE,
1826 .bEndpointAddress = USB_DIR_IN | 13,
1827 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1828 .reg_udccs = &UDC_REGS->udccs[13],
1829 .reg_uddr = &UDC_REGS->uddr13,
1830 },
1831 .ep[14] = {
1832 .ep = {
1833 .name = "ep14out-iso",
1834 .ops = &pxa25x_ep_ops,
1835 .maxpacket = ISO_FIFO_SIZE,
1836 },
1837 .dev = &memory,
1838 .fifo_size = ISO_FIFO_SIZE,
1839 .bEndpointAddress = 14,
1840 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1841 .reg_udccs = &UDC_REGS->udccs[14],
1842 .reg_ubcr = &UDC_REGS->ubcr14,
1843 .reg_uddr = &UDC_REGS->uddr14,
1844 },
1845 .ep[15] = {
1846 .ep = {
1847 .name = "ep15in-int",
1848 .ops = &pxa25x_ep_ops,
1849 .maxpacket = INT_FIFO_SIZE,
1850 },
1851 .dev = &memory,
1852 .fifo_size = INT_FIFO_SIZE,
1853 .bEndpointAddress = USB_DIR_IN | 15,
1854 .bmAttributes = USB_ENDPOINT_XFER_INT,
1855 .reg_udccs = &UDC_REGS->udccs[15],
1856 .reg_uddr = &UDC_REGS->uddr15,
1857 },
1858 #endif /* !CONFIG_USB_PXA25X_SMALL */
1859 };
1860
udc_command(int cmd)1861 static void udc_command(int cmd)
1862 {
1863 switch (cmd) {
1864 case PXA2XX_UDC_CMD_CONNECT:
1865 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1866 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1867
1868 /* enable pullup */
1869 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1870 GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
1871
1872 debug("Connected to USB\n");
1873 break;
1874
1875 case PXA2XX_UDC_CMD_DISCONNECT:
1876 /* disable pullup resistor */
1877 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1878 GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
1879
1880 /* setup pin as input, line will float */
1881 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1882 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1883
1884 debug("Disconnected from USB\n");
1885 break;
1886 }
1887 }
1888
1889 static struct pxa2xx_udc_mach_info mach_info = {
1890 .udc_command = udc_command,
1891 };
1892
1893 /*
1894 * when a driver is successfully registered, it will receive
1895 * control requests including set_configuration(), which enables
1896 * non-control requests. then usb traffic follows until a
1897 * disconnect is reported. then a host may connect again, or
1898 * the driver might get unbound.
1899 */
usb_gadget_register_driver(struct usb_gadget_driver * driver)1900 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1901 {
1902 struct pxa25x_udc *dev = &memory;
1903 int retval;
1904 uint32_t chiprev;
1905
1906 if (!driver
1907 || driver->speed < USB_SPEED_FULL
1908 || !driver->disconnect
1909 || !driver->setup)
1910 return -EINVAL;
1911 if (!dev)
1912 return -ENODEV;
1913 if (dev->driver)
1914 return -EBUSY;
1915
1916 /* Enable clock for usb controller */
1917 setbits_le32(CKEN, CKEN11_USB);
1918
1919 /* first hook up the driver ... */
1920 dev->driver = driver;
1921 dev->pullup = 1;
1922
1923 /* trigger chiprev-specific logic */
1924 switch ((chiprev = pxa_get_cpu_revision())) {
1925 case PXA255_A0:
1926 dev->has_cfr = 1;
1927 break;
1928 case PXA250_A0:
1929 case PXA250_A1:
1930 /* A0/A1 "not released"; ep 13, 15 unusable */
1931 /* fall through */
1932 case PXA250_B2: case PXA210_B2:
1933 case PXA250_B1: case PXA210_B1:
1934 case PXA250_B0: case PXA210_B0:
1935 /* OUT-DMA is broken ... */
1936 /* fall through */
1937 case PXA250_C0: case PXA210_C0:
1938 break;
1939 default:
1940 printf("%s: unrecognized processor: %08x\n",
1941 DRIVER_NAME, chiprev);
1942 return -ENODEV;
1943 }
1944
1945 the_controller = dev;
1946
1947 /* prepare watchdog timer */
1948 dev->watchdog.running = 0;
1949 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
1950 dev->watchdog.function = udc_watchdog;
1951
1952 dev->mach = &mach_info;
1953
1954 udc_disable(dev);
1955 udc_reinit(dev);
1956
1957 dev->gadget.name = "pxa2xx_udc";
1958 retval = driver->bind(&dev->gadget);
1959 if (retval) {
1960 printf("bind to driver %s --> error %d\n",
1961 DRIVER_NAME, retval);
1962 dev->driver = NULL;
1963 return retval;
1964 }
1965
1966 /*
1967 * ... then enable host detection and ep0; and we're ready
1968 * for set_configuration as well as eventual disconnect.
1969 */
1970 printf("registered gadget driver '%s'\n", DRIVER_NAME);
1971
1972 pullup(dev);
1973 dump_state(dev);
1974 return 0;
1975 }
1976
1977 static void
stop_activity(struct pxa25x_udc * dev,struct usb_gadget_driver * driver)1978 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1979 {
1980 int i;
1981
1982 /* don't disconnect drivers more than once */
1983 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1984 driver = NULL;
1985 dev->gadget.speed = USB_SPEED_UNKNOWN;
1986
1987 /* prevent new request submissions, kill any outstanding requests */
1988 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1989 struct pxa25x_ep *ep = &dev->ep[i];
1990
1991 ep->stopped = 1;
1992 nuke(ep, -ESHUTDOWN);
1993 }
1994 stop_watchdog(dev);
1995
1996 /* report disconnect; the driver is already quiesced */
1997 if (driver)
1998 driver->disconnect(&dev->gadget);
1999
2000 /* re-init driver-visible data structures */
2001 udc_reinit(dev);
2002 }
2003
usb_gadget_unregister_driver(struct usb_gadget_driver * driver)2004 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2005 {
2006 struct pxa25x_udc *dev = the_controller;
2007
2008 if (!dev)
2009 return -ENODEV;
2010 if (!driver || driver != dev->driver || !driver->unbind)
2011 return -EINVAL;
2012
2013 local_irq_disable();
2014 dev->pullup = 0;
2015 pullup(dev);
2016 stop_activity(dev, driver);
2017 local_irq_enable();
2018
2019 driver->unbind(&dev->gadget);
2020 dev->driver = NULL;
2021
2022 printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
2023 dump_state(dev);
2024
2025 the_controller = NULL;
2026
2027 clrbits_le32(CKEN, CKEN11_USB);
2028
2029 return 0;
2030 }
2031
udc_disconnect(void)2032 extern void udc_disconnect(void)
2033 {
2034 setbits_le32(CKEN, CKEN11_USB);
2035 udc_clear_mask_UDCCR(UDCCR_UDE);
2036 udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2037 clrbits_le32(CKEN, CKEN11_USB);
2038 }
2039
2040 /*-------------------------------------------------------------------------*/
2041
2042 extern int
usb_gadget_handle_interrupts(int index)2043 usb_gadget_handle_interrupts(int index)
2044 {
2045 return pxa25x_udc_irq();
2046 }
2047