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1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13612 bytes, from 2017-12-19 18:19:46)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  34499 bytes, from 2018-01-03 15:58:51)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2017-12-19 18:19:46)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 146261 bytes, from 2018-01-03 15:58:51)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
20 
21 Copyright (C) 2013-2018 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24 
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32 
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36 
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45 
46 
47 enum vgt_event_type {
48 	VS_DEALLOC = 0,
49 	PS_DEALLOC = 1,
50 	VS_DONE_TS = 2,
51 	PS_DONE_TS = 3,
52 	CACHE_FLUSH_TS = 4,
53 	CONTEXT_DONE = 5,
54 	CACHE_FLUSH = 6,
55 	HLSQ_FLUSH = 7,
56 	VIZQUERY_START = 7,
57 	VIZQUERY_END = 8,
58 	SC_WAIT_WC = 9,
59 	RST_PIX_CNT = 13,
60 	RST_VTX_CNT = 14,
61 	TILE_FLUSH = 15,
62 	STAT_EVENT = 16,
63 	CACHE_FLUSH_AND_INV_TS_EVENT = 20,
64 	ZPASS_DONE = 21,
65 	CACHE_FLUSH_AND_INV_EVENT = 22,
66 	PERFCOUNTER_START = 23,
67 	PERFCOUNTER_STOP = 24,
68 	VS_FETCH_DONE = 27,
69 	FACENESS_FLUSH = 28,
70 	FLUSH_SO_0 = 17,
71 	FLUSH_SO_1 = 18,
72 	FLUSH_SO_2 = 19,
73 	FLUSH_SO_3 = 20,
74 	UNK_19 = 25,
75 	UNK_1C = 28,
76 	UNK_1D = 29,
77 	BLIT = 30,
78 	UNK_25 = 37,
79 	LRZ_FLUSH = 38,
80 	UNK_2C = 44,
81 	UNK_2D = 45,
82 };
83 
84 enum pc_di_primtype {
85 	DI_PT_NONE = 0,
86 	DI_PT_POINTLIST_PSIZE = 1,
87 	DI_PT_LINELIST = 2,
88 	DI_PT_LINESTRIP = 3,
89 	DI_PT_TRILIST = 4,
90 	DI_PT_TRIFAN = 5,
91 	DI_PT_TRISTRIP = 6,
92 	DI_PT_LINELOOP = 7,
93 	DI_PT_RECTLIST = 8,
94 	DI_PT_POINTLIST = 9,
95 	DI_PT_LINE_ADJ = 10,
96 	DI_PT_LINESTRIP_ADJ = 11,
97 	DI_PT_TRI_ADJ = 12,
98 	DI_PT_TRISTRIP_ADJ = 13,
99 };
100 
101 enum pc_di_src_sel {
102 	DI_SRC_SEL_DMA = 0,
103 	DI_SRC_SEL_IMMEDIATE = 1,
104 	DI_SRC_SEL_AUTO_INDEX = 2,
105 	DI_SRC_SEL_RESERVED = 3,
106 };
107 
108 enum pc_di_index_size {
109 	INDEX_SIZE_IGN = 0,
110 	INDEX_SIZE_16_BIT = 0,
111 	INDEX_SIZE_32_BIT = 1,
112 	INDEX_SIZE_8_BIT = 2,
113 	INDEX_SIZE_INVALID = 0,
114 };
115 
116 enum pc_di_vis_cull_mode {
117 	IGNORE_VISIBILITY = 0,
118 	USE_VISIBILITY = 1,
119 };
120 
121 enum adreno_pm4_packet_type {
122 	CP_TYPE0_PKT = 0,
123 	CP_TYPE1_PKT = 0x40000000,
124 	CP_TYPE2_PKT = 0x80000000,
125 	CP_TYPE3_PKT = 0xc0000000,
126 	CP_TYPE4_PKT = 0x40000000,
127 	CP_TYPE7_PKT = 0x70000000,
128 };
129 
130 enum adreno_pm4_type3_packets {
131 	CP_ME_INIT = 72,
132 	CP_NOP = 16,
133 	CP_PREEMPT_ENABLE = 28,
134 	CP_PREEMPT_TOKEN = 30,
135 	CP_INDIRECT_BUFFER = 63,
136 	CP_INDIRECT_BUFFER_PFD = 55,
137 	CP_WAIT_FOR_IDLE = 38,
138 	CP_WAIT_REG_MEM = 60,
139 	CP_WAIT_REG_EQ = 82,
140 	CP_WAIT_REG_GTE = 83,
141 	CP_WAIT_UNTIL_READ = 92,
142 	CP_WAIT_IB_PFD_COMPLETE = 93,
143 	CP_REG_RMW = 33,
144 	CP_SET_BIN_DATA = 47,
145 	CP_SET_BIN_DATA5 = 47,
146 	CP_REG_TO_MEM = 62,
147 	CP_MEM_WRITE = 61,
148 	CP_MEM_WRITE_CNTR = 79,
149 	CP_COND_EXEC = 68,
150 	CP_COND_WRITE = 69,
151 	CP_COND_WRITE5 = 69,
152 	CP_EVENT_WRITE = 70,
153 	CP_EVENT_WRITE_SHD = 88,
154 	CP_EVENT_WRITE_CFL = 89,
155 	CP_EVENT_WRITE_ZPD = 91,
156 	CP_RUN_OPENCL = 49,
157 	CP_DRAW_INDX = 34,
158 	CP_DRAW_INDX_2 = 54,
159 	CP_DRAW_INDX_BIN = 52,
160 	CP_DRAW_INDX_2_BIN = 53,
161 	CP_VIZ_QUERY = 35,
162 	CP_SET_STATE = 37,
163 	CP_SET_CONSTANT = 45,
164 	CP_IM_LOAD = 39,
165 	CP_IM_LOAD_IMMEDIATE = 43,
166 	CP_LOAD_CONSTANT_CONTEXT = 46,
167 	CP_INVALIDATE_STATE = 59,
168 	CP_SET_SHADER_BASES = 74,
169 	CP_SET_BIN_MASK = 80,
170 	CP_SET_BIN_SELECT = 81,
171 	CP_CONTEXT_UPDATE = 94,
172 	CP_INTERRUPT = 64,
173 	CP_IM_STORE = 44,
174 	CP_SET_DRAW_INIT_FLAGS = 75,
175 	CP_SET_PROTECTED_MODE = 95,
176 	CP_BOOTSTRAP_UCODE = 111,
177 	CP_LOAD_STATE = 48,
178 	CP_LOAD_STATE4 = 48,
179 	CP_COND_INDIRECT_BUFFER_PFE = 58,
180 	CP_COND_INDIRECT_BUFFER_PFD = 50,
181 	CP_INDIRECT_BUFFER_PFE = 63,
182 	CP_SET_BIN = 76,
183 	CP_TEST_TWO_MEMS = 113,
184 	CP_REG_WR_NO_CTXT = 120,
185 	CP_RECORD_PFP_TIMESTAMP = 17,
186 	CP_SET_SECURE_MODE = 102,
187 	CP_WAIT_FOR_ME = 19,
188 	CP_SET_DRAW_STATE = 67,
189 	CP_DRAW_INDX_OFFSET = 56,
190 	CP_DRAW_INDIRECT = 40,
191 	CP_DRAW_INDX_INDIRECT = 41,
192 	CP_DRAW_AUTO = 36,
193 	CP_UNKNOWN_19 = 25,
194 	CP_UNKNOWN_1A = 26,
195 	CP_UNKNOWN_4E = 78,
196 	CP_WIDE_REG_WRITE = 116,
197 	CP_SCRATCH_TO_REG = 77,
198 	CP_REG_TO_SCRATCH = 74,
199 	CP_WAIT_MEM_WRITES = 18,
200 	CP_COND_REG_EXEC = 71,
201 	CP_MEM_TO_REG = 66,
202 	CP_EXEC_CS_INDIRECT = 65,
203 	CP_EXEC_CS = 51,
204 	CP_PERFCOUNTER_ACTION = 80,
205 	CP_SMMU_TABLE_UPDATE = 83,
206 	CP_CONTEXT_REG_BUNCH = 92,
207 	CP_YIELD_ENABLE = 28,
208 	CP_SKIP_IB2_ENABLE_GLOBAL = 29,
209 	CP_SKIP_IB2_ENABLE_LOCAL = 35,
210 	CP_SET_SUBDRAW_SIZE = 53,
211 	CP_SET_VISIBILITY_OVERRIDE = 100,
212 	CP_PREEMPT_ENABLE_GLOBAL = 105,
213 	CP_PREEMPT_ENABLE_LOCAL = 106,
214 	CP_CONTEXT_SWITCH_YIELD = 107,
215 	CP_SET_RENDER_MODE = 108,
216 	CP_COMPUTE_CHECKPOINT = 110,
217 	CP_MEM_TO_MEM = 115,
218 	CP_BLIT = 44,
219 	CP_UNK_39 = 57,
220 	IN_IB_PREFETCH_END = 23,
221 	IN_SUBBLK_PREFETCH = 31,
222 	IN_INSTR_PREFETCH = 32,
223 	IN_INSTR_MATCH = 71,
224 	IN_CONST_PREFETCH = 73,
225 	IN_INCR_UPDT_STATE = 85,
226 	IN_INCR_UPDT_CONST = 86,
227 	IN_INCR_UPDT_INSTR = 87,
228 	PKT4 = 4,
229 };
230 
231 enum adreno_state_block {
232 	SB_VERT_TEX = 0,
233 	SB_VERT_MIPADDR = 1,
234 	SB_FRAG_TEX = 2,
235 	SB_FRAG_MIPADDR = 3,
236 	SB_VERT_SHADER = 4,
237 	SB_GEOM_SHADER = 5,
238 	SB_FRAG_SHADER = 6,
239 	SB_COMPUTE_SHADER = 7,
240 };
241 
242 enum adreno_state_type {
243 	ST_SHADER = 0,
244 	ST_CONSTANTS = 1,
245 };
246 
247 enum adreno_state_src {
248 	SS_DIRECT = 0,
249 	SS_INVALID_ALL_IC = 2,
250 	SS_INVALID_PART_IC = 3,
251 	SS_INDIRECT = 4,
252 	SS_INDIRECT_TCM = 5,
253 	SS_INDIRECT_STM = 6,
254 };
255 
256 enum a4xx_state_block {
257 	SB4_VS_TEX = 0,
258 	SB4_HS_TEX = 1,
259 	SB4_DS_TEX = 2,
260 	SB4_GS_TEX = 3,
261 	SB4_FS_TEX = 4,
262 	SB4_CS_TEX = 5,
263 	SB4_VS_SHADER = 8,
264 	SB4_HS_SHADER = 9,
265 	SB4_DS_SHADER = 10,
266 	SB4_GS_SHADER = 11,
267 	SB4_FS_SHADER = 12,
268 	SB4_CS_SHADER = 13,
269 	SB4_SSBO = 14,
270 	SB4_CS_SSBO = 15,
271 };
272 
273 enum a4xx_state_type {
274 	ST4_SHADER = 0,
275 	ST4_CONSTANTS = 1,
276 };
277 
278 enum a4xx_state_src {
279 	SS4_DIRECT = 0,
280 	SS4_INDIRECT = 2,
281 };
282 
283 enum a4xx_index_size {
284 	INDEX4_SIZE_8_BIT = 0,
285 	INDEX4_SIZE_16_BIT = 1,
286 	INDEX4_SIZE_32_BIT = 2,
287 };
288 
289 enum cp_cond_function {
290 	WRITE_ALWAYS = 0,
291 	WRITE_LT = 1,
292 	WRITE_LE = 2,
293 	WRITE_EQ = 3,
294 	WRITE_NE = 4,
295 	WRITE_GE = 5,
296 	WRITE_GT = 6,
297 };
298 
299 enum render_mode_cmd {
300 	BYPASS = 1,
301 	BINNING = 2,
302 	GMEM = 3,
303 	BLIT2D = 5,
304 	BLIT2DSCALE = 7,
305 	END2D = 8,
306 };
307 
308 enum cp_blit_cmd {
309 	BLIT_OP_FILL = 0,
310 	BLIT_OP_COPY = 1,
311 	BLIT_OP_SCALE = 3,
312 };
313 
314 #define REG_CP_LOAD_STATE_0					0x00000000
315 #define CP_LOAD_STATE_0_DST_OFF__MASK				0x0000ffff
316 #define CP_LOAD_STATE_0_DST_OFF__SHIFT				0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)317 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
318 {
319 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
320 }
321 #define CP_LOAD_STATE_0_STATE_SRC__MASK				0x00070000
322 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT			16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)323 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
324 {
325 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
326 }
327 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK			0x00380000
328 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT			19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)329 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
330 {
331 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
332 }
333 #define CP_LOAD_STATE_0_NUM_UNIT__MASK				0xffc00000
334 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT				22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)335 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
336 {
337 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
338 }
339 
340 #define REG_CP_LOAD_STATE_1					0x00000001
341 #define CP_LOAD_STATE_1_STATE_TYPE__MASK			0x00000003
342 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT			0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)343 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
344 {
345 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
346 }
347 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK			0xfffffffc
348 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT			2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)349 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
350 {
351 	assert(!(val & 0x3));
352 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
353 }
354 
355 #define REG_CP_LOAD_STATE4_0					0x00000000
356 #define CP_LOAD_STATE4_0_DST_OFF__MASK				0x0000ffff
357 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT				0
CP_LOAD_STATE4_0_DST_OFF(uint32_t val)358 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
359 {
360 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
361 }
362 #define CP_LOAD_STATE4_0_STATE_SRC__MASK			0x00030000
363 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT			16
CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)364 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
365 {
366 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
367 }
368 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK			0x003c0000
369 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT			18
CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)370 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
371 {
372 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
373 }
374 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK				0xffc00000
375 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT			22
CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)376 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
377 {
378 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
379 }
380 
381 #define REG_CP_LOAD_STATE4_1					0x00000001
382 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK			0x00000003
383 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT			0
CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)384 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
385 {
386 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
387 }
388 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK			0xfffffffc
389 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT			2
CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)390 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
391 {
392 	assert(!(val & 0x3));
393 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
394 }
395 
396 #define REG_CP_LOAD_STATE4_2					0x00000002
397 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK			0xffffffff
398 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT			0
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)399 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
400 {
401 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
402 }
403 
404 #define REG_CP_DRAW_INDX_0					0x00000000
405 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff
406 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT				0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)407 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
408 {
409 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
410 }
411 
412 #define REG_CP_DRAW_INDX_1					0x00000001
413 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK				0x0000003f
414 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT				0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)415 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
416 {
417 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
418 }
419 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK			0x000000c0
420 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT			6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)421 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
422 {
423 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
424 }
425 #define CP_DRAW_INDX_1_VIS_CULL__MASK				0x00000600
426 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT				9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)427 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
428 {
429 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
430 }
431 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK				0x00000800
432 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT			11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)433 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
434 {
435 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
436 }
437 #define CP_DRAW_INDX_1_NOT_EOP					0x00001000
438 #define CP_DRAW_INDX_1_SMALL_INDEX				0x00002000
439 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
440 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK			0xff000000
441 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT			24
CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)442 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
443 {
444 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
445 }
446 
447 #define REG_CP_DRAW_INDX_2					0x00000002
448 #define CP_DRAW_INDX_2_NUM_INDICES__MASK			0xffffffff
449 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT			0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)450 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
451 {
452 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
453 }
454 
455 #define REG_CP_DRAW_INDX_3					0x00000003
456 #define CP_DRAW_INDX_3_INDX_BASE__MASK				0xffffffff
457 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT				0
CP_DRAW_INDX_3_INDX_BASE(uint32_t val)458 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
459 {
460 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
461 }
462 
463 #define REG_CP_DRAW_INDX_4					0x00000004
464 #define CP_DRAW_INDX_4_INDX_SIZE__MASK				0xffffffff
465 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT				0
CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)466 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
467 {
468 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
469 }
470 
471 #define REG_CP_DRAW_INDX_2_0					0x00000000
472 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK			0xffffffff
473 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT			0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)474 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
475 {
476 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
477 }
478 
479 #define REG_CP_DRAW_INDX_2_1					0x00000001
480 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK			0x0000003f
481 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT			0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)482 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
483 {
484 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
485 }
486 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK			0x000000c0
487 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT			6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)488 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
489 {
490 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
491 }
492 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK				0x00000600
493 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT			9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)494 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
495 {
496 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
497 }
498 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK			0x00000800
499 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT			11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)500 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
501 {
502 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
503 }
504 #define CP_DRAW_INDX_2_1_NOT_EOP				0x00001000
505 #define CP_DRAW_INDX_2_1_SMALL_INDEX				0x00002000
506 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
507 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK			0xff000000
508 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT			24
CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)509 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
510 {
511 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
512 }
513 
514 #define REG_CP_DRAW_INDX_2_2					0x00000002
515 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK			0xffffffff
516 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT			0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)517 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
518 {
519 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
520 }
521 
522 #define REG_CP_DRAW_INDX_OFFSET_0				0x00000000
523 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f
524 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)525 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
526 {
527 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
528 }
529 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0
530 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)531 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
532 {
533 	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
534 }
535 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK			0x00000300
536 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT			8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)537 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
538 {
539 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
540 }
541 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000c00
542 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			10
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)543 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
544 {
545 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
546 }
547 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK			0x01f00000
548 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT			20
CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)549 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
550 {
551 	return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
552 }
553 
554 #define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
555 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK		0xffffffff
556 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT		0
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)557 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
558 {
559 	return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
560 }
561 
562 #define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
563 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff
564 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)565 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
566 {
567 	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
568 }
569 
570 #define REG_CP_DRAW_INDX_OFFSET_3				0x00000003
571 
572 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
573 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK			0xffffffff
574 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT			0
CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)575 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
576 {
577 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
578 }
579 
580 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
581 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK			0xffffffff
582 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT			0
CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)583 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
584 {
585 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
586 }
587 
588 #define REG_A4XX_CP_DRAW_INDIRECT_0				0x00000000
589 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK			0x0000003f
590 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT		0
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)591 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
592 {
593 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
594 }
595 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK		0x000000c0
596 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT		6
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)597 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
598 {
599 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
600 }
601 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK			0x00000300
602 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT			8
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)603 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
604 {
605 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
606 }
607 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
608 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT		10
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)609 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
610 {
611 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
612 }
613 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK			0x01f00000
614 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT		20
A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)615 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
616 {
617 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
618 }
619 
620 #define REG_A4XX_CP_DRAW_INDIRECT_1				0x00000001
621 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK			0xffffffff
622 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT			0
A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)623 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
624 {
625 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
626 }
627 
628 
629 #define REG_A5XX_CP_DRAW_INDIRECT_2				0x00000002
630 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK		0xffffffff
631 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT		0
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)632 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
633 {
634 	return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
635 }
636 
637 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0			0x00000000
638 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK		0x0000003f
639 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)640 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
641 {
642 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
643 }
644 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK	0x000000c0
645 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT	6
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)646 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
647 {
648 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
649 }
650 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK		0x00000300
651 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT		8
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)652 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
653 {
654 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
655 }
656 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
657 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT		10
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)658 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
659 {
660 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
661 }
662 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK		0x01f00000
663 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT		20
A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)664 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
665 {
666 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
667 }
668 
669 
670 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
671 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK		0xffffffff
672 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)673 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
674 {
675 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
676 }
677 
678 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
679 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK		0xffffffff
680 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)681 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
682 {
683 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
684 }
685 
686 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
687 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK		0xffffffff
688 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT		0
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)689 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
690 {
691 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
692 }
693 
694 
695 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
696 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK		0xffffffff
697 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT	0
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)698 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
699 {
700 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
701 }
702 
703 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
704 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK		0xffffffff
705 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT	0
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)706 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
707 {
708 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
709 }
710 
711 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
712 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK		0xffffffff
713 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)714 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
715 {
716 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
717 }
718 
719 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4			0x00000004
720 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK		0xffffffff
721 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)722 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
723 {
724 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
725 }
726 
727 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5			0x00000005
728 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK		0xffffffff
729 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT		0
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)730 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
731 {
732 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
733 }
734 
REG_CP_SET_DRAW_STATE_(uint32_t i0)735 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
736 
REG_CP_SET_DRAW_STATE__0(uint32_t i0)737 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
738 #define CP_SET_DRAW_STATE__0_COUNT__MASK			0x0000ffff
739 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT			0
CP_SET_DRAW_STATE__0_COUNT(uint32_t val)740 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
741 {
742 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
743 }
744 #define CP_SET_DRAW_STATE__0_DIRTY				0x00010000
745 #define CP_SET_DRAW_STATE__0_DISABLE				0x00020000
746 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS			0x00040000
747 #define CP_SET_DRAW_STATE__0_LOAD_IMMED				0x00080000
748 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK			0x1f000000
749 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT			24
CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)750 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
751 {
752 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
753 }
754 
REG_CP_SET_DRAW_STATE__1(uint32_t i0)755 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
756 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK			0xffffffff
757 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT			0
CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)758 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
759 {
760 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
761 }
762 
REG_CP_SET_DRAW_STATE__2(uint32_t i0)763 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
764 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK			0xffffffff
765 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT			0
CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)766 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
767 {
768 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
769 }
770 
771 #define REG_CP_SET_BIN_0					0x00000000
772 
773 #define REG_CP_SET_BIN_1					0x00000001
774 #define CP_SET_BIN_1_X1__MASK					0x0000ffff
775 #define CP_SET_BIN_1_X1__SHIFT					0
CP_SET_BIN_1_X1(uint32_t val)776 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
777 {
778 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
779 }
780 #define CP_SET_BIN_1_Y1__MASK					0xffff0000
781 #define CP_SET_BIN_1_Y1__SHIFT					16
CP_SET_BIN_1_Y1(uint32_t val)782 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
783 {
784 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
785 }
786 
787 #define REG_CP_SET_BIN_2					0x00000002
788 #define CP_SET_BIN_2_X2__MASK					0x0000ffff
789 #define CP_SET_BIN_2_X2__SHIFT					0
CP_SET_BIN_2_X2(uint32_t val)790 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
791 {
792 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
793 }
794 #define CP_SET_BIN_2_Y2__MASK					0xffff0000
795 #define CP_SET_BIN_2_Y2__SHIFT					16
CP_SET_BIN_2_Y2(uint32_t val)796 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
797 {
798 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
799 }
800 
801 #define REG_CP_SET_BIN_DATA_0					0x00000000
802 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK			0xffffffff
803 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT			0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)804 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
805 {
806 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
807 }
808 
809 #define REG_CP_SET_BIN_DATA_1					0x00000001
810 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK		0xffffffff
811 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT		0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)812 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
813 {
814 	return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
815 }
816 
817 #define REG_CP_SET_BIN_DATA5_0					0x00000000
818 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK			0x003f0000
819 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT			16
CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)820 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
821 {
822 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
823 }
824 #define CP_SET_BIN_DATA5_0_VSC_N__MASK				0x07c00000
825 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT				22
CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)826 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
827 {
828 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
829 }
830 
831 #define REG_CP_SET_BIN_DATA5_1					0x00000001
832 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK		0xffffffff
833 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT		0
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)834 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
835 {
836 	return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
837 }
838 
839 #define REG_CP_SET_BIN_DATA5_2					0x00000002
840 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK		0xffffffff
841 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT		0
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)842 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
843 {
844 	return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
845 }
846 
847 #define REG_CP_SET_BIN_DATA5_3					0x00000003
848 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK		0xffffffff
849 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT		0
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)850 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
851 {
852 	return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
853 }
854 
855 #define REG_CP_SET_BIN_DATA5_4					0x00000004
856 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK		0xffffffff
857 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT		0
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)858 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
859 {
860 	return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
861 }
862 
863 #define REG_CP_REG_TO_MEM_0					0x00000000
864 #define CP_REG_TO_MEM_0_REG__MASK				0x0000ffff
865 #define CP_REG_TO_MEM_0_REG__SHIFT				0
CP_REG_TO_MEM_0_REG(uint32_t val)866 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
867 {
868 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
869 }
870 #define CP_REG_TO_MEM_0_CNT__MASK				0x3ff80000
871 #define CP_REG_TO_MEM_0_CNT__SHIFT				19
CP_REG_TO_MEM_0_CNT(uint32_t val)872 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
873 {
874 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
875 }
876 #define CP_REG_TO_MEM_0_64B					0x40000000
877 #define CP_REG_TO_MEM_0_ACCUMULATE				0x80000000
878 
879 #define REG_CP_REG_TO_MEM_1					0x00000001
880 #define CP_REG_TO_MEM_1_DEST__MASK				0xffffffff
881 #define CP_REG_TO_MEM_1_DEST__SHIFT				0
CP_REG_TO_MEM_1_DEST(uint32_t val)882 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
883 {
884 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
885 }
886 
887 #define REG_CP_MEM_TO_MEM_0					0x00000000
888 #define CP_MEM_TO_MEM_0_NEG_A					0x00000001
889 #define CP_MEM_TO_MEM_0_NEG_B					0x00000002
890 #define CP_MEM_TO_MEM_0_NEG_C					0x00000004
891 #define CP_MEM_TO_MEM_0_DOUBLE					0x20000000
892 
893 #define REG_CP_COND_WRITE_0					0x00000000
894 #define CP_COND_WRITE_0_FUNCTION__MASK				0x00000007
895 #define CP_COND_WRITE_0_FUNCTION__SHIFT				0
CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)896 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
897 {
898 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
899 }
900 #define CP_COND_WRITE_0_POLL_MEMORY				0x00000010
901 #define CP_COND_WRITE_0_WRITE_MEMORY				0x00000100
902 
903 #define REG_CP_COND_WRITE_1					0x00000001
904 #define CP_COND_WRITE_1_POLL_ADDR__MASK				0xffffffff
905 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT			0
CP_COND_WRITE_1_POLL_ADDR(uint32_t val)906 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
907 {
908 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
909 }
910 
911 #define REG_CP_COND_WRITE_2					0x00000002
912 #define CP_COND_WRITE_2_REF__MASK				0xffffffff
913 #define CP_COND_WRITE_2_REF__SHIFT				0
CP_COND_WRITE_2_REF(uint32_t val)914 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
915 {
916 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
917 }
918 
919 #define REG_CP_COND_WRITE_3					0x00000003
920 #define CP_COND_WRITE_3_MASK__MASK				0xffffffff
921 #define CP_COND_WRITE_3_MASK__SHIFT				0
CP_COND_WRITE_3_MASK(uint32_t val)922 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
923 {
924 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
925 }
926 
927 #define REG_CP_COND_WRITE_4					0x00000004
928 #define CP_COND_WRITE_4_WRITE_ADDR__MASK			0xffffffff
929 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT			0
CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)930 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
931 {
932 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
933 }
934 
935 #define REG_CP_COND_WRITE_5					0x00000005
936 #define CP_COND_WRITE_5_WRITE_DATA__MASK			0xffffffff
937 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT			0
CP_COND_WRITE_5_WRITE_DATA(uint32_t val)938 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
939 {
940 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
941 }
942 
943 #define REG_CP_COND_WRITE5_0					0x00000000
944 #define CP_COND_WRITE5_0_FUNCTION__MASK				0x00000007
945 #define CP_COND_WRITE5_0_FUNCTION__SHIFT			0
CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)946 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
947 {
948 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
949 }
950 #define CP_COND_WRITE5_0_POLL_MEMORY				0x00000010
951 #define CP_COND_WRITE5_0_WRITE_MEMORY				0x00000100
952 
953 #define REG_CP_COND_WRITE5_1					0x00000001
954 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK			0xffffffff
955 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT			0
CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)956 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
957 {
958 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
959 }
960 
961 #define REG_CP_COND_WRITE5_2					0x00000002
962 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK			0xffffffff
963 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT			0
CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)964 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
965 {
966 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
967 }
968 
969 #define REG_CP_COND_WRITE5_3					0x00000003
970 #define CP_COND_WRITE5_3_REF__MASK				0xffffffff
971 #define CP_COND_WRITE5_3_REF__SHIFT				0
CP_COND_WRITE5_3_REF(uint32_t val)972 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
973 {
974 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
975 }
976 
977 #define REG_CP_COND_WRITE5_4					0x00000004
978 #define CP_COND_WRITE5_4_MASK__MASK				0xffffffff
979 #define CP_COND_WRITE5_4_MASK__SHIFT				0
CP_COND_WRITE5_4_MASK(uint32_t val)980 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
981 {
982 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
983 }
984 
985 #define REG_CP_COND_WRITE5_5					0x00000005
986 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK			0xffffffff
987 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT			0
CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)988 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
989 {
990 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
991 }
992 
993 #define REG_CP_COND_WRITE5_6					0x00000006
994 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK			0xffffffff
995 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT			0
CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)996 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
997 {
998 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
999 }
1000 
1001 #define REG_CP_COND_WRITE5_7					0x00000007
1002 #define CP_COND_WRITE5_7_WRITE_DATA__MASK			0xffffffff
1003 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT			0
CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)1004 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1005 {
1006 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1007 }
1008 
1009 #define REG_CP_DISPATCH_COMPUTE_0				0x00000000
1010 
1011 #define REG_CP_DISPATCH_COMPUTE_1				0x00000001
1012 #define CP_DISPATCH_COMPUTE_1_X__MASK				0xffffffff
1013 #define CP_DISPATCH_COMPUTE_1_X__SHIFT				0
CP_DISPATCH_COMPUTE_1_X(uint32_t val)1014 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1015 {
1016 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1017 }
1018 
1019 #define REG_CP_DISPATCH_COMPUTE_2				0x00000002
1020 #define CP_DISPATCH_COMPUTE_2_Y__MASK				0xffffffff
1021 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT				0
CP_DISPATCH_COMPUTE_2_Y(uint32_t val)1022 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1023 {
1024 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1025 }
1026 
1027 #define REG_CP_DISPATCH_COMPUTE_3				0x00000003
1028 #define CP_DISPATCH_COMPUTE_3_Z__MASK				0xffffffff
1029 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT				0
CP_DISPATCH_COMPUTE_3_Z(uint32_t val)1030 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1031 {
1032 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1033 }
1034 
1035 #define REG_CP_SET_RENDER_MODE_0				0x00000000
1036 #define CP_SET_RENDER_MODE_0_MODE__MASK				0x000001ff
1037 #define CP_SET_RENDER_MODE_0_MODE__SHIFT			0
CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)1038 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1039 {
1040 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1041 }
1042 
1043 #define REG_CP_SET_RENDER_MODE_1				0x00000001
1044 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK			0xffffffff
1045 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT			0
CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)1046 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1047 {
1048 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1049 }
1050 
1051 #define REG_CP_SET_RENDER_MODE_2				0x00000002
1052 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK			0xffffffff
1053 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT			0
CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)1054 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1055 {
1056 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1057 }
1058 
1059 #define REG_CP_SET_RENDER_MODE_3				0x00000003
1060 #define CP_SET_RENDER_MODE_3_VSC_ENABLE				0x00000008
1061 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE			0x00000010
1062 
1063 #define REG_CP_SET_RENDER_MODE_4				0x00000004
1064 
1065 #define REG_CP_SET_RENDER_MODE_5				0x00000005
1066 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK			0xffffffff
1067 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT			0
CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)1068 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1069 {
1070 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1071 }
1072 
1073 #define REG_CP_SET_RENDER_MODE_6				0x00000006
1074 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK			0xffffffff
1075 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT			0
CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)1076 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1077 {
1078 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1079 }
1080 
1081 #define REG_CP_SET_RENDER_MODE_7				0x00000007
1082 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK			0xffffffff
1083 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT			0
CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)1084 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1085 {
1086 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1087 }
1088 
1089 #define REG_CP_COMPUTE_CHECKPOINT_0				0x00000000
1090 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK			0xffffffff
1091 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT		0
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)1092 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1093 {
1094 	return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1095 }
1096 
1097 #define REG_CP_COMPUTE_CHECKPOINT_1				0x00000001
1098 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK			0xffffffff
1099 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT		0
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)1100 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1101 {
1102 	return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1103 }
1104 
1105 #define REG_CP_COMPUTE_CHECKPOINT_2				0x00000002
1106 
1107 #define REG_CP_COMPUTE_CHECKPOINT_3				0x00000003
1108 
1109 #define REG_CP_COMPUTE_CHECKPOINT_4				0x00000004
1110 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK		0xffffffff
1111 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT		0
CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)1112 static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
1113 {
1114 	return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
1115 }
1116 
1117 #define REG_CP_COMPUTE_CHECKPOINT_5				0x00000005
1118 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK			0xffffffff
1119 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT		0
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)1120 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1121 {
1122 	return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1123 }
1124 
1125 #define REG_CP_COMPUTE_CHECKPOINT_6				0x00000006
1126 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK			0xffffffff
1127 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT		0
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)1128 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1129 {
1130 	return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1131 }
1132 
1133 #define REG_CP_PERFCOUNTER_ACTION_0				0x00000000
1134 
1135 #define REG_CP_PERFCOUNTER_ACTION_1				0x00000001
1136 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK			0xffffffff
1137 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT		0
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)1138 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1139 {
1140 	return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1141 }
1142 
1143 #define REG_CP_PERFCOUNTER_ACTION_2				0x00000002
1144 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK			0xffffffff
1145 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT		0
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)1146 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1147 {
1148 	return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1149 }
1150 
1151 #define REG_CP_EVENT_WRITE_0					0x00000000
1152 #define CP_EVENT_WRITE_0_EVENT__MASK				0x000000ff
1153 #define CP_EVENT_WRITE_0_EVENT__SHIFT				0
CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)1154 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1155 {
1156 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1157 }
1158 #define CP_EVENT_WRITE_0_TIMESTAMP				0x40000000
1159 
1160 #define REG_CP_EVENT_WRITE_1					0x00000001
1161 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK			0xffffffff
1162 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT			0
CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)1163 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1164 {
1165 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1166 }
1167 
1168 #define REG_CP_EVENT_WRITE_2					0x00000002
1169 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK			0xffffffff
1170 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT			0
CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)1171 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1172 {
1173 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1174 }
1175 
1176 #define REG_CP_EVENT_WRITE_3					0x00000003
1177 
1178 #define REG_CP_BLIT_0						0x00000000
1179 #define CP_BLIT_0_OP__MASK					0x0000000f
1180 #define CP_BLIT_0_OP__SHIFT					0
CP_BLIT_0_OP(enum cp_blit_cmd val)1181 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1182 {
1183 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1184 }
1185 
1186 #define REG_CP_BLIT_1						0x00000001
1187 #define CP_BLIT_1_SRC_X1__MASK					0x00003fff
1188 #define CP_BLIT_1_SRC_X1__SHIFT					0
CP_BLIT_1_SRC_X1(uint32_t val)1189 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1190 {
1191 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1192 }
1193 #define CP_BLIT_1_SRC_Y1__MASK					0x3fff0000
1194 #define CP_BLIT_1_SRC_Y1__SHIFT					16
CP_BLIT_1_SRC_Y1(uint32_t val)1195 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1196 {
1197 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1198 }
1199 
1200 #define REG_CP_BLIT_2						0x00000002
1201 #define CP_BLIT_2_SRC_X2__MASK					0x00003fff
1202 #define CP_BLIT_2_SRC_X2__SHIFT					0
CP_BLIT_2_SRC_X2(uint32_t val)1203 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1204 {
1205 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1206 }
1207 #define CP_BLIT_2_SRC_Y2__MASK					0x3fff0000
1208 #define CP_BLIT_2_SRC_Y2__SHIFT					16
CP_BLIT_2_SRC_Y2(uint32_t val)1209 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1210 {
1211 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1212 }
1213 
1214 #define REG_CP_BLIT_3						0x00000003
1215 #define CP_BLIT_3_DST_X1__MASK					0x00003fff
1216 #define CP_BLIT_3_DST_X1__SHIFT					0
CP_BLIT_3_DST_X1(uint32_t val)1217 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1218 {
1219 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1220 }
1221 #define CP_BLIT_3_DST_Y1__MASK					0x3fff0000
1222 #define CP_BLIT_3_DST_Y1__SHIFT					16
CP_BLIT_3_DST_Y1(uint32_t val)1223 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1224 {
1225 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1226 }
1227 
1228 #define REG_CP_BLIT_4						0x00000004
1229 #define CP_BLIT_4_DST_X2__MASK					0x00003fff
1230 #define CP_BLIT_4_DST_X2__SHIFT					0
CP_BLIT_4_DST_X2(uint32_t val)1231 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1232 {
1233 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1234 }
1235 #define CP_BLIT_4_DST_Y2__MASK					0x3fff0000
1236 #define CP_BLIT_4_DST_Y2__SHIFT					16
CP_BLIT_4_DST_Y2(uint32_t val)1237 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1238 {
1239 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1240 }
1241 
1242 #define REG_CP_EXEC_CS_0					0x00000000
1243 
1244 #define REG_CP_EXEC_CS_1					0x00000001
1245 #define CP_EXEC_CS_1_NGROUPS_X__MASK				0xffffffff
1246 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT				0
CP_EXEC_CS_1_NGROUPS_X(uint32_t val)1247 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1248 {
1249 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1250 }
1251 
1252 #define REG_CP_EXEC_CS_2					0x00000002
1253 #define CP_EXEC_CS_2_NGROUPS_Y__MASK				0xffffffff
1254 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT				0
CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)1255 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1256 {
1257 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1258 }
1259 
1260 #define REG_CP_EXEC_CS_3					0x00000003
1261 #define CP_EXEC_CS_3_NGROUPS_Z__MASK				0xffffffff
1262 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT				0
CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)1263 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1264 {
1265 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1266 }
1267 
1268 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0				0x00000000
1269 
1270 
1271 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1				0x00000001
1272 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK			0xffffffff
1273 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT			0
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)1274 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1275 {
1276 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1277 }
1278 
1279 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2				0x00000002
1280 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK		0x00000ffc
1281 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT		2
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)1282 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1283 {
1284 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1285 }
1286 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK		0x003ff000
1287 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT		12
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)1288 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1289 {
1290 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1291 }
1292 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK		0xffc00000
1293 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT		22
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)1294 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1295 {
1296 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1297 }
1298 
1299 
1300 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1				0x00000001
1301 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK		0xffffffff
1302 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT		0
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)1303 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1304 {
1305 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1306 }
1307 
1308 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2				0x00000002
1309 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK		0xffffffff
1310 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT		0
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)1311 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1312 {
1313 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1314 }
1315 
1316 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3				0x00000003
1317 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK		0x00000ffc
1318 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT		2
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)1319 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1320 {
1321 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1322 }
1323 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK		0x003ff000
1324 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT		12
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)1325 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1326 {
1327 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1328 }
1329 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK		0xffc00000
1330 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT		22
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)1331 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1332 {
1333 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1334 }
1335 
1336 
1337 #endif /* ADRENO_PM4_XML */
1338