| /external/compiler-rt/test/asan/TestCases/Linux/ |
| D | sized_delete_test.cc | 25 struct D1 { struct
27 ~D1() { fprintf(stderr, "D1::~D1\n"); } in ~D1() argument
|
| /external/clang/test/SemaTemplate/ |
| D | elaborated-type-specifier.cpp | 10 struct D1 { struct
11 enum X { value };
|
| D | class-template-id-2.cpp | 16 struct D1 { struct
|
| /external/clang/test/CXX/special/class.init/class.inhctor.init/ |
| D | p1.cpp | 14 struct D1 : B1 { // expected-note {{no default constructor}} struct
16 int x;
17 int y = get();
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| D | p2.cpp | 10 struct D1 : C1, C2 { struct
|
| /external/clang/test/CodeGenCXX/ |
| D | homogeneous-aggregates.cpp | 23 struct D1 : Base1 { // non-homogeneous aggregate struct
41 // PPC: define void @_Z7func_D12D1(%struct.D1* noalias sret %agg.result, [3 x i64] %x.coerce) argument
|
| /external/clang/test/Misc/ |
| D | diag-line-wrapping.cpp | 5 struct D1 : B {}; struct
|
| /external/eigen/bench/tensors/ |
| D | contraction_benchmarks_cpu.cc | 14 #define BM_ContractionCPU(D1, D2, D3) \ argument
|
| D | tensor_benchmarks_fp16_gpu.cu | 40 #define BM_FuncWithInputDimsGPU(FUNC, D1, D2, D3) \ argument
|
| D | tensor_benchmarks_gpu.cu | 40 #define BM_FuncWithInputDimsGPU(FUNC, D1, D2, D3) \ argument
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| D | tensor_benchmarks_cpu.cc | 83 #define BM_FuncWithInputDimsCPU(FUNC, D1, D2, D3, THREADS) \ argument
|
| /external/mesa3d/src/compiler/glsl/glcpp/tests/ |
| D | 067-nested-ifdef-ifndef.c | 1 #define D1 macro
|
| /external/libcxx/test/std/utilities/time/time.duration/time.duration.arithmetic/ |
| D | op_+.pass.cpp | 39 typedef std::chrono::duration<int, std::ratio< 1, 1> > D1; in main() typedef
|
| D | op_-.pass.cpp | 39 typedef std::chrono::duration<int, std::ratio< 1, 1> > D1; in main() typedef
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 386 unsigned &D1, unsigned &D2, unsigned &D3) { in GetDSubRegs()
423 unsigned D0, D1, D2, D3; in ExpandVLD() local
496 unsigned D0, D1, D2, D3; in ExpandVST() local
545 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; in ExpandLaneOp() local
622 unsigned D0, D1, D2, D3; in ExpandVTBL() local
992 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI() local
1022 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI() local
|
| /external/clang/test/CXX/special/class.inhctor/ |
| D | p7.cpp | 12 struct D1 : B1, B2 { // expected-note 2{{candidate}} struct
|
| D | elsewhere.cpp | 29 struct D1 : I1 { struct
|
| /external/webp/src/dsp/ |
| D | rescaler_neon.c | 56 const uint64x2_t D1 = vmlal_n_u32(C1, vget_high_u32(B0), B); in Interpolate_NEON() local
101 const uint32x4_t D1 = MULT_FIX(C1, fy_scale_half); in RescalerExportRowExpand_NEON() local
143 const uint16x4_t D1 = vmovn_u32(C1); in RescalerExportRowShrink_NEON() local
|
| /external/clang/test/CodeGen/ |
| D | mips64-class-return.cpp | 14 class D1 : public B1 { class
|
| /external/clang/test/CXX/dcl.dcl/basic.namespace/namespace.udecl/ |
| D | p15.cpp | 11 struct D1 : B1, B2 { // expected-note 2{{candidate}} struct
|
| /external/libcxx/test/std/utilities/memory/pointer.traits/pointer.traits.types/ |
| D | rebind.pass.cpp | 46 template <class T, class U> struct D1 {}; struct
|
| /external/clang/test/CXX/class.derived/class.member.lookup/ |
| D | p8.cpp | 12 struct D1 : public Base {}; struct
|
| /external/clang/test/Sema/ |
| D | ms_bitfield_layout.c | 216 typedef struct D1 { struct
221 } D1; argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 438 unsigned &D1, unsigned &D2, unsigned &D3) { in GetDSubRegs()
500 unsigned D0, D1, D2, D3; in ExpandVLD() local
627 unsigned D0, D1, D2, D3; in ExpandVST() local
680 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; in ExpandLaneOp() local
761 unsigned D0, D1, D2, D3; in ExpandVTBL() local
1592 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI() local
1624 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 370 unsigned &D1, unsigned &D2, unsigned &D3) { in GetDSubRegs()
407 unsigned D0, D1, D2, D3; in ExpandVLD() local
482 unsigned D0, D1, D2, D3; in ExpandVST() local
535 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; in ExpandLaneOp() local
614 unsigned D0, D1, D2, D3; in ExpandVTBL() local
1398 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI() local
1429 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI() local
|