• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /** @file
2 *
3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 *  This program and the accompanying materials
6 *  are licensed and made available under the terms and conditions of the BSD License
7 *  which accompanies this distribution.  The full text of the license may be found at
8 *  http://opensource.org/licenses/bsd-license.php
9 *
10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14 
15 #ifndef _PL341DMC_H_
16 #define _PL341DMC_H_
17 
18 
19 typedef struct  {
20     UINTN   HasQos;        // has QoS registers
21     UINTN   MaxChip;       // number of memory chips accessible
22     BOOLEAN IsUserCfg;
23     UINT32  User0Cfg;
24     UINT32  User2Cfg;
25     UINT32  RefreshPeriod;
26     UINT32  CasLatency;
27     UINT32  WriteLatency;
28     UINT32  t_mrd;
29     UINT32  t_ras;
30     UINT32  t_rc;
31     UINT32  t_rcd;
32     UINT32  t_rfc;
33     UINT32  t_rp;
34     UINT32  t_rrd;
35     UINT32  t_wr;
36     UINT32  t_wtr;
37     UINT32  t_xp;
38     UINT32  t_xsr;
39     UINT32  t_esr;
40     UINT32  MemoryCfg;
41     UINT32  MemoryCfg2;
42     UINT32  MemoryCfg3;
43     UINT32  ChipCfg0;
44     UINT32  ChipCfg1;
45     UINT32  ChipCfg2;
46     UINT32  ChipCfg3;
47     UINT32  t_faw;
48     UINT32  t_data_en;
49     UINT32  t_wdata_en;
50     UINT32  ModeReg;
51     UINT32  ExtModeReg;
52 } PL341_DMC_CONFIG;
53 
54 /* Memory config bit fields */
55 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1
56 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2
57 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3
58 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4
59 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)
60 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)
61 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)
62 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)
63 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)
64 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)
65 #define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)
66 #define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)
67 #define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)
68 #define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)
69 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1    (0x0 << 21)
70 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2    (0x1 << 21)
71 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3    (0x2 << 21)
72 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4    (0x3 << 21)
73 
74 #define DMC_MEMORY_CFG2_CLK_ASYNC    (0x0 << 0)
75 #define DMC_MEMORY_CFG2_CLK_SYNC    (0x1 << 0)
76 #define DMC_MEMORY_CFG2_DQM_INIT    (0x1 << 2)
77 #define DMC_MEMORY_CFG2_CKE_INIT    (0x1 << 3)
78 #define DMC_MEMORY_CFG2_BANK_BITS_2    (0x0 << 4)
79 #define DMC_MEMORY_CFG2_BANK_BITS_3    (0x3 << 4)
80 #define DMC_MEMORY_CFG2_MEM_WIDTH_16    (0x0 << 6)
81 #define DMC_MEMORY_CFG2_MEM_WIDTH_32    (0x1 << 6)
82 #define DMC_MEMORY_CFG2_MEM_WIDTH_64    (0x2 << 6)
83 #define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED  (0x3 << 6)
84 
85 //
86 // DMC Configuration Register Map
87 //
88 #define DMC_STATUS_REG              0x00
89 #define DMC_COMMAND_REG             0x04
90 #define DMC_DIRECT_CMD_REG          0x08
91 #define DMC_MEMORY_CONFIG_REG       0x0C
92 #define DMC_REFRESH_PRD_REG         0x10
93 #define DMC_CAS_LATENCY_REG         0x14
94 #define DMC_WRITE_LATENCY_REG       0x18
95 #define DMC_T_MRD_REG               0x1C
96 #define DMC_T_RAS_REG               0x20
97 #define DMC_T_RC_REG                0x24
98 #define DMC_T_RCD_REG               0x28
99 #define DMC_T_RFC_REG               0x2C
100 #define DMC_T_RP_REG                0x30
101 #define DMC_T_RRD_REG               0x34
102 #define DMC_T_WR_REG                0x38
103 #define DMC_T_WTR_REG               0x3C
104 #define DMC_T_XP_REG                0x40
105 #define DMC_T_XSR_REG               0x44
106 #define DMC_T_ESR_REG               0x48
107 #define DMC_MEMORY_CFG2_REG         0x4C
108 #define DMC_MEMORY_CFG3_REG         0x50
109 #define DMC_T_FAW_REG               0x54
110 #define DMC_T_RDATA_EN              0x5C        /* DFI read data enable register */
111 #define DMC_T_WRLAT_DIFF            0x60        /* DFI write data enable register */
112 
113 // Returns the state of the memory controller:
114 #define DMC_STATUS_CONFIG       0x0
115 #define DMC_STATUS_READY        0x1
116 #define DMC_STATUS_PAUSED       0x2
117 #define DMC_STATUS_LOWPOWER     0x3
118 
119 // Changes the state of the memory controller:
120 #define DMC_COMMAND_GO              0x0
121 #define DMC_COMMAND_SLEEP           0x1
122 #define DMC_COMMAND_WAKEUP          0x2
123 #define DMC_COMMAND_PAUSE           0x3
124 #define DMC_COMMAND_CONFIGURE       0x4
125 #define DMC_COMMAND_ACTIVEPAUSE     0x7
126 
127 // Determines the command required
128 #define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL      0x0
129 #define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH       (0x1 << 18)
130 #define DMC_DIRECT_CMD_MEMCMD_MODEREG           (0x2 << 18)
131 #define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG        (0x2 << 18)
132 #define DMC_DIRECT_CMD_MEMCMD_NOP               (0x3 << 18)
133 #define DMC_DIRECT_CMD_MEMCMD_DPD               (0x1 << 22)
134 #define DMC_DIRECT_CMD_BANKADDR(n)              ((n & 0x3) << 16)
135 #define DMC_DIRECT_CMD_CHIP_ADDR(n)             ((n & 0x3) << 20)
136 
137 
138 //
139 // AXI ID configuration register map
140 //
141 #define DMC_ID_0_CFG_REG            0x100
142 #define DMC_ID_1_CFG_REG            0x104
143 #define DMC_ID_2_CFG_REG            0x108
144 #define DMC_ID_3_CFG_REG            0x10C
145 #define DMC_ID_4_CFG_REG            0x110
146 #define DMC_ID_5_CFG_REG            0x114
147 #define DMC_ID_6_CFG_REG            0x118
148 #define DMC_ID_7_CFG_REG            0x11C
149 #define DMC_ID_8_CFG_REG            0x120
150 #define DMC_ID_9_CFG_REG            0x124
151 #define DMC_ID_10_CFG_REG           0x128
152 #define DMC_ID_11_CFG_REG           0x12C
153 #define DMC_ID_12_CFG_REG           0x130
154 #define DMC_ID_13_CFG_REG           0x134
155 #define DMC_ID_14_CFG_REG           0x138
156 #define DMC_ID_15_CFG_REG           0x13C
157 
158 // Set the QoS
159 #define DMC_ID_CFG_QOS_DISABLE      0
160 #define DMC_ID_CFG_QOS_ENABLE       1
161 #define DMC_ID_CFG_QOS_MIN          2
162 
163 
164 //
165 // Chip configuration register map
166 //
167 #define DMC_CHIP_0_CFG_REG          0x200
168 #define DMC_CHIP_1_CFG_REG          0x204
169 #define DMC_CHIP_2_CFG_REG          0x208
170 #define DMC_CHIP_3_CFG_REG          0x20C
171 
172 //
173 // User Defined Pins
174 //
175 #define DMC_USER_STATUS_REG         0x300
176 #define DMC_USER_0_CFG_REG          0x304
177 #define DMC_USER_1_CFG_REG          0x308
178 #define DMC_FEATURE_CRTL_REG        0x30C
179 #define DMC_USER_2_CFG_REG          0x310
180 
181 
182 //
183 // PHY Register Settings
184 //
185 #define PHY_PTM_DFI_CLK_RANGE       0xE00  // DDR2 PHY PTM register offset
186 #define PHY_PTM_IOTERM              0xE04
187 #define PHY_PTM_PLL_EN              0xe0c
188 #define PHY_PTM_PLL_RANGE           0xe18
189 #define PHY_PTM_FEEBACK_DIV         0xe1c
190 #define PHY_PTM_RCLK_DIV            0xe20
191 #define PHY_PTM_LOCK_STATUS         0xe28
192 #define PHY_PTM_INIT_DONE           0xe34
193 #define PHY_PTM_ADDCOM_IOSTR_OFF    0xec8
194 #define PHY_PTM_SQU_TRAINING        0xee8
195 #define PHY_PTM_SQU_STAT            0xeec
196 
197 // ==============================================================================
198 // PIPD 40G DDR2/DDR3 PHY Register definitions
199 //
200 // Offsets from APB Base Address
201 // ==============================================================================
202 #define PHY_BYTE0_OFFSET            0x000
203 #define PHY_BYTE1_OFFSET            0x200
204 #define PHY_BYTE2_OFFSET            0x400
205 #define PHY_BYTE3_OFFSET            0x600
206 
207 #define PHY_BYTE0_COARSE_SQADJ_INIT 0x064  ;// Coarse squelch adjust
208 #define PHY_BYTE1_COARSE_SQADJ_INIT 0x264  ;// Coarse squelch adjust
209 #define PHY_BYTE2_COARSE_SQADJ_INIT 0x464  ;// Coarse squelch adjust
210 #define PHY_BYTE3_COARSE_SQADJ_INIT 0x664  ;// Coarse squelch adjust
211 
212 #define PHY_BYTE0_IOSTR_OFFSET      0x004
213 #define PHY_BYTE1_IOSTR_OFFSET      0x204
214 #define PHY_BYTE2_IOSTR_OFFSET      0x404
215 #define PHY_BYTE3_IOSTR_OFFSET      0x604
216 
217 
218 ;//--------------------------------------------------------------------------
219 
220 // DFI Clock ranges:
221 
222 #define PHY_PTM_DFI_CLK_RANGE_200MHz            0x0
223 #define PHY_PTM_DFI_CLK_RANGE_201_267MHz        0x1
224 #define PHY_PTM_DFI_CLK_RANGE_268_333MHz        0x2
225 #define PHY_PTM_DFI_CLK_RANGE_334_400MHz        0x3
226 #define PHY_PTM_DFI_CLK_RANGE_401_533MHz        0x4
227 #define PHY_PTM_DFI_CLK_RANGE_534_667MHz        0x5
228 #define PHY_PTM_DFI_CLK_RANGE_668_800MHz        0x6
229 
230 
231 
232 #define  PHY_PTM_DFI_CLK_RANGE_VAL              PHY_PTM_DFI_CLK_RANGE_334_400MHz
233 
234 //--------------------------------------------------------------------------
235 
236 
237 // PLL Range
238 
239 #define PHY_PTM_PLL_RANGE_200_400MHz            0x0     // b0 = frequency >= 200 MHz and < 400 MHz
240 #define PHY_PTM_PLL_RANGE_400_800MHz            0x1     // b1 = frequency >= 400 MHz.
241 #define PHY_PTM_FEEBACK_DIV_200_400MHz          0x0     // b0 = frequency >= 200 MHz and < 400 MHz
242 #define PHY_PTM_FEEBACK_DIV_400_800MHz          0x1     // b1 = frequency >= 400 MHz.
243 #define PHY_PTM_REFCLK_DIV_200_400MHz           0x0
244 #define PHY_PTM_REFCLK_DIV_400_800MHz           0x1
245 
246 #define TC_UIOLHNC_MASK                         0x000003C0
247 #define TC_UIOLHNC_SHIFT                        0x6
248 #define TC_UIOLHPC_MASK                         0x0000003F
249 #define TC_UIOLHPC_SHIFT                        0x2
250 #define TC_UIOHOCT_MASK                         0x2
251 #define TC_UIOHOCT_SHIFT                        0x1
252 #define TC_UIOHSTOP_SHIFT                       0x0
253 #define TC_UIOLHXC_VALUE                        0x4
254 
255 #define PHY_PTM_SQU_TRAINING_ENABLE             0x1
256 #define PHY_PTM_SQU_TRAINING_DISABLE            0x0
257 
258 
259 //--------------------------------------
260 // JEDEC DDR2 Device Register definitions and settings
261 //--------------------------------------
262 #define DDR_MODESET_SHFT                        14
263 #define DDR_MODESET_MR                          0x0  ;// Mode register
264 #define DDR_MODESET_EMR                         0x1  ;// Extended Mode register
265 #define DDR_MODESET_EMR2                        0x2
266 #define DDR_MODESET_EMR3                        0x3
267 
268 //
269 // Extended Mode Register settings
270 //
271 #define DDR_EMR_OCD_MASK                        0x0000380
272 #define DDR_EMR_OCD_SHIFT                       0x7
273 #define DDR_EMR_RTT_MASK                        0x00000044                  // DDR2 Device RTT (ODT) settings
274 #define DDR_EMR_RTT_SHIFT                       0x2
275 #define DDR_EMR_ODS_MASK                        0x00000002                  // DDR2 Output Drive Strength
276 #define DDR_EMR_ODS_SHIFT                       0x0001
277 
278 // Termination Values:
279 #define DDR_EMR_RTT_50R                         0x00000044                  // DDR2 50 Ohm termination
280 #define DDR_EMR_RTT_75R                         0x00000004                  // DDR2 75 Ohm termination
281 #define DDR_EMR_RTT_150                         0x00000040                  // DDR2 150 Ohm termination
282 
283 // Output Drive Strength Values:
284 #define DDR_EMR_ODS_FULL                        0x0                         // DDR2 Full Drive Strength
285 #define DDR_EMR_ODS_HALF                        0x1                         // DDR2 Half Drive Strength
286 
287 // OCD values
288 #define DDR_EMR_OCD_DEFAULT                     0x7
289 #define DDR_EMR_OCD_NS                          0x0
290 
291 #define DDR_EMR_ODS_VAL                         DDR_EMR_ODS_FULL
292 
293 #define DDR_SDRAM_START_ADDR                    0x10000000
294 
295 
296 // ----------------------------------------
297 // PHY IOTERM values
298 // ----------------------------------------
299 #define PHY_PTM_IOTERM_OFF                      0x0
300 #define PHY_PTM_IOTERM_150R                     0x1
301 #define PHY_PTM_IOTERM_75R                      0x2
302 #define PHY_PTM_IOTERM_50R                      0x3
303 
304 #define PHY_BYTE_IOSTR_60OHM                    0x0
305 #define PHY_BYTE_IOSTR_40OHM                    0x1
306 #define PHY_BYTE_IOSTR_30OHM                    0x2
307 #define PHY_BYTE_IOSTR_30AOHM                   0x3
308 
309 #define DDR2_MR_BURST_LENGTH_4     (2)
310 #define DDR2_MR_BURST_LENGTH_8     (3)
311 #define DDR2_MR_DLL_RESET          (1 << 8)
312 #define DDR2_MR_CAS_LATENCY_4      (4 << 4)
313 #define DDR2_MR_CAS_LATENCY_5      (5 << 4)
314 #define DDR2_MR_CAS_LATENCY_6      (6 << 4)
315 #define DDR2_MR_WR_CYCLES_2        (1 << 9)
316 #define DDR2_MR_WR_CYCLES_3        (2 << 9)
317 #define DDR2_MR_WR_CYCLES_4        (3 << 9)
318 #define DDR2_MR_WR_CYCLES_5        (4 << 9)
319 #define DDR2_MR_WR_CYCLES_6        (5 << 9)
320 
321 
322 VOID
323 PL341DmcInit (
324   IN  UINTN             DmcBase,
325   IN  PL341_DMC_CONFIG* DmcConfig
326   );
327 
328 VOID PL341DmcPhyInit (
329   IN UINTN   DmcPhyBase
330   );
331 
332 VOID PL341DmcTrainPHY (
333   IN UINTN   DmcPhyBase
334   );
335 
336 #endif /* _PL341DMC_H_ */
337