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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2007-2012
4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5  * Berg Xing <bergxing@allwinnertech.com>
6  * Tom Cubie <tangliang@allwinnertech.com>
7  *
8  * Sunxi platform dram register definition.
9  */
10 
11 #ifndef _SUNXI_DRAM_SUN4I_H
12 #define _SUNXI_DRAM_SUN4I_H
13 
14 struct sunxi_dram_reg {
15 	u32 ccr;		/* 0x00 controller configuration register */
16 	u32 dcr;		/* 0x04 dram configuration register */
17 	u32 iocr;		/* 0x08 i/o configuration register */
18 	u32 csr;		/* 0x0c controller status register */
19 	u32 drr;		/* 0x10 dram refresh register */
20 	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
21 	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
22 	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
23 	u32 gdllcr;		/* 0x20 global dll control register */
24 	u8 res0[0x28];
25 	u32 rslr0;		/* 0x4c rank system latency register */
26 	u32 rslr1;		/* 0x50 rank system latency register */
27 	u8 res1[0x8];
28 	u32 rdgr0;		/* 0x5c rank dqs gating register */
29 	u32 rdgr1;		/* 0x60 rank dqs gating register */
30 	u8 res2[0x34];
31 	u32 odtcr;		/* 0x98 odt configuration register */
32 	u32 dtr0;		/* 0x9c data training register 0 */
33 	u32 dtr1;		/* 0xa0 data training register 1 */
34 	u32 dtar;		/* 0xa4 data training address register */
35 	u32 zqcr0;		/* 0xa8 zq control register 0 */
36 	u32 zqcr1;		/* 0xac zq control register 1 */
37 	u32 zqsr;		/* 0xb0 zq status register */
38 	u32 idcr;		/* 0xb4 initializaton delay configure reg */
39 	u8 res3[0x138];
40 	u32 mr;			/* 0x1f0 mode register */
41 	u32 emr;		/* 0x1f4 extended mode register */
42 	u32 emr2;		/* 0x1f8 extended mode register */
43 	u32 emr3;		/* 0x1fc extended mode register */
44 	u32 dllctr;		/* 0x200 dll control register */
45 	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
46 	/* 0x208 dll control register 1(byte 1) */
47 	/* 0x20c dll control register 2(byte 2) */
48 	/* 0x210 dll control register 3(byte 3) */
49 	/* 0x214 dll control register 4(byte 4) */
50 	u32 dqtr0;		/* 0x218 dq timing register */
51 	u32 dqtr1;		/* 0x21c dq timing register */
52 	u32 dqtr2;		/* 0x220 dq timing register */
53 	u32 dqtr3;		/* 0x224 dq timing register */
54 	u32 dqstr;		/* 0x228 dqs timing register */
55 	u32 dqsbtr;		/* 0x22c dqsb timing register */
56 	u32 mcr;		/* 0x230 mode configure register */
57 	u8 res[0x8];
58 	u32 ppwrsctl;		/* 0x23c pad power save control */
59 	u32 apr;		/* 0x240 arbiter period register */
60 	u32 pldtr;		/* 0x244 priority level data threshold reg */
61 	u8 res5[0x8];
62 	u32 hpcr[32];		/* 0x250 host port configure register */
63 	u8 res6[0x10];
64 	u32 csel;		/* 0x2e0 controller select register */
65 };
66 
67 struct dram_para {
68 	u32 clock;
69 	u32 mbus_clock;
70 	u32 type;
71 	u32 rank_num;
72 	u32 density;
73 	u32 io_width;
74 	u32 bus_width;
75 	u32 cas;
76 	u32 zq;
77 	u32 odt_en;
78 	u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */
79 	u32 tpr0;
80 	u32 tpr1;
81 	u32 tpr2;
82 	u32 tpr3;
83 	u32 tpr4;
84 	u32 tpr5;
85 	u32 emr1;
86 	u32 emr2;
87 	u32 emr3;
88 	u32 dqs_gating_delay;
89 	u32 active_windowing;
90 };
91 
92 #define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
93 #define DRAM_CCR_DQS_GATE (0x1 << 14)
94 #define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
95 #define DRAM_CCR_ITM_OFF (0x1 << 28)
96 #define DRAM_CCR_DATA_TRAINING (0x1 << 30)
97 #define DRAM_CCR_INIT (0x1 << 31)
98 
99 #define DRAM_MEMORY_TYPE_DDR1 1
100 #define DRAM_MEMORY_TYPE_DDR2 2
101 #define DRAM_MEMORY_TYPE_DDR3 3
102 #define DRAM_MEMORY_TYPE_LPDDR2 4
103 #define DRAM_MEMORY_TYPE_LPDDR 5
104 #define DRAM_DCR_TYPE (0x1 << 0)
105 #define DRAM_DCR_TYPE_DDR2 0x0
106 #define DRAM_DCR_TYPE_DDR3 0x1
107 #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
108 #define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
109 #define DRAM_DCR_IO_WIDTH_8BIT 0x0
110 #define DRAM_DCR_IO_WIDTH_16BIT 0x1
111 #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
112 #define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
113 #define DRAM_DCR_CHIP_DENSITY_256M 0x0
114 #define DRAM_DCR_CHIP_DENSITY_512M 0x1
115 #define DRAM_DCR_CHIP_DENSITY_1024M 0x2
116 #define DRAM_DCR_CHIP_DENSITY_2048M 0x3
117 #define DRAM_DCR_CHIP_DENSITY_4096M 0x4
118 #define DRAM_DCR_CHIP_DENSITY_8192M 0x5
119 #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
120 #define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
121 #define DRAM_DCR_BUS_WIDTH_32BIT 0x3
122 #define DRAM_DCR_BUS_WIDTH_16BIT 0x1
123 #define DRAM_DCR_BUS_WIDTH_8BIT 0x0
124 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
125 #define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
126 #define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
127 #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
128 #define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
129 #define DRAM_DCR_MODE_SEQ 0x0
130 #define DRAM_DCR_MODE_INTERLEAVE 0x1
131 
132 #define DRAM_CSR_DTERR  (0x1 << 20)
133 #define DRAM_CSR_DTIERR (0x1 << 21)
134 #define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
135 
136 #define DRAM_DRR_TRFC(n) ((n) & 0xff)
137 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
138 #define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
139 
140 #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
141 #define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
142 #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
143 #define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
144 #define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
145 #define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
146 #define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
147 #define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
148 #define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
149 #define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
150 #define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
151 #define DRAM_MCR_RESET (0x1 << 12)
152 #define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
153 #define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
154 #define DRAM_MCR_DCLK_OUT (0x1 << 16)
155 
156 #define DRAM_DLLCR_NRESET (0x1 << 30)
157 #define DRAM_DLLCR_DISABLE (0x1 << 31)
158 
159 #define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
160 #define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
161 #define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
162 #define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
163 
164 #define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
165 
166 #define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0))
167 
168 #define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
169 #define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
170 #define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
171 #define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
172 #define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
173 #define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
174 #define DRAM_MR_POWER_DOWN (0x1 << 12)
175 
176 #define DRAM_CSEL_MAGIC 0x16237495
177 
178 unsigned long dramc_init(struct dram_para *para);
179 
180 #endif /* _SUNXI_DRAM_SUN4I_H */
181