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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Auther:
4  *       Vaibhav Hiremath <hvaibhav@ti.com>
5  *
6  * Copyright (C) 2010
7  * Texas Instruments Incorporated - http://www.ti.com/
8  */
9 
10 #ifndef _EMIF_H_
11 #define _EMIF_H_
12 
13 /*
14  * Configuration values
15  */
16 #define EMIF4_TIM1_T_RP		(0x3 << 25)
17 #define EMIF4_TIM1_T_RCD	(0x3 << 21)
18 #define EMIF4_TIM1_T_WR		(0x3 << 17)
19 #define EMIF4_TIM1_T_RAS	(0x8 << 12)
20 #define EMIF4_TIM1_T_RC		(0xA << 6)
21 #define EMIF4_TIM1_T_RRD	(0x2 << 3)
22 #define EMIF4_TIM1_T_WTR	(0x2)
23 
24 #define EMIF4_TIM2_T_XP		(0x2 << 28)
25 #define EMIF4_TIM2_T_ODT	(0x0 << 25)
26 #define EMIF4_TIM2_T_XSNR	(0x1C << 16)
27 #define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
28 #define EMIF4_TIM2_T_RTP	(0x1 << 3)
29 #define EMIF4_TIM2_T_CKE	(0x2)
30 
31 #define EMIF4_TIM3_T_RFC	(0x25 << 4)
32 #define EMIF4_TIM3_T_RAS_MAX	(0x7)
33 
34 #define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
35 #define EMIF4_PWR_DPD_DIS	(0x0 << 10)
36 #define EMIF4_PWR_DPD_EN	(0x1 << 10)
37 #define EMIF4_PWR_LP_MODE	(0x0 << 8)
38 #define EMIF4_PWR_PM_TIM	(0x0)
39 
40 #define EMIF4_INITREF_DIS	(0x0 << 31)
41 #define EMIF4_REFRESH_RATE	(0x50F)
42 
43 #define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
44 #define EMIF4_CFG_IBANK_POS	(0x0 << 27)
45 #define EMIF4_CFG_DDR_TERM	(0x0 << 24)
46 #define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
47 #define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
48 #define EMIF4_CFG_SDR_DRV	(0x0 << 18)
49 #define EMIF4_CFG_NARROW_MD	(0x0 << 14)
50 #define EMIF4_CFG_CL		(0x5 << 10)
51 #define EMIF4_CFG_ROWSIZE	(0x0 << 7)
52 #define EMIF4_CFG_IBANK		(0x3 << 4)
53 #define EMIF4_CFG_EBANK		(0x0 << 3)
54 #define EMIF4_CFG_PGSIZE	(0x2)
55 
56 /*
57  * EMIF4 PHY Control 1 register configuration
58  */
59 #define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
60 #define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
61 #define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
62 #define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
63 #define EMIF4_DDR1_READ_LAT	(0x6 << 0)
64 
65 #endif /* endif _EMIF_H_ */
66