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1 /*
2  * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __GIC_V2_H__
8 #define __GIC_V2_H__
9 
10 /* The macros required here are additional to those in gic_common.h. */
11 #include <gic_common.h>
12 
13 /******************************************************************************
14  * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
15  * and for GICv3 systems, use the driver in gicv3.h.
16  *****************************************************************************/
17 #if ERROR_DEPRECATED
18 #error " The legacy ARM GIC driver is deprecated."
19 #endif
20 
21 #define GIC400_NUM_SPIS		U(480)
22 #define MAX_PPIS		U(14)
23 #define MAX_SGIS		U(16)
24 
25 
26 #define GRP0			U(0)
27 #define GRP1			U(1)
28 #define GIC_TARGET_CPU_MASK	U(0xff)
29 
30 #define ENABLE_GRP0		(U(1) << 0)
31 #define ENABLE_GRP1		(U(1) << 1)
32 
33 /* Distributor interface definitions */
34 #define GICD_ITARGETSR		U(0x800)
35 #define GICD_SGIR		U(0xF00)
36 #define GICD_CPENDSGIR		U(0xF10)
37 #define GICD_SPENDSGIR		U(0xF20)
38 
39 #define CPENDSGIR_SHIFT		U(2)
40 #define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
41 
42 /* GICD_TYPER bit definitions */
43 #define IT_LINES_NO_MASK	U(0x1f)
44 
45 /* Physical CPU Interface registers */
46 #define GICC_CTLR		U(0x0)
47 #define GICC_PMR		U(0x4)
48 #define GICC_BPR		U(0x8)
49 #define GICC_IAR		U(0xC)
50 #define GICC_EOIR		U(0x10)
51 #define GICC_RPR		U(0x14)
52 #define GICC_HPPIR		U(0x18)
53 #define GICC_AHPPIR		U(0x28)
54 #define GICC_IIDR		U(0xFC)
55 #define GICC_DIR		U(0x1000)
56 #define GICC_PRIODROP           GICC_EOIR
57 
58 /* Common CPU Interface definitions */
59 #define INT_ID_MASK		U(0x3ff)
60 
61 /* GICC_CTLR bit definitions */
62 #define EOI_MODE_NS		(U(1) << 10)
63 #define EOI_MODE_S		(U(1) << 9)
64 #define IRQ_BYP_DIS_GRP1	(U(1) << 8)
65 #define FIQ_BYP_DIS_GRP1	(U(1) << 7)
66 #define IRQ_BYP_DIS_GRP0	(U(1) << 6)
67 #define FIQ_BYP_DIS_GRP0	(U(1) << 5)
68 #define CBPR			(U(1) << 4)
69 #define FIQ_EN			(U(1) << 3)
70 #define ACK_CTL			(U(1) << 2)
71 
72 /* GICC_IIDR bit masks and shifts */
73 #define GICC_IIDR_PID_SHIFT	U(20)
74 #define GICC_IIDR_ARCH_SHIFT	U(16)
75 #define GICC_IIDR_REV_SHIFT	U(12)
76 #define GICC_IIDR_IMP_SHIFT	U(0)
77 
78 #define GICC_IIDR_PID_MASK	U(0xfff)
79 #define GICC_IIDR_ARCH_MASK	U(0xf)
80 #define GICC_IIDR_REV_MASK	U(0xf)
81 #define GICC_IIDR_IMP_MASK	U(0xfff)
82 
83 /* HYP view virtual CPU Interface registers */
84 #define GICH_CTL		U(0x0)
85 #define GICH_VTR		U(0x4)
86 #define GICH_ELRSR0		U(0x30)
87 #define GICH_ELRSR1		U(0x34)
88 #define GICH_APR0		U(0xF0)
89 #define GICH_LR_BASE		U(0x100)
90 
91 /* Virtual CPU Interface registers */
92 #define GICV_CTL		U(0x0)
93 #define GICV_PRIMASK		U(0x4)
94 #define GICV_BP			U(0x8)
95 #define GICV_INTACK		U(0xC)
96 #define GICV_EOI		U(0x10)
97 #define GICV_RUNNINGPRI		U(0x14)
98 #define GICV_HIGHESTPEND	U(0x18)
99 #define GICV_DEACTIVATE		U(0x1000)
100 
101 #ifndef __ASSEMBLY__
102 
103 #include <mmio.h>
104 #include <stdint.h>
105 
106 /*******************************************************************************
107  * GIC Distributor function prototypes
108  ******************************************************************************/
109 
110 unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
111 unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
112 unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
113 unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
114 unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
115 unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
116 unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
117 unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
118 unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
119 unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
120 unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
121 unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
122 void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
123 void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
124 void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
125 void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
126 void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
127 void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
128 void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
129 void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
130 void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
131 void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
132 void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
133 void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
134 unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
135 void gicd_set_igroupr(uintptr_t, unsigned int);
136 void gicd_clr_igroupr(uintptr_t, unsigned int);
137 void gicd_set_isenabler(uintptr_t, unsigned int);
138 void gicd_set_icenabler(uintptr_t, unsigned int);
139 void gicd_set_ispendr(uintptr_t, unsigned int);
140 void gicd_set_icpendr(uintptr_t, unsigned int);
141 void gicd_set_isactiver(uintptr_t, unsigned int);
142 void gicd_set_icactiver(uintptr_t, unsigned int);
143 void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
144 void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
145 
146 
147 /*******************************************************************************
148  * GIC Distributor interface accessors for reading entire registers
149  ******************************************************************************/
150 
gicd_read_ctlr(uintptr_t base)151 static inline unsigned int gicd_read_ctlr(uintptr_t base)
152 {
153 	return mmio_read_32(base + GICD_CTLR);
154 }
155 
gicd_read_typer(uintptr_t base)156 static inline unsigned int gicd_read_typer(uintptr_t base)
157 {
158 	return mmio_read_32(base + GICD_TYPER);
159 }
160 
gicd_read_sgir(uintptr_t base)161 static inline unsigned int gicd_read_sgir(uintptr_t base)
162 {
163 	return mmio_read_32(base + GICD_SGIR);
164 }
165 
166 
167 /*******************************************************************************
168  * GIC Distributor interface accessors for writing entire registers
169  ******************************************************************************/
170 
gicd_write_ctlr(uintptr_t base,unsigned int val)171 static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
172 {
173 	mmio_write_32(base + GICD_CTLR, val);
174 }
175 
gicd_write_sgir(uintptr_t base,unsigned int val)176 static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
177 {
178 	mmio_write_32(base + GICD_SGIR, val);
179 }
180 
181 
182 /*******************************************************************************
183  * GIC CPU interface accessors for reading entire registers
184  ******************************************************************************/
185 
gicc_read_ctlr(uintptr_t base)186 static inline unsigned int gicc_read_ctlr(uintptr_t base)
187 {
188 	return mmio_read_32(base + GICC_CTLR);
189 }
190 
gicc_read_pmr(uintptr_t base)191 static inline unsigned int gicc_read_pmr(uintptr_t base)
192 {
193 	return mmio_read_32(base + GICC_PMR);
194 }
195 
gicc_read_BPR(uintptr_t base)196 static inline unsigned int gicc_read_BPR(uintptr_t base)
197 {
198 	return mmio_read_32(base + GICC_BPR);
199 }
200 
gicc_read_IAR(uintptr_t base)201 static inline unsigned int gicc_read_IAR(uintptr_t base)
202 {
203 	return mmio_read_32(base + GICC_IAR);
204 }
205 
gicc_read_EOIR(uintptr_t base)206 static inline unsigned int gicc_read_EOIR(uintptr_t base)
207 {
208 	return mmio_read_32(base + GICC_EOIR);
209 }
210 
gicc_read_hppir(uintptr_t base)211 static inline unsigned int gicc_read_hppir(uintptr_t base)
212 {
213 	return mmio_read_32(base + GICC_HPPIR);
214 }
215 
gicc_read_ahppir(uintptr_t base)216 static inline unsigned int gicc_read_ahppir(uintptr_t base)
217 {
218 	return mmio_read_32(base + GICC_AHPPIR);
219 }
220 
gicc_read_dir(uintptr_t base)221 static inline unsigned int gicc_read_dir(uintptr_t base)
222 {
223 	return mmio_read_32(base + GICC_DIR);
224 }
225 
gicc_read_iidr(uintptr_t base)226 static inline unsigned int gicc_read_iidr(uintptr_t base)
227 {
228 	return mmio_read_32(base + GICC_IIDR);
229 }
230 
231 
232 /*******************************************************************************
233  * GIC CPU interface accessors for writing entire registers
234  ******************************************************************************/
235 
gicc_write_ctlr(uintptr_t base,unsigned int val)236 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
237 {
238 	mmio_write_32(base + GICC_CTLR, val);
239 }
240 
gicc_write_pmr(uintptr_t base,unsigned int val)241 static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
242 {
243 	mmio_write_32(base + GICC_PMR, val);
244 }
245 
gicc_write_BPR(uintptr_t base,unsigned int val)246 static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
247 {
248 	mmio_write_32(base + GICC_BPR, val);
249 }
250 
251 
gicc_write_IAR(uintptr_t base,unsigned int val)252 static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
253 {
254 	mmio_write_32(base + GICC_IAR, val);
255 }
256 
gicc_write_EOIR(uintptr_t base,unsigned int val)257 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
258 {
259 	mmio_write_32(base + GICC_EOIR, val);
260 }
261 
gicc_write_hppir(uintptr_t base,unsigned int val)262 static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
263 {
264 	mmio_write_32(base + GICC_HPPIR, val);
265 }
266 
gicc_write_dir(uintptr_t base,unsigned int val)267 static inline void gicc_write_dir(uintptr_t base, unsigned int val)
268 {
269 	mmio_write_32(base + GICC_DIR, val);
270 }
271 
272 /*******************************************************************************
273  * Prototype of function to map an interrupt type to the interrupt line used to
274  * signal it.
275  ******************************************************************************/
276 uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
277 
278 #endif /*__ASSEMBLY__*/
279 
280 #endif /* __GIC_V2_H__ */
281