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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
4  */
5 
6 #ifndef __GX_H__
7 #define __GX_H__
8 
9 #define GX_FIRMWARE_MEM_SIZE	0x1000000
10 
11 #define GX_AOBUS_BASE		0xc8100000
12 #define GX_PERIPHS_BASE	0xc8834400
13 #define GX_HIU_BASE		0xc883c000
14 #define GX_ETH_BASE		0xc9410000
15 
16 /* Always-On Peripherals registers */
17 #define GX_AO_ADDR(off)	(GX_AOBUS_BASE + ((off) << 2))
18 
19 #define GX_AO_SEC_GP_CFG0	GX_AO_ADDR(0x90)
20 #define GX_AO_SEC_GP_CFG3	GX_AO_ADDR(0x93)
21 #define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
22 #define GX_AO_SEC_GP_CFG5	GX_AO_ADDR(0x95)
23 
24 #define GX_AO_MEM_SIZE_MASK	0xFFFF0000
25 #define GX_AO_MEM_SIZE_SHIFT	16
26 #define GX_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
27 #define GX_AO_BL31_RSVMEM_SIZE_SHIFT	16
28 #define GX_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
29 
30 /* Peripherals registers */
31 #define GX_PERIPHS_ADDR(off)	(GX_PERIPHS_BASE + ((off) << 2))
32 
33 /* GPIO registers 0 to 6 */
34 #define _GX_GPIO_OFF(n)	((n) == 6 ? 0x08 : 0x0c + 3 * (n))
35 #define GX_GPIO_EN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
36 #define GX_GPIO_IN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
37 #define GX_GPIO_OUT(n)	GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
38 
39 #define GX_ETH_REG_0		GX_PERIPHS_ADDR(0x50)
40 #define GX_ETH_REG_1		GX_PERIPHS_ADDR(0x51)
41 #define GX_ETH_REG_2		GX_PERIPHS_ADDR(0x56)
42 #define GX_ETH_REG_3		GX_PERIPHS_ADDR(0x57)
43 
44 #define GX_ETH_REG_0_PHY_INTF		BIT(0)
45 #define GX_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
46 #define GX_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
47 #define GX_ETH_REG_0_PHY_CLK_EN	BIT(10)
48 #define GX_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
49 #define GX_ETH_REG_0_CLK_EN		BIT(12)
50 
51 /* HIU registers */
52 #define GX_HIU_ADDR(off)	(GX_HIU_BASE + ((off) << 2))
53 
54 #define GX_MEM_PD_REG_0	GX_HIU_ADDR(0x40)
55 
56 /* Ethernet memory power domain */
57 #define GX_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
58 
59 #endif /* __GX_H__ */
60