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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015-2016 Marvell International Ltd.
4  */
5 
6 #ifndef _COMPHY_HPIPE_H_
7 #define _COMPHY_HPIPE_H_
8 
9 /* SerDes IP register */
10 #define SD_EXTERNAL_CONFIG0_REG			0
11 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET	1
12 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK	\
13 	(1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
14 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
15 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK	\
16 	(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
17 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
18 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK	\
19 	(0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
20 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET	11
21 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK	\
22 	(1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
23 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET	12
24 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK	\
25 	(1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
26 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
27 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK	\
28 	(1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
29 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET	15
30 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK	\
31 	(0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
32 
33 #define SD_EXTERNAL_CONFIG1_REG			0x4
34 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET	3
35 #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK	\
36 	(0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
37 #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET	4
38 #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK	\
39 	(0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
40 #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET	5
41 #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK	\
42 	(0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
43 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET	6
44 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK	\
45 	(0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
46 
47 #define SD_EXTERNAL_CONFIG2_REG			0x8
48 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET	4
49 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK	\
50 	(0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
51 #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET	7
52 #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK	\
53 	(0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
54 
55 #define SD_EXTERNAL_STATUS0_REG			0x18
56 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET	2
57 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK		\
58 	(0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
59 #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET	3
60 #define SD_EXTERNAL_STATUS0_PLL_RX_MASK		\
61 	(0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
62 #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET	4
63 #define SD_EXTERNAL_STATUS0_RX_INIT_MASK	\
64 	(0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
65 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET	6
66 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK	\
67 	(0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
68 
69 /* HPIPE register */
70 #define HPIPE_PWR_PLL_REG			0x4
71 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET		0
72 #define HPIPE_PWR_PLL_REF_FREQ_MASK		\
73 	(0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
74 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET		5
75 #define HPIPE_PWR_PLL_PHY_MODE_MASK		\
76 	(0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
77 
78 #define HPIPE_KVCO_CALIB_CTRL_REG		0x8
79 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET	12
80 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK	\
81 	(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
82 
83 #define HPIPE_CAL_REG1_REG			0xc
84 #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET	10
85 #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK		\
86 	(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
87 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET	15
88 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK	\
89 	(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
90 
91 #define HPIPE_SQUELCH_FFE_SETTING_REG           0x018
92 
93 #define HPIPE_DFE_REG0				0x01C
94 #define HPIPE_DFE_RES_FORCE_OFFSET		15
95 #define HPIPE_DFE_RES_FORCE_MASK		\
96 	(0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
97 
98 #define HPIPE_DFE_F3_F5_REG			0x028
99 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET		14
100 #define HPIPE_DFE_F3_F5_DFE_EN_MASK		\
101 	(0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
102 #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET		15
103 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK		\
104 	(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
105 
106 #define HPIPE_G1_SET_0_REG			0x034
107 #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET		1
108 #define HPIPE_G1_SET_0_G1_TX_AMP_MASK		\
109 	(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
110 #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET	6
111 #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK	\
112 	(0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
113 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET	7
114 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK		\
115 	(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
116 #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET	11
117 #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK	\
118 	(0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
119 
120 #define HPIPE_G1_SET_1_REG			0x038
121 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET	0
122 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK	\
123 	(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
124 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET	3
125 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK	\
126 	(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
127 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET	6
128 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK	\
129 	(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
130 #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET	8
131 #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK	\
132 	(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
133 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET	10
134 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK	\
135 	(0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
136 
137 #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET	11
138 #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK	\
139 	(0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
140 
141 #define HPIPE_G2_SET_0_REG			0x3c
142 #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET		1
143 #define HPIPE_G2_SET_0_G2_TX_AMP_MASK		\
144 	(0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
145 #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET	6
146 #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK	\
147 	(0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
148 #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET	7
149 #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK		\
150 	(0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
151 #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET	11
152 #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK	\
153 	(0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
154 
155 #define HPIPE_G2_SET_1_REG			0x040
156 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET	0
157 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK	\
158 	(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
159 #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET	3
160 #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK	\
161 	(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
162 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET	6
163 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK	\
164 	(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
165 #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET	8
166 #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK	\
167 	(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
168 #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET	10
169 #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK	\
170 	(0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
171 #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET	11
172 #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK	\
173 	(0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
174 
175 #define HPIPE_G3_SET_0_REG			0x44
176 #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET		1
177 #define HPIPE_G3_SET_0_G3_TX_AMP_MASK		\
178 	(0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
179 #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET	6
180 #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK	\
181 	(0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
182 #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET	7
183 #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK		\
184 	(0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
185 #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET	11
186 #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK	\
187 	(0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
188 #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
189 #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK	\
190 	(0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
191 #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
192 #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK	\
193 	(0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
194 
195 #define HPIPE_G3_SET_1_REG			0x048
196 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET	0
197 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK	\
198 	(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
199 #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET	3
200 #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK	\
201 	(0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
202 #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET	6
203 #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK	\
204 	(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
205 #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET	8
206 #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK	\
207 	(0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
208 #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET	10
209 #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK	\
210 	(0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
211 #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET	11
212 #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK	 \
213 	(0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
214 #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET	13
215 #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK	\
216 	(0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
217 
218 #define HPIPE_LOOPBACK_REG			0x08c
219 #define HPIPE_LOOPBACK_SEL_OFFSET		1
220 #define HPIPE_LOOPBACK_SEL_MASK			\
221 	(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
222 
223 #define HPIPE_SYNC_PATTERN_REG                  0x090
224 
225 #define HPIPE_INTERFACE_REG			0x94
226 #define HPIPE_INTERFACE_GEN_MAX_OFFSET		10
227 #define HPIPE_INTERFACE_GEN_MAX_MASK		\
228 	(0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
229 #define HPIPE_INTERFACE_DET_BYPASS_OFFSET	12
230 #define HPIPE_INTERFACE_DET_BYPASS_MASK		\
231 	(0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
232 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET	14
233 #define HPIPE_INTERFACE_LINK_TRAIN_MASK		\
234 	(0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
235 
236 #define HPIPE_ISOLATE_MODE_REG			0x98
237 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET	0
238 #define HPIPE_ISOLATE_MODE_GEN_RX_MASK		\
239 	(0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
240 #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET	4
241 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK		\
242 	(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
243 
244 #define HPIPE_G1_SET_2_REG			0xf4
245 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET	0
246 #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK		\
247 	(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
248 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET	4
249 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK	\
250 	(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
251 
252 #define HPIPE_VTHIMPCAL_CTRL_REG                0x104
253 
254 #define HPIPE_VDD_CAL_CTRL_REG			0x114
255 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET		5
256 #define HPIPE_EXT_SELLV_RXSAMPL_MASK		\
257 	(0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
258 
259 #define HPIPE_VDD_CAL_0_REG			0x108
260 #define HPIPE_CAL_VDD_CONT_MODE_OFFSET		15
261 #define HPIPE_CAL_VDD_CONT_MODE_MASK		\
262 	(0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
263 
264 #define HPIPE_PCIE_REG0                         0x120
265 #define HPIPE_PCIE_IDLE_SYNC_OFFSET		12
266 #define HPIPE_PCIE_IDLE_SYNC_MASK		\
267 	(0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
268 #define HPIPE_PCIE_SEL_BITS_OFFSET		13
269 #define HPIPE_PCIE_SEL_BITS_MASK		\
270 	(0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
271 
272 #define HPIPE_LANE_ALIGN_REG			0x124
273 #define HPIPE_LANE_ALIGN_OFF_OFFSET		12
274 #define HPIPE_LANE_ALIGN_OFF_MASK		\
275 	(0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
276 
277 #define HPIPE_MISC_REG				0x13C
278 #define HPIPE_MISC_CLK100M_125M_OFFSET		4
279 #define HPIPE_MISC_CLK100M_125M_MASK		\
280 	(0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
281 #define HPIPE_MISC_ICP_FORCE_OFFSET		5
282 #define HPIPE_MISC_ICP_FORCE_MASK		\
283 	(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
284 #define HPIPE_MISC_TXDCLK_2X_OFFSET		6
285 #define HPIPE_MISC_TXDCLK_2X_MASK		\
286 	(0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
287 #define HPIPE_MISC_CLK500_EN_OFFSET		7
288 #define HPIPE_MISC_CLK500_EN_MASK		\
289 	(0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
290 #define HPIPE_MISC_REFCLK_SEL_OFFSET		10
291 #define HPIPE_MISC_REFCLK_SEL_MASK		\
292 	(0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
293 
294 #define HPIPE_RX_CONTROL_1_REG			0x140
295 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET	11
296 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK	\
297 	(0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
298 #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET	12
299 #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK	\
300 	(0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
301 
302 #define HPIPE_PWR_CTR_REG			0x148
303 #define HPIPE_PWR_CTR_RST_DFE_OFFSET		0
304 #define HPIPE_PWR_CTR_RST_DFE_MASK		\
305 	(0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
306 #define HPIPE_PWR_CTR_SFT_RST_OFFSET		10
307 #define HPIPE_PWR_CTR_SFT_RST_MASK		\
308 	(0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
309 
310 #define HPIPE_SPD_DIV_FORCE_REG				0x154
311 #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET			7
312 #define HPIPE_TXDIGCK_DIV_FORCE_MASK			\
313 	(0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
314 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET		8
315 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK		\
316 	(0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
317 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET	10
318 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK	\
319 	(0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
320 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET		13
321 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK		\
322 	(0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
323 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET	15
324 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK	\
325 	(0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
326 
327 #define HPIPE_PLLINTP_REG1			0x150
328 
329 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG	0x16C
330 #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET		6
331 #define HPIPE_RX_SAMPLER_OS_GAIN_MASK		\
332 	(0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
333 #define HPIPE_SMAPLER_OFFSET			12
334 #define HPIPE_SMAPLER_MASK			\
335 	(0x1 << HPIPE_SMAPLER_OFFSET)
336 
337 #define HPIPE_TX_REG1_REG			0x174
338 #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET	5
339 #define HPIPE_TX_REG1_TX_EMPH_RES_MASK		\
340 	(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
341 #define HPIPE_TX_REG1_SLC_EN_OFFSET		10
342 #define HPIPE_TX_REG1_SLC_EN_MASK		\
343 	(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
344 
345 #define HPIPE_PWR_CTR_DTL_REG				0x184
346 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET		0
347 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK		\
348 	(0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
349 #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET		1
350 #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK		\
351 	(0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
352 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET		2
353 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK			\
354 	(0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
355 #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET		4
356 #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK		\
357 	(0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
358 #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET	10
359 #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK	\
360 	(0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
361 #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET		12
362 #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK			\
363 	(0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
364 #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET		14
365 #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK		\
366 	(1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
367 
368 #define HPIPE_PHASE_CONTROL_REG			0x188
369 #define HPIPE_OS_PH_OFFSET_OFFSET		0
370 #define HPIPE_OS_PH_OFFSET_MASK			\
371 	(0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
372 #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET		7
373 #define HPIPE_OS_PH_OFFSET_FORCE_MASK		\
374 	(0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
375 #define HPIPE_OS_PH_VALID_OFFSET		8
376 #define HPIPE_OS_PH_VALID_MASK			\
377 	(0x1 << HPIPE_OS_PH_VALID_OFFSET)
378 
379 #define HPIPE_FRAME_DETECT_CTRL_0_REG			0x214
380 #define HPIPE_TRAIN_PAT_NUM_OFFSET			0x7
381 #define HPIPE_TRAIN_PAT_NUM_MASK			\
382 	(0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
383 
384 #define HPIPE_FRAME_DETECT_CTRL_3_REG			0x220
385 #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET	12
386 #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK		\
387 	(0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
388 
389 #define HPIPE_DME_REG					0x228
390 #define HPIPE_DME_ETHERNET_MODE_OFFSET			7
391 #define HPIPE_DME_ETHERNET_MODE_MASK			\
392 	(0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
393 
394 #define HPIPE_TX_TRAIN_CTRL_0_REG		0x268
395 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET		15
396 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK		\
397 	(0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
398 
399 #define HPIPE_TX_TRAIN_CTRL_REG			0x26C
400 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET		0
401 #define HPIPE_TX_TRAIN_CTRL_G1_MASK		\
402 	(0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
403 #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET		1
404 #define HPIPE_TX_TRAIN_CTRL_GN1_MASK		\
405 	(0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
406 #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET		2
407 #define HPIPE_TX_TRAIN_CTRL_G0_MASK		\
408 	(0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
409 
410 #define HPIPE_TX_TRAIN_CTRL_4_REG		0x278
411 #define HPIPE_TRX_TRAIN_TIMER_OFFSET		0
412 #define HPIPE_TRX_TRAIN_TIMER_MASK		\
413 	(0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
414 
415 #define HPIPE_PCIE_REG1				0x288
416 #define HPIPE_PCIE_REG3				0x290
417 
418 #define HPIPE_TX_TRAIN_CTRL_5_REG		0x2A4
419 #define HPIPE_RX_TRAIN_TIMER_OFFSET		0
420 #define HPIPE_RX_TRAIN_TIMER_MASK		\
421 	(0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
422 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET	11
423 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK		\
424 	(0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
425 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET	12
426 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK	\
427 	(0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
428 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET	13
429 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK	\
430 	(0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
431 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET	14
432 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK	\
433 	(0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
434 
435 #define HPIPE_TX_TRAIN_REG			0x31C
436 #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET		4
437 #define HPIPE_TX_TRAIN_CHK_INIT_MASK		\
438 	(0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
439 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET	7
440 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK	\
441 	(0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
442 #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET	8
443 #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK	\
444 	(0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
445 #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET		9
446 #define HPIPE_TX_TRAIN_PAT_SEL_MASK		\
447 	(0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
448 
449 #define HPIPE_CDR_CONTROL_REG			0x418
450 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET	12
451 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK	\
452 	(0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
453 #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET	9
454 #define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK		\
455 	(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
456 #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET	6
457 #define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK		\
458 	(0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
459 
460 #define HPIPE_TX_TRAIN_CTRL_11_REG		0x438
461 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET	6
462 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK	\
463 	(0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
464 #define HPIPE_TX_NUM_OF_PRESET_OFFSET		10
465 #define HPIPE_TX_NUM_OF_PRESET_MASK		\
466 	(0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
467 #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET		15
468 #define HPIPE_TX_SWEEP_PRESET_EN_MASK		\
469 	(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
470 
471 #define HPIPE_G1_SETTINGS_3_REG				0x440
472 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET	0
473 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK		\
474 	(0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
475 #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET	4
476 #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK		\
477 	(0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
478 #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET	7
479 #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK	\
480 	(0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
481 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET		9
482 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK		\
483 	(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
484 #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET	12
485 #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK	\
486 	(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
487 #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET	14
488 #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK	\
489 	(0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
490 
491 #define HPIPE_G1_SETTINGS_4_REG			0x444
492 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET	8
493 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK	\
494 	(0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
495 
496 #define HPIPE_G2_SETTINGS_3_REG			0x448
497 
498 #define HPIPE_G2_SETTINGS_4_REG			0x44c
499 #define HPIPE_G2_DFE_RES_OFFSET			8
500 #define HPIPE_G2_DFE_RES_MASK			\
501 	(0x3 << HPIPE_G2_DFE_RES_OFFSET)
502 
503 #define HPIPE_G3_SETTING_3_REG			0x450
504 #define HPIPE_G3_FFE_CAP_SEL_OFFSET		0
505 #define HPIPE_G3_FFE_CAP_SEL_MASK		\
506 	(0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
507 #define HPIPE_G3_FFE_RES_SEL_OFFSET		4
508 #define HPIPE_G3_FFE_RES_SEL_MASK		\
509 	(0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
510 #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET	7
511 #define HPIPE_G3_FFE_SETTING_FORCE_MASK		\
512 	(0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
513 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET	12
514 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK		\
515 	(0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
516 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET	14
517 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK	\
518 	(0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
519 
520 #define HPIPE_G3_SETTING_4_REG			0x454
521 #define HPIPE_G3_DFE_RES_OFFSET			8
522 #define HPIPE_G3_DFE_RES_MASK			\
523 	(0x3 << HPIPE_G3_DFE_RES_OFFSET)
524 
525 #define HPIPE_TX_PRESET_INDEX_REG		0x468
526 #define HPIPE_TX_PRESET_INDEX_OFFSET		0
527 #define HPIPE_TX_PRESET_INDEX_MASK		\
528 	(0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
529 
530 #define HPIPE_DFE_CONTROL_REG			0x470
531 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET	14
532 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK		\
533 	(0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
534 
535 #define HPIPE_DFE_CTRL_28_REG			0x49C
536 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET		7
537 #define HPIPE_DFE_CTRL_28_PIPE4_MASK		\
538 	(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
539 
540 #define HPIPE_G1_SETTING_5_REG			0x538
541 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET	0
542 #define HPIPE_G1_SETTING_5_G1_ICP_MASK		\
543 	(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
544 
545 #define HPIPE_G3_SETTING_5_REG			0x548
546 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET	0
547 #define HPIPE_G3_SETTING_5_G3_ICP_MASK		\
548 	(0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
549 
550 #define HPIPE_LANE_CONFIG0_REG			0x600
551 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET	0
552 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK	\
553 	(0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
554 
555 #define HPIPE_LANE_CONFIG1_REG			0x604
556 #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET	9
557 #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK		\
558 	(0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
559 #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET	10
560 #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK	\
561 	(0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
562 
563 #define HPIPE_LANE_STATUS1_REG			0x60C
564 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET	0
565 #define HPIPE_LANE_STATUS1_PCLK_EN_MASK		\
566 	(0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
567 
568 #define HPIPE_LANE_CFG4_REG                     0x620
569 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET		0
570 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK		\
571 	(0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
572 #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET	3
573 #define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK		\
574 	(0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
575 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET		6
576 #define HPIPE_LANE_CFG4_DFE_OVER_MASK		\
577 	(0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
578 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET		7
579 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK		\
580 	(0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
581 
582 #define HPIPE_LANE_EQU_CONFIG_0_REG		0x69C
583 #define HPIPE_CFG_PHY_RC_EP_OFFSET		12
584 #define HPIPE_CFG_PHY_RC_EP_MASK		\
585 	(0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
586 
587 #define HPIPE_LANE_EQ_CFG1_REG			0x6a0
588 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET	12
589 #define HPIPE_CFG_UPDATE_POLARITY_MASK		\
590 	(0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
591 
592 #define HPIPE_LANE_EQ_REMOTE_SETTING_REG	0x6f8
593 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET	0
594 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK	\
595 	(0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
596 #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET	1
597 #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK	\
598 	(0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
599 #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET	2
600 #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK	\
601 	(0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
602 
603 #define HPIPE_RST_CLK_CTRL_REG			0x704
604 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET	0
605 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK	\
606 	(0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
607 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET	2
608 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK	\
609 	(0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
610 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET	3
611 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK	\
612 	(0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
613 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET	9
614 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK	\
615 	(0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
616 
617 #define HPIPE_TST_MODE_CTRL_REG			0x708
618 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET	2
619 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK	\
620 	(0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
621 
622 #define HPIPE_CLK_SRC_LO_REG			0x70c
623 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
624 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK	\
625 	(0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
626 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
627 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
628 	(0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
629 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET	5
630 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK	\
631 	(0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
632 
633 #define HPIPE_CLK_SRC_HI_REG			0x710
634 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET	0
635 #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK		\
636 	(0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
637 #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET	1
638 #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK	\
639 	(0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
640 #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET	2
641 #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK	\
642 	(0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
643 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET	7
644 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK		\
645 	(0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
646 
647 #define HPIPE_GLOBAL_MISC_CTRL                  0x718
648 #define HPIPE_GLOBAL_PM_CTRL                    0x740
649 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET	0
650 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK	\
651 	(0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
652 
653 #endif /* _COMPHY_HPIPE_H_ */
654 
655