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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Based on Linux i.MX iomux-v3.h file:
4  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5  *			<armlinux@phytec.de>
6  *
7  * Copyright (C) 2016 Freescale Semiconductor, Inc.
8  */
9 
10 #ifndef __MACH_IOMUX_H__
11 #define __MACH_IOMUX_H__
12 
13 /*
14  *	build IOMUX_PAD structure
15  *
16  * This iomux scheme is based around pads, which are the physical balls
17  * on the processor.
18  *
19  * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
20  *   things like driving strength and pullup/pulldown.
21  * - Each pad can have but not necessarily does have an output routing register
22  *   (IOMUXC_SW_MUX_CTL_PAD_x).
23  * - Each pad can have but not necessarily does have an input routing register
24  *   (IOMUXC_x_SELECT_INPUT)
25  *
26  * The three register sets do not have a fixed offset to each other,
27  * hence we order this table by pad control registers (which all pads
28  * have) and put the optional i/o routing registers into additional
29  * fields.
30  *
31  * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
32  * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
33  *
34  * IOMUX/PAD Bit field definitions
35  *
36  * MUX_CTRL_OFS:	                0..15 (16)
37  * SEL_INPUT_OFS:	               16..31 (16)
38  * MUX_MODE:	                   32..37  (6)
39  * SEL_INP:		                   38..41  (4)
40  * PAD_CTRL + NO_PAD_CTRL:         42..60 (19)
41  * reserved:		               61-63      (3)
42 */
43 
44 typedef u64 iomux_cfg_t;
45 
46 #define MUX_CTRL_OFS_SHIFT	     0
47 #define MUX_CTRL_OFS_MASK	((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
48 #define MUX_SEL_INPUT_OFS_SHIFT	16
49 #define MUX_SEL_INPUT_OFS_MASK	((iomux_cfg_t)0xffff << \
50 	MUX_SEL_INPUT_OFS_SHIFT)
51 
52 #define MUX_MODE_SHIFT		32
53 #define MUX_MODE_MASK		((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
54 #define MUX_SEL_INPUT_SHIFT	38
55 #define MUX_SEL_INPUT_MASK	((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
56 #define MUX_PAD_CTRL_SHIFT	42
57 #define MUX_PAD_CTRL_MASK	((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
58 
59 #define MUX_PAD_CTRL(x)		((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
60 
61 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
62 		sel_input, pad_ctrl)					\
63 	(((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
64 	((iomux_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
65 	((iomux_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
66 	((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
67 	((iomux_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
68 
69 #define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
70 					MUX_PAD_CTRL(pad))
71 
72 
73 #define IOMUX_CONFIG_MPORTS       0x20
74 #define MUX_MODE_MPORTS           ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
75 				MUX_MODE_SHIFT)
76 
77 /* Bit definition below needs to be fixed acccording to ulp rm */
78 
79 #define NO_PAD_CTRL		     (1 << 18)
80 #define PAD_CTL_OBE_ENABLE	 (1 << 17)
81 #define PAD_CTL_IBE_ENABLE	 (1 << 16)
82 #define PAD_CTL_DSE          (1 << 6)
83 #define PAD_CTL_ODE          (1 << 5)
84 #define PAD_CTL_SRE_FAST     (0 << 2)
85 #define PAD_CTL_SRE_SLOW     (1 << 2)
86 #define PAD_CTL_PUE          (1 << 1)
87 #define PAD_CTL_PUS_UP       ((1 << 0) | PAD_CTL_PUE)
88 #define PAD_CTL_PUS_DOWN     ((0 << 0) | PAD_CTL_PUE)
89 
90 
91 void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
92 void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
93 				      unsigned count);
94 #endif	/* __MACH_IOMUX_H__*/
95