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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Marvell Semiconductor <www.marvell.com>
5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6  */
7 
8 #ifndef _KWCPU_H
9 #define _KWCPU_H
10 
11 #include <asm/system.h>
12 
13 #ifndef __ASSEMBLY__
14 
15 #define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
16 			| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
17 
18 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
19 		((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
20 
21 #define KW_REG_PCIE_DEVID		(KW_REG_PCIE_BASE + 0x00)
22 #define KW_REG_PCIE_REVID		(KW_REG_PCIE_BASE + 0x08)
23 #define KW_REG_DEVICE_ID		(KW_MPP_BASE + 0x34)
24 #define KW_REG_SYSRST_CNT		(KW_MPP_BASE + 0x50)
25 #define SYSRST_CNT_1SEC_VAL		(25*1000000)
26 #define KW_REG_MPP_OUT_DRV_REG		(KW_MPP_BASE + 0xE0)
27 
28 enum memory_bank {
29 	BANK0,
30 	BANK1,
31 	BANK2,
32 	BANK3
33 };
34 
35 enum kwcpu_winen {
36 	KWCPU_WIN_DISABLE,
37 	KWCPU_WIN_ENABLE
38 };
39 
40 enum kwcpu_target {
41 	KWCPU_TARGET_RESERVED,
42 	KWCPU_TARGET_MEMORY,
43 	KWCPU_TARGET_1RESERVED,
44 	KWCPU_TARGET_SASRAM,
45 	KWCPU_TARGET_PCIE
46 };
47 
48 enum kwcpu_attrib {
49 	KWCPU_ATTR_SASRAM = 0x01,
50 	KWCPU_ATTR_DRAM_CS0 = 0x0e,
51 	KWCPU_ATTR_DRAM_CS1 = 0x0d,
52 	KWCPU_ATTR_DRAM_CS2 = 0x0b,
53 	KWCPU_ATTR_DRAM_CS3 = 0x07,
54 	KWCPU_ATTR_NANDFLASH = 0x2f,
55 	KWCPU_ATTR_SPIFLASH = 0x1e,
56 	KWCPU_ATTR_BOOTROM = 0x1d,
57 	KWCPU_ATTR_PCIE_IO = 0xe0,
58 	KWCPU_ATTR_PCIE_MEM = 0xe8
59 };
60 
61 /*
62  * Default Device Address MAP BAR values
63  */
64 #define KW_DEFADR_PCI_MEM	0x90000000
65 #define KW_DEFADR_PCI_IO	0xC0000000
66 #define KW_DEFADR_PCI_IO_REMAP	0xC0000000
67 #define KW_DEFADR_SASRAM	0xC8010000
68 #define KW_DEFADR_NANDF		0xD8000000
69 #define KW_DEFADR_SPIF		0xE8000000
70 #define KW_DEFADR_BOOTROM	0xF8000000
71 
72 /*
73  * read feroceon/sheeva core extra feature register
74  * using co-proc instruction
75  */
readfr_extra_feature_reg(void)76 static inline unsigned int readfr_extra_feature_reg(void)
77 {
78 	unsigned int val;
79 	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
80 			(val)::"cc");
81 	return val;
82 }
83 
84 /*
85  * write feroceon/sheeva core extra feature register
86  * using co-proc instruction
87  */
writefr_extra_feature_reg(unsigned int val)88 static inline void writefr_extra_feature_reg(unsigned int val)
89 {
90 	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
91 			(val):"cc");
92 	isb();
93 }
94 
95 /*
96  * MBus-L to Mbus Bridge Registers
97  * Ref: Datasheet sec:A.3
98  */
99 struct kwwin_registers {
100 	u32 ctrl;
101 	u32 base;
102 	u32 remap_lo;
103 	u32 remap_hi;
104 };
105 
106 /*
107  * CPU control and status Registers
108  * Ref: Datasheet sec:A.3.2
109  */
110 struct kwcpu_registers {
111 	u32 config;	/*0x20100 */
112 	u32 ctrl_stat;	/*0x20104 */
113 	u32 rstoutn_mask; /* 0x20108 */
114 	u32 sys_soft_rst; /* 0x2010C */
115 	u32 ahb_mbus_cause_irq; /* 0x20110 */
116 	u32 ahb_mbus_mask_irq; /* 0x20114 */
117 	u32 pad1[2];
118 	u32 ftdll_config; /* 0x20120 */
119 	u32 pad2;
120 	u32 l2_cfg;	/* 0x20128 */
121 };
122 
123 /*
124  * GPIO Registers
125  * Ref: Datasheet sec:A.19
126  */
127 struct kwgpio_registers {
128 	u32 dout;
129 	u32 oe;
130 	u32 blink_en;
131 	u32 din_pol;
132 	u32 din;
133 	u32 irq_cause;
134 	u32 irq_mask;
135 	u32 irq_level;
136 };
137 
138 /*
139  * functions
140  */
141 unsigned int mvebu_sdram_bar(enum memory_bank bank);
142 unsigned int mvebu_sdram_bs(enum memory_bank bank);
143 void mvebu_sdram_size_adjust(enum memory_bank bank);
144 int kw_config_adr_windows(void);
145 void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
146 		unsigned int gpp0_oe, unsigned int gpp1_oe);
147 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
148 		unsigned int mpp16_23, unsigned int mpp24_31,
149 		unsigned int mpp32_39, unsigned int mpp40_47,
150 		unsigned int mpp48_55);
151 unsigned int kw_winctrl_calcsize(unsigned int sizeval);
152 #endif /* __ASSEMBLY__ */
153 #endif /* _KWCPU_H */
154