1 //===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the PowerPC specific subclass of MachineFunctionInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 16 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/TargetCallingConv.h" 20 21 namespace llvm { 22 23 /// PPCFunctionInfo - This class is derived from MachineFunction private 24 /// PowerPC target-specific information for each MachineFunction. 25 class PPCFunctionInfo : public MachineFunctionInfo { 26 virtual void anchor(); 27 28 /// FramePointerSaveIndex - Frame index of where the old frame pointer is 29 /// stored. Also used as an anchor for instructions that need to be altered 30 /// when using frame pointers (dyna_add, dyna_sub.) 31 int FramePointerSaveIndex = 0; 32 33 /// ReturnAddrSaveIndex - Frame index of where the return address is stored. 34 /// 35 int ReturnAddrSaveIndex = 0; 36 37 /// Frame index where the old base pointer is stored. 38 int BasePointerSaveIndex = 0; 39 40 /// Frame index where the old PIC base pointer is stored. 41 int PICBasePointerSaveIndex = 0; 42 43 /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current 44 /// function. This is only valid after the initial scan of the function by 45 /// PEI. 46 bool MustSaveLR; 47 48 /// Do we have to disable shrink-wrapping? This has to be set if we emit any 49 /// instructions that clobber LR in the entry block because discovering this 50 /// in PEI is too late (happens after shrink-wrapping); 51 bool ShrinkWrapDisabled = false; 52 53 /// Does this function have any stack spills. 54 bool HasSpills = false; 55 56 /// Does this function spill using instructions with only r+r (not r+i) 57 /// forms. 58 bool HasNonRISpills = false; 59 60 /// SpillsCR - Indicates whether CR is spilled in the current function. 61 bool SpillsCR = false; 62 63 /// Indicates whether VRSAVE is spilled in the current function. 64 bool SpillsVRSAVE = false; 65 66 /// LRStoreRequired - The bool indicates whether there is some explicit use of 67 /// the LR/LR8 stack slot that is not obvious from scanning the code. This 68 /// requires that the code generator produce a store of LR to the stack on 69 /// entry, even though LR may otherwise apparently not be used. 70 bool LRStoreRequired = false; 71 72 /// This function makes use of the PPC64 ELF TOC base pointer (register r2). 73 bool UsesTOCBasePtr = false; 74 75 /// MinReservedArea - This is the frame size that is at least reserved in a 76 /// potential caller (parameter+linkage area). 77 unsigned MinReservedArea = 0; 78 79 /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum 80 /// amount the stack pointer is adjusted to make the frame bigger for tail 81 /// calls. Used for creating an area before the register spill area. 82 int TailCallSPDelta = 0; 83 84 /// HasFastCall - Does this function contain a fast call. Used to determine 85 /// how the caller's stack pointer should be calculated (epilog/dynamicalloc). 86 bool HasFastCall = false; 87 88 /// VarArgsFrameIndex - FrameIndex for start of varargs area. 89 int VarArgsFrameIndex = 0; 90 91 /// VarArgsStackOffset - StackOffset for start of stack 92 /// arguments. 93 94 int VarArgsStackOffset = 0; 95 96 /// VarArgsNumGPR - Index of the first unused integer 97 /// register for parameter passing. 98 unsigned VarArgsNumGPR = 0; 99 100 /// VarArgsNumFPR - Index of the first unused double 101 /// register for parameter passing. 102 unsigned VarArgsNumFPR = 0; 103 104 /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4. 105 int CRSpillFrameIndex = 0; 106 107 /// If any of CR[2-4] need to be saved in the prologue and restored in the 108 /// epilogue then they are added to this array. This is used for the 109 /// 64-bit SVR4 ABI. 110 SmallVector<unsigned, 3> MustSaveCRs; 111 112 /// Hold onto our MachineFunction context. 113 MachineFunction &MF; 114 115 /// Whether this uses the PIC Base register or not. 116 bool UsesPICBase = false; 117 118 /// True if this function has a subset of CSRs that is handled explicitly via 119 /// copies 120 bool IsSplitCSR = false; 121 122 /// We keep track attributes for each live-in virtual registers 123 /// to use SExt/ZExt flags in later optimization. 124 std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs; 125 126 public: PPCFunctionInfo(MachineFunction & MF)127 explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {} 128 getFramePointerSaveIndex()129 int getFramePointerSaveIndex() const { return FramePointerSaveIndex; } setFramePointerSaveIndex(int Idx)130 void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; } 131 getReturnAddrSaveIndex()132 int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; } setReturnAddrSaveIndex(int idx)133 void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; } 134 getBasePointerSaveIndex()135 int getBasePointerSaveIndex() const { return BasePointerSaveIndex; } setBasePointerSaveIndex(int Idx)136 void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; } 137 getPICBasePointerSaveIndex()138 int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; } setPICBasePointerSaveIndex(int Idx)139 void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; } 140 getMinReservedArea()141 unsigned getMinReservedArea() const { return MinReservedArea; } setMinReservedArea(unsigned size)142 void setMinReservedArea(unsigned size) { MinReservedArea = size; } 143 getTailCallSPDelta()144 int getTailCallSPDelta() const { return TailCallSPDelta; } setTailCallSPDelta(int size)145 void setTailCallSPDelta(int size) { TailCallSPDelta = size; } 146 147 /// MustSaveLR - This is set when the prolog/epilog inserter does its initial 148 /// scan of the function. It is true if the LR/LR8 register is ever explicitly 149 /// defined/clobbered in the machine function (e.g. by calls and movpctolr, 150 /// which is used in PIC generation), or if the LR stack slot is explicitly 151 /// referenced by builtin_return_address. setMustSaveLR(bool U)152 void setMustSaveLR(bool U) { MustSaveLR = U; } mustSaveLR()153 bool mustSaveLR() const { return MustSaveLR; } 154 155 /// We certainly don't want to shrink wrap functions if we've emitted a 156 /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely 157 /// has to go into the entry block. setShrinkWrapDisabled(bool U)158 void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; } shrinkWrapDisabled()159 bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; } 160 setHasSpills()161 void setHasSpills() { HasSpills = true; } hasSpills()162 bool hasSpills() const { return HasSpills; } 163 setHasNonRISpills()164 void setHasNonRISpills() { HasNonRISpills = true; } hasNonRISpills()165 bool hasNonRISpills() const { return HasNonRISpills; } 166 setSpillsCR()167 void setSpillsCR() { SpillsCR = true; } isCRSpilled()168 bool isCRSpilled() const { return SpillsCR; } 169 setSpillsVRSAVE()170 void setSpillsVRSAVE() { SpillsVRSAVE = true; } isVRSAVESpilled()171 bool isVRSAVESpilled() const { return SpillsVRSAVE; } 172 setLRStoreRequired()173 void setLRStoreRequired() { LRStoreRequired = true; } isLRStoreRequired()174 bool isLRStoreRequired() const { return LRStoreRequired; } 175 setUsesTOCBasePtr()176 void setUsesTOCBasePtr() { UsesTOCBasePtr = true; } usesTOCBasePtr()177 bool usesTOCBasePtr() const { return UsesTOCBasePtr; } 178 setHasFastCall()179 void setHasFastCall() { HasFastCall = true; } hasFastCall()180 bool hasFastCall() const { return HasFastCall;} 181 getVarArgsFrameIndex()182 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } setVarArgsFrameIndex(int Index)183 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } 184 getVarArgsStackOffset()185 int getVarArgsStackOffset() const { return VarArgsStackOffset; } setVarArgsStackOffset(int Offset)186 void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; } 187 getVarArgsNumGPR()188 unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; } setVarArgsNumGPR(unsigned Num)189 void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; } 190 getVarArgsNumFPR()191 unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; } setVarArgsNumFPR(unsigned Num)192 void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; } 193 194 /// This function associates attributes for each live-in virtual register. addLiveInAttr(unsigned VReg,ISD::ArgFlagsTy Flags)195 void addLiveInAttr(unsigned VReg, ISD::ArgFlagsTy Flags) { 196 LiveInAttrs.push_back(std::make_pair(VReg, Flags)); 197 } 198 199 /// This function returns true if the specified vreg is 200 /// a live-in register and sign-extended. 201 bool isLiveInSExt(unsigned VReg) const; 202 203 /// This function returns true if the specified vreg is 204 /// a live-in register and zero-extended. 205 bool isLiveInZExt(unsigned VReg) const; 206 getCRSpillFrameIndex()207 int getCRSpillFrameIndex() const { return CRSpillFrameIndex; } setCRSpillFrameIndex(int idx)208 void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; } 209 210 const SmallVectorImpl<unsigned> & getMustSaveCRs()211 getMustSaveCRs() const { return MustSaveCRs; } addMustSaveCR(unsigned Reg)212 void addMustSaveCR(unsigned Reg) { MustSaveCRs.push_back(Reg); } 213 setUsesPICBase(bool uses)214 void setUsesPICBase(bool uses) { UsesPICBase = uses; } usesPICBase()215 bool usesPICBase() const { return UsesPICBase; } 216 isSplitCSR()217 bool isSplitCSR() const { return IsSplitCSR; } setIsSplitCSR(bool s)218 void setIsSplitCSR(bool s) { IsSplitCSR = s; } 219 220 MCSymbol *getPICOffsetSymbol() const; 221 222 MCSymbol *getGlobalEPSymbol() const; 223 MCSymbol *getLocalEPSymbol() const; 224 MCSymbol *getTOCOffsetSymbol() const; 225 }; 226 227 } // end namespace llvm 228 229 #endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H 230