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1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Blackfin uses to lower LLVM code
11 // into a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BlackfinISelLowering.h"
16 #include "BlackfinTargetMachine.h"
17 #include "llvm/Function.h"
18 #include "llvm/Type.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 using namespace llvm;
31 
32 //===----------------------------------------------------------------------===//
33 // Calling Convention Implementation
34 //===----------------------------------------------------------------------===//
35 
36 #include "BlackfinGenCallingConv.inc"
37 
38 //===----------------------------------------------------------------------===//
39 // TargetLowering Implementation
40 //===----------------------------------------------------------------------===//
41 
BlackfinTargetLowering(TargetMachine & TM)42 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
43   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
44   setBooleanContents(ZeroOrOneBooleanContent);
45   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
46   setStackPointerRegisterToSaveRestore(BF::SP);
47   setIntDivIsCheap(false);
48 
49   // Set up the legal register classes.
50   addRegisterClass(MVT::i32, BF::DRegisterClass);
51   addRegisterClass(MVT::i16, BF::D16RegisterClass);
52 
53   computeRegisterProperties();
54 
55   // Blackfin doesn't have i1 loads or stores
56   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
57   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
58   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
59 
60   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
61   setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
62 
63   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
64   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
65   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
66 
67   // i16 registers don't do much
68   setOperationAction(ISD::AND,   MVT::i16, Promote);
69   setOperationAction(ISD::OR,    MVT::i16, Promote);
70   setOperationAction(ISD::XOR,   MVT::i16, Promote);
71   setOperationAction(ISD::CTPOP, MVT::i16, Promote);
72   // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
73   // immediately.
74   setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
75   setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
76   setOperationAction(ISD::SETCC, MVT::i16, Promote);
77 
78   // Blackfin has no division
79   setOperationAction(ISD::SDIV,    MVT::i16, Expand);
80   setOperationAction(ISD::SDIV,    MVT::i32, Expand);
81   setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
82   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
83   setOperationAction(ISD::SREM,    MVT::i16, Expand);
84   setOperationAction(ISD::SREM,    MVT::i32, Expand);
85   setOperationAction(ISD::UDIV,    MVT::i16, Expand);
86   setOperationAction(ISD::UDIV,    MVT::i32, Expand);
87   setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
88   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
89   setOperationAction(ISD::UREM,    MVT::i16, Expand);
90   setOperationAction(ISD::UREM,    MVT::i32, Expand);
91 
92   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
93   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94   setOperationAction(ISD::MULHU,     MVT::i32, Expand);
95   setOperationAction(ISD::MULHS,     MVT::i32, Expand);
96 
97   // No carry-in operations.
98   setOperationAction(ISD::ADDE, MVT::i32, Custom);
99   setOperationAction(ISD::SUBE, MVT::i32, Custom);
100 
101   // Blackfin has no intrinsics for these particular operations.
102   setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
103   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
104   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
105 
106   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
107   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
108   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
109 
110   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
111 
112   // i32 has native CTPOP, but not CTLZ/CTTZ
113   setOperationAction(ISD::CTLZ, MVT::i32, Expand);
114   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
115 
116   // READCYCLECOUNTER needs special type legalization.
117   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
118 
119   setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
120 
121   // Use the default implementation.
122   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
123   setOperationAction(ISD::VAEND, MVT::Other, Expand);
124   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
125   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
126 
127   setMinFunctionAlignment(2);
128 }
129 
getTargetNodeName(unsigned Opcode) const130 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
131   switch (Opcode) {
132   default: return 0;
133   case BFISD::CALL:     return "BFISD::CALL";
134   case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
135   case BFISD::Wrapper:  return "BFISD::Wrapper";
136   }
137 }
138 
getSetCCResultType(EVT VT) const139 EVT BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
140   // SETCC always sets the CC register. Technically that is an i1 register, but
141   // that type is not legal, so we treat it as an i32 register.
142   return MVT::i32;
143 }
144 
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const145 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
146                                                    SelectionDAG &DAG) const {
147   DebugLoc DL = Op.getDebugLoc();
148   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
149 
150   Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
151   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
152 }
153 
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const154 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
155                                                SelectionDAG &DAG) const {
156   DebugLoc DL = Op.getDebugLoc();
157   int JTI = cast<JumpTableSDNode>(Op)->getIndex();
158 
159   Op = DAG.getTargetJumpTable(JTI, MVT::i32);
160   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
161 }
162 
163 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const164 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
165                                              CallingConv::ID CallConv, bool isVarArg,
166                                             const SmallVectorImpl<ISD::InputArg>
167                                                &Ins,
168                                              DebugLoc dl, SelectionDAG &DAG,
169                                              SmallVectorImpl<SDValue> &InVals)
170                                                const {
171 
172   MachineFunction &MF = DAG.getMachineFunction();
173   MachineFrameInfo *MFI = MF.getFrameInfo();
174 
175   SmallVector<CCValAssign, 16> ArgLocs;
176   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
177 		 getTargetMachine(), ArgLocs, *DAG.getContext());
178   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
179   CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
180 
181   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
182     CCValAssign &VA = ArgLocs[i];
183 
184     if (VA.isRegLoc()) {
185       EVT RegVT = VA.getLocVT();
186       TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
187         BF::PRegisterClass : BF::DRegisterClass;
188       assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
189       assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
190 
191       unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
192       MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
193       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
194 
195       // If this is an 8 or 16-bit value, it is really passed promoted to 32
196       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
197       // right size.
198       if (VA.getLocInfo() == CCValAssign::SExt)
199         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
200                                DAG.getValueType(VA.getValVT()));
201       else if (VA.getLocInfo() == CCValAssign::ZExt)
202         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
203                                DAG.getValueType(VA.getValVT()));
204 
205       if (VA.getLocInfo() != CCValAssign::Full)
206         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
207 
208       InVals.push_back(ArgValue);
209     } else {
210       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
211       unsigned ObjSize = VA.getLocVT().getStoreSize();
212       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
213       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
214       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
215                                    MachinePointerInfo(),
216                                    false, false, 0));
217     }
218   }
219 
220   return Chain;
221 }
222 
223 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,DebugLoc dl,SelectionDAG & DAG) const224 BlackfinTargetLowering::LowerReturn(SDValue Chain,
225                                     CallingConv::ID CallConv, bool isVarArg,
226                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
227                                     const SmallVectorImpl<SDValue> &OutVals,
228                                     DebugLoc dl, SelectionDAG &DAG) const {
229 
230   // CCValAssign - represent the assignment of the return value to locations.
231   SmallVector<CCValAssign, 16> RVLocs;
232 
233   // CCState - Info about the registers and stack slot.
234   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
235 		 DAG.getTarget(), RVLocs, *DAG.getContext());
236 
237   // Analize return values.
238   CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
239 
240   // If this is the first return lowered for this function, add the regs to the
241   // liveout set for the function.
242   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
243     for (unsigned i = 0; i != RVLocs.size(); ++i)
244       DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
245   }
246 
247   SDValue Flag;
248 
249   // Copy the result values into the output registers.
250   for (unsigned i = 0; i != RVLocs.size(); ++i) {
251     CCValAssign &VA = RVLocs[i];
252     assert(VA.isRegLoc() && "Can only return in registers!");
253     SDValue Opi = OutVals[i];
254 
255     // Expand to i32 if necessary
256     switch (VA.getLocInfo()) {
257     default: llvm_unreachable("Unknown loc info!");
258     case CCValAssign::Full: break;
259     case CCValAssign::SExt:
260       Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
261       break;
262     case CCValAssign::ZExt:
263       Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
264       break;
265     case CCValAssign::AExt:
266       Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
267       break;
268     }
269     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
270     // Guarantee that all emitted copies are stuck together with flags.
271     Flag = Chain.getValue(1);
272   }
273 
274   if (Flag.getNode()) {
275     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
276   } else {
277     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
278   }
279 }
280 
281 SDValue
LowerCall(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool & isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,DebugLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const282 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
283                                   CallingConv::ID CallConv, bool isVarArg,
284                                   bool &isTailCall,
285                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
286                                   const SmallVectorImpl<SDValue> &OutVals,
287                                   const SmallVectorImpl<ISD::InputArg> &Ins,
288                                   DebugLoc dl, SelectionDAG &DAG,
289                                   SmallVectorImpl<SDValue> &InVals) const {
290   // Blackfin target does not yet support tail call optimization.
291   isTailCall = false;
292 
293   // Analyze operands of the call, assigning locations to each operand.
294   SmallVector<CCValAssign, 16> ArgLocs;
295   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
296 		 DAG.getTarget(), ArgLocs, *DAG.getContext());
297   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
298   CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
299 
300   // Get the size of the outgoing arguments stack space requirement.
301   unsigned ArgsSize = CCInfo.getNextStackOffset();
302 
303   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
304   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
305   SmallVector<SDValue, 8> MemOpChains;
306 
307   // Walk the register/memloc assignments, inserting copies/loads.
308   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
309     CCValAssign &VA = ArgLocs[i];
310     SDValue Arg = OutVals[i];
311 
312     // Promote the value if needed.
313     switch (VA.getLocInfo()) {
314     default: llvm_unreachable("Unknown loc info!");
315     case CCValAssign::Full: break;
316     case CCValAssign::SExt:
317       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
318       break;
319     case CCValAssign::ZExt:
320       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
321       break;
322     case CCValAssign::AExt:
323       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
324       break;
325     }
326 
327     // Arguments that can be passed on register must be kept at
328     // RegsToPass vector
329     if (VA.isRegLoc()) {
330       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
331     } else {
332       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
333       int Offset = VA.getLocMemOffset();
334       assert(Offset%4 == 0 && "Unaligned LocMemOffset");
335       assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
336       SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
337       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
338       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
339       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
340                                          MachinePointerInfo(),false, false, 0));
341     }
342   }
343 
344   // Transform all store nodes into one single node because
345   // all store nodes are independent of each other.
346   if (!MemOpChains.empty())
347     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
348                         &MemOpChains[0], MemOpChains.size());
349 
350   // Build a sequence of copy-to-reg nodes chained together with token
351   // chain and flag operands which copy the outgoing args into registers.
352   // The InFlag in necessary since all emitted instructions must be
353   // stuck together.
354   SDValue InFlag;
355   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
356     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
357                              RegsToPass[i].second, InFlag);
358     InFlag = Chain.getValue(1);
359   }
360 
361   // If the callee is a GlobalAddress node (quite common, every direct call is)
362   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
363   // Likewise ExternalSymbol -> TargetExternalSymbol.
364   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
365     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
366   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
367     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
368 
369   std::vector<EVT> NodeTys;
370   NodeTys.push_back(MVT::Other);   // Returns a chain
371   NodeTys.push_back(MVT::Glue);    // Returns a flag for retval copy to use.
372   SDValue Ops[] = { Chain, Callee, InFlag };
373   Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
374                       InFlag.getNode() ? 3 : 2);
375   InFlag = Chain.getValue(1);
376 
377   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
378                              DAG.getIntPtrConstant(0, true), InFlag);
379   InFlag = Chain.getValue(1);
380 
381   // Assign locations to each value returned by this call.
382   SmallVector<CCValAssign, 16> RVLocs;
383   CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
384 		 DAG.getTarget(), RVLocs, *DAG.getContext());
385 
386   RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
387 
388   // Copy all of the result registers out of their specified physreg.
389   for (unsigned i = 0; i != RVLocs.size(); ++i) {
390     CCValAssign &RV = RVLocs[i];
391     unsigned Reg = RV.getLocReg();
392 
393     Chain = DAG.getCopyFromReg(Chain, dl, Reg,
394                                RVLocs[i].getLocVT(), InFlag);
395     SDValue Val = Chain.getValue(0);
396     InFlag = Chain.getValue(2);
397     Chain = Chain.getValue(1);
398 
399     // Callee is responsible for extending any i16 return values.
400     switch (RV.getLocInfo()) {
401     case CCValAssign::SExt:
402       Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
403                         DAG.getValueType(RV.getValVT()));
404       break;
405     case CCValAssign::ZExt:
406       Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
407                         DAG.getValueType(RV.getValVT()));
408       break;
409     default:
410       break;
411     }
412 
413     // Truncate to valtype
414     if (RV.getLocInfo() != CCValAssign::Full)
415       Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
416     InVals.push_back(Val);
417   }
418 
419   return Chain;
420 }
421 
422 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
423 // add-with-carry instructions.
LowerADDE(SDValue Op,SelectionDAG & DAG) const424 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
425   // Operands: lhs, rhs, carry-in (AC0 flag)
426   // Results: sum, carry-out (AC0 flag)
427   DebugLoc dl = Op.getDebugLoc();
428 
429   unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
430 
431   // zext incoming carry flag in AC0 to 32 bits
432   SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
433                                        /* flag= */ Op.getOperand(2));
434   CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
435                                SDValue(CarryIn, 0));
436 
437   // Add operands, produce sum and carry flag
438   SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
439                                    Op.getOperand(0), Op.getOperand(1));
440 
441   // Store intermediate carry from Sum
442   SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
443                                       /* flag= */ SDValue(Sum, 1));
444 
445   // Add incoming carry, again producing an output flag
446   Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
447                            SDValue(Sum, 0), SDValue(CarryIn, 0));
448 
449   // Update AC0 with the intermediate carry, producing a flag.
450   SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Glue,
451                                         SDValue(Carry1, 0));
452 
453   // Compose (i32, flag) pair
454   SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
455   return DAG.getMergeValues(ops, 2, dl);
456 }
457 
LowerOperation(SDValue Op,SelectionDAG & DAG) const458 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
459                                                SelectionDAG &DAG) const {
460   switch (Op.getOpcode()) {
461   default:
462     Op.getNode()->dump();
463     llvm_unreachable("Should not custom lower this!");
464   case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
465   case ISD::GlobalTLSAddress:
466     llvm_unreachable("TLS not implemented for Blackfin.");
467   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
468     // Frame & Return address.  Currently unimplemented
469   case ISD::FRAMEADDR:          return SDValue();
470   case ISD::RETURNADDR:         return SDValue();
471   case ISD::ADDE:
472   case ISD::SUBE:               return LowerADDE(Op, DAG);
473   }
474 }
475 
476 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const477 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
478                                            SmallVectorImpl<SDValue> &Results,
479                                            SelectionDAG &DAG) const {
480   DebugLoc dl = N->getDebugLoc();
481   switch (N->getOpcode()) {
482   default:
483     llvm_unreachable("Do not know how to custom type legalize this operation!");
484     return;
485   case ISD::READCYCLECOUNTER: {
486     // The low part of the cycle counter is in CYCLES, the high part in
487     // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
488     // CYCLES2 last.
489     SDValue TheChain = N->getOperand(0);
490     SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
491     SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
492     // Use a buildpair to merge the two 32-bit values into a 64-bit one.
493     Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
494     // Outgoing chain. If we were to use the chain from lo instead, it would be
495     // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
496     // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
497     // read beyond the next CYCLES read, leading to invalid results.
498     Results.push_back(hi.getValue(1));
499     return;
500   }
501   }
502 }
503 
504 //===----------------------------------------------------------------------===//
505 //                         Blackfin Inline Assembly Support
506 //===----------------------------------------------------------------------===//
507 
508 /// getConstraintType - Given a constraint letter, return the type of
509 /// constraint it is for this target.
510 BlackfinTargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const511 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
512   if (Constraint.size() != 1)
513     return TargetLowering::getConstraintType(Constraint);
514 
515   switch (Constraint[0]) {
516     // Standard constraints
517   case 'r':
518     return C_RegisterClass;
519 
520     // Blackfin-specific constraints
521   case 'a':
522   case 'd':
523   case 'z':
524   case 'D':
525   case 'W':
526   case 'e':
527   case 'b':
528   case 'v':
529   case 'f':
530   case 'c':
531   case 't':
532   case 'u':
533   case 'k':
534   case 'x':
535   case 'y':
536   case 'w':
537     return C_RegisterClass;
538   case 'A':
539   case 'B':
540   case 'C':
541   case 'Z':
542   case 'Y':
543     return C_Register;
544   }
545 
546   // Not implemented: q0-q7, qA. Use {R2} etc instead
547 
548   return TargetLowering::getConstraintType(Constraint);
549 }
550 
551 /// Examine constraint type and operand type and determine a weight value.
552 /// This object must already have been set up with the operand type
553 /// and the current alternative constraint selected.
554 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const555 BlackfinTargetLowering::getSingleConstraintMatchWeight(
556     AsmOperandInfo &info, const char *constraint) const {
557   ConstraintWeight weight = CW_Invalid;
558   Value *CallOperandVal = info.CallOperandVal;
559     // If we don't have a value, we can't do a match,
560     // but allow it at the lowest weight.
561   if (CallOperandVal == NULL)
562     return CW_Default;
563   // Look at the constraint type.
564   switch (*constraint) {
565   default:
566     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
567     break;
568 
569     // Blackfin-specific constraints
570   case 'a':
571   case 'd':
572   case 'z':
573   case 'D':
574   case 'W':
575   case 'e':
576   case 'b':
577   case 'v':
578   case 'f':
579   case 'c':
580   case 't':
581   case 'u':
582   case 'k':
583   case 'x':
584   case 'y':
585   case 'w':
586     return CW_Register;
587   case 'A':
588   case 'B':
589   case 'C':
590   case 'Z':
591   case 'Y':
592     return CW_SpecificReg;
593   }
594   return weight;
595 }
596 
597 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
598 /// constraint.
599 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
getRegForInlineAsmConstraint(const std::string & Constraint,EVT VT) const600 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
601   typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
602   using namespace BF;
603 
604   if (Constraint.size() != 1)
605     return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
606 
607   switch (Constraint[0]) {
608     // Standard constraints
609   case 'r':
610     return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
611 
612     // Blackfin-specific constraints
613   case 'a': return Pair(0U, PRegisterClass);
614   case 'd': return Pair(0U, DRegisterClass);
615   case 'e': return Pair(0U, AccuRegisterClass);
616   case 'A': return Pair(A0, AccuRegisterClass);
617   case 'B': return Pair(A1, AccuRegisterClass);
618   case 'b': return Pair(0U, IRegisterClass);
619   case 'v': return Pair(0U, BRegisterClass);
620   case 'f': return Pair(0U, MRegisterClass);
621   case 'C': return Pair(CC, JustCCRegisterClass);
622   case 'x': return Pair(0U, GRRegisterClass);
623   case 'w': return Pair(0U, ALLRegisterClass);
624   case 'Z': return Pair(P3, PRegisterClass);
625   case 'Y': return Pair(P1, PRegisterClass);
626   case 'z': return Pair(0U, zConsRegisterClass);
627   case 'D': return Pair(0U, DConsRegisterClass);
628   case 'W': return Pair(0U, WConsRegisterClass);
629   case 'c': return Pair(0U, cConsRegisterClass);
630   case 't': return Pair(0U, tConsRegisterClass);
631   case 'u': return Pair(0U, uConsRegisterClass);
632   case 'k': return Pair(0U, kConsRegisterClass);
633   case 'y': return Pair(0U, yConsRegisterClass);
634   }
635 
636   // Not implemented: q0-q7, qA. Use {R2} etc instead.
637 
638   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
639 }
640 
641 bool BlackfinTargetLowering::
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const642 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
643   // The Blackfin target isn't yet aware of offsets.
644   return false;
645 }
646