1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * keystone2: common clock header file 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9 #ifndef __ASM_ARCH_CLOCK_H 10 #define __ASM_ARCH_CLOCK_H 11 12 #ifndef __ASSEMBLY__ 13 14 #ifdef CONFIG_SOC_K2HK 15 #include <asm/arch/clock-k2hk.h> 16 #endif 17 18 #ifdef CONFIG_SOC_K2E 19 #include <asm/arch/clock-k2e.h> 20 #endif 21 22 #ifdef CONFIG_SOC_K2L 23 #include <asm/arch/clock-k2l.h> 24 #endif 25 26 #ifdef CONFIG_SOC_K2G 27 #include <asm/arch/clock-k2g.h> 28 #endif 29 30 #define CORE_PLL MAIN_PLL 31 #define DDR3_PLL DDR3A_PLL 32 #define NSS_PLL PASS_PLL 33 34 #define CLK_LIST(CLK)\ 35 CLK(0, core_pll_clk)\ 36 CLK(1, pass_pll_clk)\ 37 CLK(2, tetris_pll_clk)\ 38 CLK(3, ddr3a_pll_clk)\ 39 CLK(4, ddr3b_pll_clk)\ 40 CLK(5, sys_clk0_clk)\ 41 CLK(6, sys_clk0_1_clk)\ 42 CLK(7, sys_clk0_2_clk)\ 43 CLK(8, sys_clk0_3_clk)\ 44 CLK(9, sys_clk0_4_clk)\ 45 CLK(10, sys_clk0_6_clk)\ 46 CLK(11, sys_clk0_8_clk)\ 47 CLK(12, sys_clk0_12_clk)\ 48 CLK(13, sys_clk0_24_clk)\ 49 CLK(14, sys_clk1_clk)\ 50 CLK(15, sys_clk1_3_clk)\ 51 CLK(16, sys_clk1_4_clk)\ 52 CLK(17, sys_clk1_6_clk)\ 53 CLK(18, sys_clk1_12_clk)\ 54 CLK(19, sys_clk2_clk)\ 55 CLK(20, sys_clk3_clk)\ 56 CLK(21, uart_pll_clk) 57 58 #include <asm/types.h> 59 60 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, 61 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" 62 #define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) 63 64 enum { 65 SPD200, 66 SPD400, 67 SPD600, 68 SPD800, 69 SPD850, 70 SPD900, 71 SPD1000, 72 SPD1200, 73 SPD1250, 74 SPD1350, 75 SPD1400, 76 SPD1500, 77 NUM_SPDS, 78 }; 79 80 /* PLL identifiers */ 81 enum { 82 MAIN_PLL, 83 TETRIS_PLL, 84 PASS_PLL, 85 DDR3A_PLL, 86 DDR3B_PLL, 87 UART_PLL, 88 MAX_PLL_COUNT, 89 }; 90 91 enum ext_clk_e { 92 sys_clk, 93 alt_core_clk, 94 pa_clk, 95 tetris_clk, 96 ddr3a_clk, 97 ddr3b_clk, 98 uart_clk, 99 ext_clk_count /* number of external clocks */ 100 }; 101 102 enum clk_e { 103 CLK_LIST(GENERATE_ENUM) 104 }; 105 106 struct keystone_pll_regs { 107 u32 reg0; 108 u32 reg1; 109 }; 110 111 /* PLL configuration data */ 112 struct pll_init_data { 113 int pll; 114 int pll_m; /* PLL Multiplier */ 115 int pll_d; /* PLL divider */ 116 int pll_od; /* PLL output divider */ 117 }; 118 119 extern const struct keystone_pll_regs keystone_pll_regs[]; 120 extern s16 divn_val[]; 121 extern int speeds[]; 122 123 void init_plls(void); 124 void init_pll(const struct pll_init_data *data); 125 struct pll_init_data *get_pll_init_data(int pll); 126 unsigned long ks_clk_get_rate(unsigned int clk); 127 int get_max_dev_speed(int *spds); 128 int get_max_arm_speed(int *spds); 129 void pll_pa_clk_sel(void); 130 unsigned int get_external_clk(u32 clk); 131 132 #endif 133 #endif 134