| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 120 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc()); in TEST() local
158 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { in checkHashAndIsEqualMatch()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 360 bool VLIWPacketizerList::alias(const MachineInstr &MI1, in alias()
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| D | TargetInstrInfo.cpp | 422 const MachineInstr &MI1, in produceSameValue()
678 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
693 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| D | MachineInstr.cpp | 336 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 284 const MachineInstr *MI1; ///< Second instruction involved in the LOH member
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 392 static bool ConsecutiveInstr(MachineInstr *MI1, MachineInstr *MI2) { in ConsecutiveInstr()
458 MachineInstr *MI1 = Arguments->MI; in ReduceXWtoXWP() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 386 const MachineInstr &MI1, in produceSameValue()
570 MachineInstr *MI1 = nullptr; in hasReassociableOperands() local
585 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling() local
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| D | MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs()
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| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 364 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TargetInstrInfoImpl.cpp | 214 const MachineInstr *MI1, in produceSameValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 391 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1, in getAddrDispShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.cpp | 651 MachineInstr &MI1 = *SUa->getInstr(); in apply() local
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| D | SIFixSGPRCopies.cpp | 477 MachineInstr *MI1 = *I1; in hoistAndMergeSGPRInits() local
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| D | SIInstrInfo.cpp | 376 static bool memOpsHaveSameBasePtr(const MachineInstr &MI1, unsigned BaseReg1, in memOpsHaveSameBasePtr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 147 MachineInstr &MI1 = *SU.getInstr(); in apply() local
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| D | HexagonVLIWPacketizer.cpp | 960 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2560 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1, in isToBeScheduledASAP()
2877 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1, in addLatencyToSchedule()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 844 bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2932 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr *MI1, in addLatencyToSchedule()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1164 const MachineInstr *MI1, in produceSameValue()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1451 const MachineInstr &MI1, in produceSameValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1629 const MachineInstr &MI1, in produceSameValue()
|