1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16
17 #ifndef ARMBASEINFO_H
18 #define ARMBASEINFO_H
19
20 #include "ARMMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
22
23 namespace llvm {
24
25 // Enums corresponding to ARM condition codes
26 namespace ARMCC {
27 // The CondCodes constants map directly to the 4-bit encoding of the
28 // condition field for predicated instructions.
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
30 EQ, // Equal Equal
31 NE, // Not equal Not equal, or unordered
32 HS, // Carry set >, ==, or unordered
33 LO, // Carry clear Less than
34 MI, // Minus, negative Less than
35 PL, // Plus, positive or zero >, ==, or unordered
36 VS, // Overflow Unordered
37 VC, // No overflow Not unordered
38 HI, // Unsigned higher Greater than, or unordered
39 LS, // Unsigned lower or same Less than or equal
40 GE, // Greater than or equal Greater than or equal
41 LT, // Less than Less than, or unordered
42 GT, // Greater than Greater than
43 LE, // Less than or equal <, ==, or unordered
44 AL // Always (unconditional) Always (unconditional)
45 };
46
getOppositeCondition(CondCodes CC)47 inline static CondCodes getOppositeCondition(CondCodes CC) {
48 switch (CC) {
49 default: llvm_unreachable("Unknown condition code");
50 case EQ: return NE;
51 case NE: return EQ;
52 case HS: return LO;
53 case LO: return HS;
54 case MI: return PL;
55 case PL: return MI;
56 case VS: return VC;
57 case VC: return VS;
58 case HI: return LS;
59 case LS: return HI;
60 case GE: return LT;
61 case LT: return GE;
62 case GT: return LE;
63 case LE: return GT;
64 }
65 }
66 } // namespace ARMCC
67
ARMCondCodeToString(ARMCC::CondCodes CC)68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
69 switch (CC) {
70 default: llvm_unreachable("Unknown condition code");
71 case ARMCC::EQ: return "eq";
72 case ARMCC::NE: return "ne";
73 case ARMCC::HS: return "hs";
74 case ARMCC::LO: return "lo";
75 case ARMCC::MI: return "mi";
76 case ARMCC::PL: return "pl";
77 case ARMCC::VS: return "vs";
78 case ARMCC::VC: return "vc";
79 case ARMCC::HI: return "hi";
80 case ARMCC::LS: return "ls";
81 case ARMCC::GE: return "ge";
82 case ARMCC::LT: return "lt";
83 case ARMCC::GT: return "gt";
84 case ARMCC::LE: return "le";
85 case ARMCC::AL: return "al";
86 }
87 }
88
89 namespace ARM_PROC {
90 enum IMod {
91 IE = 2,
92 ID = 3
93 };
94
95 enum IFlags {
96 F = 1,
97 I = 2,
98 A = 4
99 };
100
IFlagsToString(unsigned val)101 inline static const char *IFlagsToString(unsigned val) {
102 switch (val) {
103 default: llvm_unreachable("Unknown iflags operand");
104 case F: return "f";
105 case I: return "i";
106 case A: return "a";
107 }
108 }
109
IModToString(unsigned val)110 inline static const char *IModToString(unsigned val) {
111 switch (val) {
112 default: llvm_unreachable("Unknown imod operand");
113 case IE: return "ie";
114 case ID: return "id";
115 }
116 }
117 }
118
119 namespace ARM_MB {
120 // The Memory Barrier Option constants map directly to the 4-bit encoding of
121 // the option field for memory barrier operations.
122 enum MemBOpt {
123 SY = 15,
124 ST = 14,
125 ISH = 11,
126 ISHST = 10,
127 NSH = 7,
128 NSHST = 6,
129 OSH = 3,
130 OSHST = 2
131 };
132
MemBOptToString(unsigned val)133 inline static const char *MemBOptToString(unsigned val) {
134 switch (val) {
135 default: llvm_unreachable("Unknown memory operation");
136 case SY: return "sy";
137 case ST: return "st";
138 case ISH: return "ish";
139 case ISHST: return "ishst";
140 case NSH: return "nsh";
141 case NSHST: return "nshst";
142 case OSH: return "osh";
143 case OSHST: return "oshst";
144 }
145 }
146 } // namespace ARM_MB
147
148 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
149 /// ARM::LR, return the number that it corresponds to (e.g. 14).
getARMRegisterNumbering(unsigned Reg)150 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
151 using namespace ARM;
152 switch (Reg) {
153 default:
154 llvm_unreachable("Unknown ARM register!");
155 case R0: case S0: case D0: case Q0: return 0;
156 case R1: case S1: case D1: case Q1: return 1;
157 case R2: case S2: case D2: case Q2: return 2;
158 case R3: case S3: case D3: case Q3: return 3;
159 case R4: case S4: case D4: case Q4: return 4;
160 case R5: case S5: case D5: case Q5: return 5;
161 case R6: case S6: case D6: case Q6: return 6;
162 case R7: case S7: case D7: case Q7: return 7;
163 case R8: case S8: case D8: case Q8: return 8;
164 case R9: case S9: case D9: case Q9: return 9;
165 case R10: case S10: case D10: case Q10: return 10;
166 case R11: case S11: case D11: case Q11: return 11;
167 case R12: case S12: case D12: case Q12: return 12;
168 case SP: case S13: case D13: case Q13: return 13;
169 case LR: case S14: case D14: case Q14: return 14;
170 case PC: case S15: case D15: case Q15: return 15;
171
172 case S16: case D16: return 16;
173 case S17: case D17: return 17;
174 case S18: case D18: return 18;
175 case S19: case D19: return 19;
176 case S20: case D20: return 20;
177 case S21: case D21: return 21;
178 case S22: case D22: return 22;
179 case S23: case D23: return 23;
180 case S24: case D24: return 24;
181 case S25: case D25: return 25;
182 case S26: case D26: return 26;
183 case S27: case D27: return 27;
184 case S28: case D28: return 28;
185 case S29: case D29: return 29;
186 case S30: case D30: return 30;
187 case S31: case D31: return 31;
188 }
189 }
190
191 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
192 ///
isARMLowRegister(unsigned Reg)193 static inline bool isARMLowRegister(unsigned Reg) {
194 using namespace ARM;
195 switch (Reg) {
196 case R0: case R1: case R2: case R3:
197 case R4: case R5: case R6: case R7:
198 return true;
199 default:
200 return false;
201 }
202 }
203
204 /// ARMII - This namespace holds all of the target specific flags that
205 /// instruction info tracks.
206 ///
207 namespace ARMII {
208
209 /// ARM Index Modes
210 enum IndexMode {
211 IndexModeNone = 0,
212 IndexModePre = 1,
213 IndexModePost = 2,
214 IndexModeUpd = 3
215 };
216
217 /// ARM Addressing Modes
218 enum AddrMode {
219 AddrModeNone = 0,
220 AddrMode1 = 1,
221 AddrMode2 = 2,
222 AddrMode3 = 3,
223 AddrMode4 = 4,
224 AddrMode5 = 5,
225 AddrMode6 = 6,
226 AddrModeT1_1 = 7,
227 AddrModeT1_2 = 8,
228 AddrModeT1_4 = 9,
229 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
230 AddrModeT2_i12 = 11,
231 AddrModeT2_i8 = 12,
232 AddrModeT2_so = 13,
233 AddrModeT2_pc = 14, // +/- i12 for pc relative data
234 AddrModeT2_i8s4 = 15, // i8 * 4
235 AddrMode_i12 = 16
236 };
237
AddrModeToString(AddrMode addrmode)238 inline static const char *AddrModeToString(AddrMode addrmode) {
239 switch (addrmode) {
240 default: llvm_unreachable("Unknown memory operation");
241 case AddrModeNone: return "AddrModeNone";
242 case AddrMode1: return "AddrMode1";
243 case AddrMode2: return "AddrMode2";
244 case AddrMode3: return "AddrMode3";
245 case AddrMode4: return "AddrMode4";
246 case AddrMode5: return "AddrMode5";
247 case AddrMode6: return "AddrMode6";
248 case AddrModeT1_1: return "AddrModeT1_1";
249 case AddrModeT1_2: return "AddrModeT1_2";
250 case AddrModeT1_4: return "AddrModeT1_4";
251 case AddrModeT1_s: return "AddrModeT1_s";
252 case AddrModeT2_i12: return "AddrModeT2_i12";
253 case AddrModeT2_i8: return "AddrModeT2_i8";
254 case AddrModeT2_so: return "AddrModeT2_so";
255 case AddrModeT2_pc: return "AddrModeT2_pc";
256 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
257 case AddrMode_i12: return "AddrMode_i12";
258 }
259 }
260
261 /// Target Operand Flag enum.
262 enum TOF {
263 //===------------------------------------------------------------------===//
264 // ARM Specific MachineOperand flags.
265
266 MO_NO_FLAG,
267
268 /// MO_LO16 - On a symbol operand, this represents a relocation containing
269 /// lower 16 bit of the address. Used only via movw instruction.
270 MO_LO16,
271
272 /// MO_HI16 - On a symbol operand, this represents a relocation containing
273 /// higher 16 bit of the address. Used only via movt instruction.
274 MO_HI16,
275
276 /// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
277 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
278 /// i.e. "FOO$non_lazy_ptr".
279 /// Used only via movw instruction.
280 MO_LO16_NONLAZY,
281
282 /// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
283 /// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
284 /// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
285 MO_HI16_NONLAZY,
286
287 /// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
288 /// relocation containing lower 16 bit of the PC relative address of the
289 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
290 /// Used only via movw instruction.
291 MO_LO16_NONLAZY_PIC,
292
293 /// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
294 /// relocation containing lower 16 bit of the PC relative address of the
295 /// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
296 /// Used only via movt instruction.
297 MO_HI16_NONLAZY_PIC,
298
299 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
300 /// call operand.
301 MO_PLT
302 };
303
304 enum {
305 //===------------------------------------------------------------------===//
306 // Instruction Flags.
307
308 //===------------------------------------------------------------------===//
309 // This four-bit field describes the addressing mode used.
310 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
311
312 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
313 // and store ops only. Generic "updating" flag is used for ld/st multiple.
314 // The index mode enums are declared in ARMBaseInfo.h
315 IndexModeShift = 5,
316 IndexModeMask = 3 << IndexModeShift,
317
318 //===------------------------------------------------------------------===//
319 // Instruction encoding formats.
320 //
321 FormShift = 7,
322 FormMask = 0x3f << FormShift,
323
324 // Pseudo instructions
325 Pseudo = 0 << FormShift,
326
327 // Multiply instructions
328 MulFrm = 1 << FormShift,
329
330 // Branch instructions
331 BrFrm = 2 << FormShift,
332 BrMiscFrm = 3 << FormShift,
333
334 // Data Processing instructions
335 DPFrm = 4 << FormShift,
336 DPSoRegFrm = 5 << FormShift,
337
338 // Load and Store
339 LdFrm = 6 << FormShift,
340 StFrm = 7 << FormShift,
341 LdMiscFrm = 8 << FormShift,
342 StMiscFrm = 9 << FormShift,
343 LdStMulFrm = 10 << FormShift,
344
345 LdStExFrm = 11 << FormShift,
346
347 // Miscellaneous arithmetic instructions
348 ArithMiscFrm = 12 << FormShift,
349 SatFrm = 13 << FormShift,
350
351 // Extend instructions
352 ExtFrm = 14 << FormShift,
353
354 // VFP formats
355 VFPUnaryFrm = 15 << FormShift,
356 VFPBinaryFrm = 16 << FormShift,
357 VFPConv1Frm = 17 << FormShift,
358 VFPConv2Frm = 18 << FormShift,
359 VFPConv3Frm = 19 << FormShift,
360 VFPConv4Frm = 20 << FormShift,
361 VFPConv5Frm = 21 << FormShift,
362 VFPLdStFrm = 22 << FormShift,
363 VFPLdStMulFrm = 23 << FormShift,
364 VFPMiscFrm = 24 << FormShift,
365
366 // Thumb format
367 ThumbFrm = 25 << FormShift,
368
369 // Miscelleaneous format
370 MiscFrm = 26 << FormShift,
371
372 // NEON formats
373 NGetLnFrm = 27 << FormShift,
374 NSetLnFrm = 28 << FormShift,
375 NDupFrm = 29 << FormShift,
376 NLdStFrm = 30 << FormShift,
377 N1RegModImmFrm= 31 << FormShift,
378 N2RegFrm = 32 << FormShift,
379 NVCVTFrm = 33 << FormShift,
380 NVDupLnFrm = 34 << FormShift,
381 N2RegVShLFrm = 35 << FormShift,
382 N2RegVShRFrm = 36 << FormShift,
383 N3RegFrm = 37 << FormShift,
384 N3RegVShFrm = 38 << FormShift,
385 NVExtFrm = 39 << FormShift,
386 NVMulSLFrm = 40 << FormShift,
387 NVTBLFrm = 41 << FormShift,
388
389 //===------------------------------------------------------------------===//
390 // Misc flags.
391
392 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
393 // it doesn't have a Rn operand.
394 UnaryDP = 1 << 13,
395
396 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
397 // a 16-bit Thumb instruction if certain conditions are met.
398 Xform16Bit = 1 << 14,
399
400 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
401 // instruction. Used by the parser to determine whether to require the 'S'
402 // suffix on the mnemonic (when not in an IT block) or preclude it (when
403 // in an IT block).
404 ThumbArithFlagSetting = 1 << 18,
405
406 //===------------------------------------------------------------------===//
407 // Code domain.
408 DomainShift = 15,
409 DomainMask = 7 << DomainShift,
410 DomainGeneral = 0 << DomainShift,
411 DomainVFP = 1 << DomainShift,
412 DomainNEON = 2 << DomainShift,
413 DomainNEONA8 = 4 << DomainShift,
414
415 //===------------------------------------------------------------------===//
416 // Field shifts - such shifts are used to set field while generating
417 // machine instructions.
418 //
419 // FIXME: This list will need adjusting/fixing as the MC code emitter
420 // takes shape and the ARMCodeEmitter.cpp bits go away.
421 ShiftTypeShift = 4,
422
423 M_BitShift = 5,
424 ShiftImmShift = 5,
425 ShiftShift = 7,
426 N_BitShift = 7,
427 ImmHiShift = 8,
428 SoRotImmShift = 8,
429 RegRsShift = 8,
430 ExtRotImmShift = 10,
431 RegRdLoShift = 12,
432 RegRdShift = 12,
433 RegRdHiShift = 16,
434 RegRnShift = 16,
435 S_BitShift = 20,
436 W_BitShift = 21,
437 AM3_I_BitShift = 22,
438 D_BitShift = 22,
439 U_BitShift = 23,
440 P_BitShift = 24,
441 I_BitShift = 25,
442 CondShift = 28
443 };
444
445 } // end namespace ARMII
446
447 } // end namespace llvm;
448
449 #endif
450