1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * UniPhier DDR MultiPHY registers 4 * 5 * Copyright (C) 2015-2017 Socionext Inc. 6 */ 7 8 #ifndef UNIPHIER_DDRMPHY_REGS_H 9 #define UNIPHIER_DDRMPHY_REGS_H 10 11 #include <linux/bitops.h> 12 13 #define MPHY_SHIFT 2 14 15 #define MPHY_RIDR (0x000 << MPHY_SHIFT) 16 #define MPHY_PIR (0x001 << MPHY_SHIFT) 17 #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */ 18 #define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ 19 #define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ 20 #define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */ 21 #define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */ 22 #define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ 23 #define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ 24 #define MPHY_PIR_WL BIT(9) /* Write Leveling */ 25 #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ 26 #define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ 27 #define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ 28 #define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ 29 #define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ 30 #define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ 31 #define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ 32 #define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ 33 #define MPHY_PGCR0 (0x002 << MPHY_SHIFT) 34 #define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ 35 #define MPHY_PGCR1 (0x003 << MPHY_SHIFT) 36 #define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ 37 #define MPHY_PGCR2 (0x004 << MPHY_SHIFT) 38 #define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ 39 #define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ 40 #define MPHY_PGCR3 (0x005 << MPHY_SHIFT) 41 #define MPHY_PGSR0 (0x006 << MPHY_SHIFT) 42 #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ 43 #define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ 44 #define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ 45 #define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ 46 #define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ 47 #define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ 48 #define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ 49 #define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ 50 #define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ 51 #define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ 52 #define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ 53 #define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ 54 #define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ 55 #define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ 56 #define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ 57 #define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ 58 #define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ 59 #define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ 60 #define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ 61 #define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ 62 #define MPHY_PGSR1 (0x007 << MPHY_SHIFT) 63 #define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ 64 #define MPHY_PLLCR (0x008 << MPHY_SHIFT) 65 #define MPHY_PTR0 (0x009 << MPHY_SHIFT) 66 #define MPHY_PTR1 (0x00A << MPHY_SHIFT) 67 #define MPHY_PTR2 (0x00B << MPHY_SHIFT) 68 #define MPHY_PTR3 (0x00C << MPHY_SHIFT) 69 #define MPHY_PTR4 (0x00D << MPHY_SHIFT) 70 #define MPHY_ACMDLR (0x00E << MPHY_SHIFT) 71 #define MPHY_ACLCDLR (0x00F << MPHY_SHIFT) 72 #define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT) 73 #define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT) 74 #define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT) 75 #define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT) 76 #define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT) 77 #define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT) 78 #define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT) 79 #define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT) 80 #define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT) 81 #define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT) 82 #define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT) 83 #define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT) 84 #define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT) 85 #define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT) 86 #define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT) 87 #define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT) 88 #define MPHY_DXCCR (0x020 << MPHY_SHIFT) 89 #define MPHY_DSGCR (0x021 << MPHY_SHIFT) 90 #define MPHY_DCR (0x022 << MPHY_SHIFT) 91 #define MPHY_DTPR0 (0x023 << MPHY_SHIFT) 92 #define MPHY_DTPR1 (0x024 << MPHY_SHIFT) 93 #define MPHY_DTPR2 (0x025 << MPHY_SHIFT) 94 #define MPHY_DTPR3 (0x026 << MPHY_SHIFT) 95 #define MPHY_MR0 (0x027 << MPHY_SHIFT) 96 #define MPHY_MR1 (0x028 << MPHY_SHIFT) 97 #define MPHY_MR2 (0x029 << MPHY_SHIFT) 98 #define MPHY_MR3 (0x02A << MPHY_SHIFT) 99 #define MPHY_ODTCR (0x02B << MPHY_SHIFT) 100 #define MPHY_DTCR (0x02C << MPHY_SHIFT) 101 #define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ 102 #define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT)) 103 #define MPHY_DTAR0 (0x02D << MPHY_SHIFT) 104 #define MPHY_DTAR1 (0x02E << MPHY_SHIFT) 105 #define MPHY_DTAR2 (0x02F << MPHY_SHIFT) 106 #define MPHY_DTAR3 (0x030 << MPHY_SHIFT) 107 #define MPHY_DTDR0 (0x031 << MPHY_SHIFT) 108 #define MPHY_DTDR1 (0x032 << MPHY_SHIFT) 109 #define MPHY_DTEDR0 (0x033 << MPHY_SHIFT) 110 #define MPHY_DTEDR1 (0x034 << MPHY_SHIFT) 111 #define MPHY_ZQCR (0x090 << MPHY_SHIFT) 112 #define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ 113 #define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ 114 /* ZQ */ 115 #define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT) 116 #define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT) 117 #define MPHY_ZQ_PR (0x000 << MPHY_SHIFT) 118 #define MPHY_ZQ_DR (0x001 << MPHY_SHIFT) 119 #define MPHY_ZQ_SR (0x002 << MPHY_SHIFT) 120 /* DATX8 */ 121 #define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT) 122 #define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT) 123 #define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT) 124 #define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 125 #define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT)) 126 #define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT) 127 #define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT) 128 #define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT) 129 #define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT) 130 #define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT) 131 #define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT) 132 #define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT) 133 #define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT) 134 #define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT) 135 #define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT) 136 #define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT) 137 #define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT) 138 #define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT) 139 #define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT) 140 #define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT) 141 #define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT) 142 #define MPHY_DX_MDLR (0x011 << MPHY_SHIFT) 143 #define MPHY_DX_GTR (0x012 << MPHY_SHIFT) 144 145 #endif /* UNIPHIER_DDRMPHY_REGS_H */ 146