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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #define MXC_CPU_MX23		0x23
7 #define MXC_CPU_MX25		0x25
8 #define MXC_CPU_MX27		0x27
9 #define MXC_CPU_MX28		0x28
10 #define MXC_CPU_MX31		0x31
11 #define MXC_CPU_MX35		0x35
12 #define MXC_CPU_MX51		0x51
13 #define MXC_CPU_MX53		0x53
14 #define MXC_CPU_MX6SL		0x60
15 #define MXC_CPU_MX6DL		0x61
16 #define MXC_CPU_MX6SX		0x62
17 #define MXC_CPU_MX6Q		0x63
18 #define MXC_CPU_MX6UL		0x64
19 #define MXC_CPU_MX6ULL		0x65
20 #define MXC_CPU_MX6SOLO		0x66 /* dummy */
21 #define MXC_CPU_MX6SLL		0x67
22 #define MXC_CPU_MX6D		0x6A
23 #define MXC_CPU_MX6DP		0x68
24 #define MXC_CPU_MX6QP		0x69
25 #define MXC_CPU_MX7S		0x71 /* dummy ID */
26 #define MXC_CPU_MX7D		0x72
27 #define MXC_CPU_MX8MQ		0x82
28 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
29 #define MXC_CPU_VF610		0xF6 /* dummy ID */
30 
31 #define MXC_SOC_MX6		0x60
32 #define MXC_SOC_MX7		0x70
33 #define MXC_SOC_MX8M		0x80
34 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
35 
36 #define CHIP_REV_1_0            0x10
37 #define CHIP_REV_1_1            0x11
38 #define CHIP_REV_1_2            0x12
39 #define CHIP_REV_1_5            0x15
40 #define CHIP_REV_2_0            0x20
41 #define CHIP_REV_2_5            0x25
42 #define CHIP_REV_3_0            0x30
43 
44 #define BOARD_REV_1_0           0x0
45 #define BOARD_REV_2_0           0x1
46 #define BOARD_VER_OFFSET        0x8
47 
48 #define CS0_128					0
49 #define CS0_64M_CS1_64M				1
50 #define CS0_64M_CS1_32M_CS2_32M			2
51 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
52 
53 u32 get_imx_reset_cause(void);
54 ulong get_systemPLLCLK(void);
55 ulong get_FCLK(void);
56 ulong get_HCLK(void);
57 ulong get_BCLK(void);
58 ulong get_PERCLK1(void);
59 ulong get_PERCLK2(void);
60 ulong get_PERCLK3(void);
61