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1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _DDR3_TRAINING_IP_FLOW_H_
7 #define _DDR3_TRAINING_IP_FLOW_H_
8 
9 #include "ddr3_training_ip.h"
10 #include "ddr3_training_ip_pbs.h"
11 #include "mv_ddr_regs.h"
12 
13 #define KILLER_PATTERN_LENGTH		32
14 #define EXT_ACCESS_BURST_LENGTH		8
15 
16 #define IS_ACTIVE(mask, id) \
17 	((mask) & (1 << (id)))
18 
19 #define VALIDATE_ACTIVE(mask, id)		\
20 	{					\
21 	if (IS_ACTIVE(mask, id) == 0)		\
22 		continue;			\
23 	}
24 
25 #define IS_IF_ACTIVE(if_mask, if_id) \
26 	((if_mask) & (1 << (if_id)))
27 
28 #define VALIDATE_IF_ACTIVE(mask, id)		\
29 	{					\
30 	if (IS_IF_ACTIVE(mask, id) == 0)	\
31 		continue;			\
32 	}
33 
34 #define IS_BUS_ACTIVE(if_mask , if_id) \
35 	(((if_mask) >> (if_id)) & 1)
36 
37 #define VALIDATE_BUS_ACTIVE(mask, id)		\
38 	{					\
39 	if (IS_BUS_ACTIVE(mask, id) == 0)	\
40 		continue;			\
41 	}
42 
43 #define DDR3_IS_ECC_PUP3_MODE(if_mask) \
44 	(((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
45 
46 #define DDR3_IS_ECC_PUP4_MODE(if_mask) \
47 	((if_mask == BUS_MASK_32BIT_ECC || if_mask == BUS_MASK_16BIT_ECC) ? 1 : 0)
48 
49 #define DDR3_IS_16BIT_DRAM_MODE(mask) \
50 	((mask == BUS_MASK_16BIT || mask == BUS_MASK_16BIT_ECC || mask == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
51 
52 #define DDR3_IS_ECC_PUP8_MODE(if_mask) \
53 	((if_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || if_mask == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
54 
55 #define MV_DDR_IS_64BIT_DRAM_MODE(mask) \
56 	((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \
57 	(((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
58 
59 #define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \
60 	((octets_per_if_num == 9/* FIXME: get from ATF */) && \
61 	((mask == BUS_MASK_32BIT) || \
62 	(mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
63 
64 #define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, octets_per_if_num/* FIXME: get from ATF */) \
65 	(MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, octets_per_if_num) || DDR3_IS_16BIT_DRAM_MODE(mask))
66 
67 #define ECC_READ_BUS_0			0
68 #define ECC_PHY_ACCESS_3		3
69 #define ECC_PHY_ACCESS_4		4
70 #define ECC_PHY_ACCESS_8		8
71 #define MEGA				1000000
72 #define BUS_WIDTH_IN_BITS		8
73 #define MAX_POLLING_ITERATIONS		1000000
74 #define NUM_OF_CS			4
75 #define ADLL_LENGTH			32
76 
77 #define GP_RSVD0_REG			0x182e0
78 
79 /*
80  * DFX address Space
81  * Table 2: DFX address space
82  * Address Bits   Value   Description
83  * [31 : 20]   0x? DFX base address bases PCIe mapping
84  * [19 : 15]   0...Number_of_client-1   Client Index inside pipe.
85  *             See also Table 1 Multi_cast = 29 Broadcast = 28
86  * [14 : 13]   2'b01   Access to Client Internal Register
87  * [12 : 0]   Client Internal Register offset   See related Client Registers
88  * [14 : 13]   2'b00   Access to Ram Wrappers Internal Register
89  * [12 : 6]   0 Number_of_rams-1   Ram Index inside Client
90  * [5 : 0]   Ram Wrapper Internal Register offset   See related Ram Wrappers
91  * Registers
92  */
93 
94 /* nsec */
95 #define  TREFI_LOW				7800
96 #define  TREFI_HIGH				3900
97 #define AUTO_ZQC_TIMING				15384
98 
99 enum mr_number {
100 	MR_CMD0,
101 	MR_CMD1,
102 	MR_CMD2,
103 	MR_CMD3,
104 	MR_LAST
105 };
106 
107 struct mv_ddr_mr_data {
108 	u32 cmd;
109 	u32 reg_addr;
110 };
111 
112 struct write_supp_result {
113 	enum hws_wl_supp stage;
114 	int is_pup_fail;
115 };
116 
117 struct page_element {
118 	enum hws_page_size page_size_8bit;
119 	/* page size in 8 bits bus width */
120 	enum hws_page_size page_size_16bit;
121 	/* page size in 16 bits bus width */
122 	u32 ui_page_mask;
123 	/* Mask used in register */
124 };
125 
126 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
127 					  enum hws_ddr_freq frequency,
128 					  u32 *round_trip_delay_arr);
129 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
130 					 enum hws_ddr_freq frequency,
131 					 u32 *total_round_trip_delay_arr);
132 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
133 		      u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
134 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
135 			u32 if_id, u32 exp_value, u32 mask, u32 offset,
136 			u32 poll_tries);
137 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
138 		     u32 if_id, u32 reg_addr, u32 *data, u32 mask);
139 int ddr3_tip_bus_read_modify_write(u32 dev_num,
140 				   enum hws_access_type access_type,
141 				   u32 if_id, u32 phy_id,
142 				   enum hws_ddr_phy phy_type,
143 				   u32 reg_addr, u32 data_value, u32 reg_mask);
144 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
145 		      u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
146 		      u32 *data);
147 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
148 		       u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
149 		       enum hws_ddr_phy e_phy_type, u32 reg_addr,
150 		       u32 data_value);
151 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
152 		      enum hws_ddr_freq memory_freq);
153 int ddr3_tip_adjust_dqs(u32 dev_num);
154 int ddr3_tip_init_controller(u32 dev_num);
155 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
156 		      u32 num_of_bursts, u32 *addr);
157 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
158 		       u32 num_of_bursts, u32 *addr);
159 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
160 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
161 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
162 int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
163 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
164 int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove);
165 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
166 int ddr3_tip_static_init_controller(u32 dev_num);
167 int ddr3_tip_configure_phy(u32 dev_num);
168 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
169 				  u32 if_id, enum hws_pattern pattern,
170 				  u32 load_addr);
171 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
172 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
173 			    u32 if_id, enum hws_dir direction, u32 tx_phases,
174 			    u32 tx_burst_size, u32 rx_phases,
175 			    u32 delay_between_burst, u32 rd_mode, u32 cs_num,
176 			    u32 addr_stress_jump, u32 single_pattern);
177 int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value);
178 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
179 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
180 int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id);
181 int ddr3_tip_reset_fifo_ptr(u32 dev_num);
182 int ddr3_tip_read_pup_value(u32 dev_num,
183 			    u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
184 			    int reg_addr, u32 mask);
185 int ddr3_tip_read_adll_value(u32 dev_num,
186 			     u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
187 			     u32 reg_addr, u32 mask);
188 int ddr3_tip_write_adll_value(u32 dev_num,
189 			      u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
190 			      u32 reg_addr);
191 int ddr3_tip_tune_training_params(u32 dev_num,
192 				  struct tune_train_params *params);
193 struct page_element *mv_ddr_page_tbl_get(void);
194 
195 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */
196