1 #ifndef __NV40_SHADER_H__ 2 #define __NV40_SHADER_H__ 3 4 /* Vertex programs instruction set 5 * 6 * The NV40 instruction set is very similar to NV30. Most fields are in 7 * a slightly different position in the instruction however. 8 * 9 * Merged instructions 10 * In some cases it is possible to put two instructions into one opcode 11 * slot. The rules for when this is OK is not entirely clear to me yet. 12 * 13 * There are separate writemasks and dest temp register fields for each 14 * grouping of instructions. There is however only one field with the 15 * ID of a result register. Writing to temp/result regs is selected by 16 * setting VEC_RESULT/SCA_RESULT. 17 * 18 * Temporary registers 19 * The source/dest temp register fields have been extended by 1 bit, to 20 * give a total of 32 temporary registers. 21 * 22 * Relative Addressing 23 * NV40 can use an address register to index into vertex attribute regs. 24 * This is done by putting the offset value into INPUT_SRC and setting 25 * the INDEX_INPUT flag. 26 * 27 * Conditional execution (see NV_vertex_program{2,3} for details) 28 * There is a second condition code register on NV40, it's use is enabled 29 * by setting the COND_REG_SELECT_1 flag. 30 * 31 * Texture lookup 32 * TODO 33 */ 34 35 /* ---- OPCODE BITS 127:96 / data DWORD 0 --- */ 36 #define NV40_VP_INST_VEC_RESULT (1 << 30) 37 /* uncertain.. */ 38 #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) 39 /* use address reg as index into attribs */ 40 #define NV40_VP_INST_INDEX_INPUT (1 << 27) 41 #define NV40_VP_INST_SATURATE (1 << 26) 42 #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) 43 #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) 44 #define NV40_VP_INST_SRC2_ABS (1 << 23) 45 #define NV40_VP_INST_SRC1_ABS (1 << 22) 46 #define NV40_VP_INST_SRC0_ABS (1 << 21) 47 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15 48 #define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x3F << 15) 49 #define NV40_VP_INST_COND_TEST_ENABLE (1 << 13) 50 #define NV40_VP_INST_COND_SHIFT 10 51 #define NV40_VP_INST_COND_MASK (0x7 << 10) 52 #define NV40_VP_INST_COND_SWZ_X_SHIFT 8 53 #define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8) 54 #define NV40_VP_INST_COND_SWZ_Y_SHIFT 6 55 #define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6) 56 #define NV40_VP_INST_COND_SWZ_Z_SHIFT 4 57 #define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4) 58 #define NV40_VP_INST_COND_SWZ_W_SHIFT 2 59 #define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2) 60 #define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2 61 #define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2) 62 #define NV40_VP_INST_ADDR_SWZ_SHIFT 0 63 #define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0) 64 #define NV40_VP_INST0_KNOWN ( \ 65 NV40_VP_INST_INDEX_INPUT | \ 66 NV40_VP_INST_COND_REG_SELECT_1 | \ 67 NV40_VP_INST_ADDR_REG_SELECT_1 | \ 68 NV40_VP_INST_SRC2_ABS | \ 69 NV40_VP_INST_SRC1_ABS | \ 70 NV40_VP_INST_SRC0_ABS | \ 71 NV40_VP_INST_VEC_DEST_TEMP_MASK | \ 72 NV40_VP_INST_COND_TEST_ENABLE | \ 73 NV40_VP_INST_COND_MASK | \ 74 NV40_VP_INST_COND_SWZ_ALL_MASK | \ 75 NV40_VP_INST_ADDR_SWZ_MASK) 76 77 /* ---- OPCODE BITS 95:64 / data DWORD 1 --- */ 78 #define NV40_VP_INST_VEC_OPCODE_SHIFT 22 79 #define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22) 80 #define NV40_VP_INST_SCA_OPCODE_SHIFT 27 81 #define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27) 82 #define NV40_VP_INST_CONST_SRC_SHIFT 12 83 #define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12) 84 #define NV40_VP_INST_INPUT_SRC_SHIFT 8 85 #define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8) 86 #define NV40_VP_INST_SRC0H_SHIFT 0 87 #define NV40_VP_INST_SRC0H_MASK (0xFF << 0) 88 #define NV40_VP_INST1_KNOWN ( \ 89 NV40_VP_INST_VEC_OPCODE_MASK | \ 90 NV40_VP_INST_SCA_OPCODE_MASK | \ 91 NV40_VP_INST_CONST_SRC_MASK | \ 92 NV40_VP_INST_INPUT_SRC_MASK | \ 93 NV40_VP_INST_SRC0H_MASK \ 94 ) 95 96 /* ---- OPCODE BITS 63:32 / data DWORD 2 --- */ 97 #define NV40_VP_INST_SRC0L_SHIFT 23 98 #define NV40_VP_INST_SRC0L_MASK (0x1FF << 23) 99 #define NV40_VP_INST_SRC1_SHIFT 6 100 #define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6) 101 #define NV40_VP_INST_SRC2H_SHIFT 0 102 #define NV40_VP_INST_SRC2H_MASK (0x3F << 0) 103 #define NV40_VP_INST_IADDRH_SHIFT 0 104 #define NV40_VP_INST_IADDRH_MASK (0x3F << 0) 105 106 /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */ 107 #define NV40_VP_INST_IADDRL_SHIFT 29 108 #define NV40_VP_INST_IADDRL_MASK (7 << 29) 109 #define NV40_VP_INST_SRC2L_SHIFT 21 110 #define NV40_VP_INST_SRC2L_MASK (0x7FF << 21) 111 #define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17 112 #define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17) 113 # define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20) 114 # define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19) 115 # define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18) 116 # define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17) 117 #define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13 118 #define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13) 119 # define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16) 120 # define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15) 121 # define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14) 122 # define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13) 123 #define NV40_VP_INST_SCA_RESULT (1 << 12) 124 #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7 125 #define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7) 126 #define NV40_VP_INST_DEST_SHIFT 2 127 #define NV40_VP_INST_DEST_MASK (31 << 2) 128 # define NV40_VP_INST_DEST_POS 0 129 # define NV40_VP_INST_DEST_COL0 1 130 # define NV40_VP_INST_DEST_COL1 2 131 # define NV40_VP_INST_DEST_BFC0 3 132 # define NV40_VP_INST_DEST_BFC1 4 133 # define NV40_VP_INST_DEST_FOGC 5 134 # define NV40_VP_INST_DEST_PSZ 6 135 # define NV40_VP_INST_DEST_TC0 7 136 # define NV40_VP_INST_DEST_TC(n) (7+n) 137 # define NV40_VP_INST_DEST_TEMP 0x1F 138 #define NV40_VP_INST_INDEX_CONST (1 << 1) 139 #define NV40_VP_INST3_KNOWN ( \ 140 NV40_VP_INST_SRC2L_MASK |\ 141 NV40_VP_INST_SCA_WRITEMASK_MASK |\ 142 NV40_VP_INST_VEC_WRITEMASK_MASK |\ 143 NV40_VP_INST_SCA_DEST_TEMP_MASK |\ 144 NV40_VP_INST_DEST_MASK |\ 145 NV40_VP_INST_INDEX_CONST) 146 147 /* Useful to split the source selection regs into their pieces */ 148 #define NV40_VP_SRC0_HIGH_SHIFT 9 149 #define NV40_VP_SRC0_HIGH_MASK 0x0001FE00 150 #define NV40_VP_SRC0_LOW_MASK 0x000001FF 151 #define NV40_VP_SRC2_HIGH_SHIFT 11 152 #define NV40_VP_SRC2_HIGH_MASK 0x0001F800 153 #define NV40_VP_SRC2_LOW_MASK 0x000007FF 154 155 /* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */ 156 #define NV40_VP_SRC_NEGATE (1 << 16) 157 #define NV40_VP_SRC_SWZ_X_SHIFT 14 158 #define NV40_VP_SRC_SWZ_X_MASK (3 << 14) 159 #define NV40_VP_SRC_SWZ_Y_SHIFT 12 160 #define NV40_VP_SRC_SWZ_Y_MASK (3 << 12) 161 #define NV40_VP_SRC_SWZ_Z_SHIFT 10 162 #define NV40_VP_SRC_SWZ_Z_MASK (3 << 10) 163 #define NV40_VP_SRC_SWZ_W_SHIFT 8 164 #define NV40_VP_SRC_SWZ_W_MASK (3 << 8) 165 #define NV40_VP_SRC_SWZ_ALL_SHIFT 8 166 #define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8) 167 #define NV40_VP_SRC_TEMP_SRC_SHIFT 2 168 #define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2) 169 #define NV40_VP_SRC_REG_TYPE_SHIFT 0 170 #define NV40_VP_SRC_REG_TYPE_MASK (3 << 0) 171 # define NV40_VP_SRC_REG_TYPE_UNK0 0 172 # define NV40_VP_SRC_REG_TYPE_TEMP 1 173 # define NV40_VP_SRC_REG_TYPE_INPUT 2 174 # define NV40_VP_SRC_REG_TYPE_CONST 3 175 176 #include "nv30/nvfx_shader.h" 177 178 #endif 179