1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "llvm/MC/MCInstrDesc.h" 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 15 16 namespace llvm { 17 18 namespace SIInstrFlags { 19 // This needs to be kept in sync with the field bits in InstSI. 20 enum : uint64_t { 21 // Low bits - basic encoding information. 22 SALU = 1 << 0, 23 VALU = 1 << 1, 24 25 // SALU instruction formats. 26 SOP1 = 1 << 2, 27 SOP2 = 1 << 3, 28 SOPC = 1 << 4, 29 SOPK = 1 << 5, 30 SOPP = 1 << 6, 31 32 // VALU instruction formats. 33 VOP1 = 1 << 7, 34 VOP2 = 1 << 8, 35 VOPC = 1 << 9, 36 37 // TODO: Should this be spilt into VOP3 a and b? 38 VOP3 = 1 << 10, 39 VOP3P = 1 << 12, 40 41 VINTRP = 1 << 13, 42 SDWA = 1 << 14, 43 DPP = 1 << 15, 44 45 // Memory instruction formats. 46 MUBUF = 1 << 16, 47 MTBUF = 1 << 17, 48 SMRD = 1 << 18, 49 MIMG = 1 << 19, 50 EXP = 1 << 20, 51 FLAT = 1 << 21, 52 DS = 1 << 22, 53 54 // Pseudo instruction formats. 55 VGPRSpill = 1 << 23, 56 SGPRSpill = 1 << 24, 57 58 // High bits - other information. 59 VM_CNT = UINT64_C(1) << 32, 60 EXP_CNT = UINT64_C(1) << 33, 61 LGKM_CNT = UINT64_C(1) << 34, 62 63 WQM = UINT64_C(1) << 35, 64 DisableWQM = UINT64_C(1) << 36, 65 Gather4 = UINT64_C(1) << 37, 66 SOPK_ZEXT = UINT64_C(1) << 38, 67 SCALAR_STORE = UINT64_C(1) << 39, 68 FIXED_SIZE = UINT64_C(1) << 40, 69 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 70 VOP3_OPSEL = UINT64_C(1) << 42, 71 maybeAtomic = UINT64_C(1) << 43, 72 renamedInGFX9 = UINT64_C(1) << 44, 73 74 // Is a clamp on FP type. 75 FPClamp = UINT64_C(1) << 45, 76 77 // Is an integer clamp 78 IntClamp = UINT64_C(1) << 46, 79 80 // Clamps lo component of register. 81 ClampLo = UINT64_C(1) << 47, 82 83 // Clamps hi component of register. 84 // ClampLo and ClampHi set for packed clamp. 85 ClampHi = UINT64_C(1) << 48, 86 87 // Is a packed VOP3P instruction. 88 IsPacked = UINT64_C(1) << 49, 89 90 // Is a D16 buffer instruction. 91 D16Buf = UINT64_C(1) << 50 92 }; 93 94 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 95 // The result is true if any of these tests are true. 96 enum ClassFlags { 97 S_NAN = 1 << 0, // Signaling NaN 98 Q_NAN = 1 << 1, // Quiet NaN 99 N_INFINITY = 1 << 2, // Negative infinity 100 N_NORMAL = 1 << 3, // Negative normal 101 N_SUBNORMAL = 1 << 4, // Negative subnormal 102 N_ZERO = 1 << 5, // Negative zero 103 P_ZERO = 1 << 6, // Positive zero 104 P_SUBNORMAL = 1 << 7, // Positive subnormal 105 P_NORMAL = 1 << 8, // Positive normal 106 P_INFINITY = 1 << 9 // Positive infinity 107 }; 108 } 109 110 namespace AMDGPU { 111 enum OperandType { 112 /// Operands with register or 32-bit immediate 113 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 114 OPERAND_REG_IMM_INT64, 115 OPERAND_REG_IMM_INT16, 116 OPERAND_REG_IMM_FP32, 117 OPERAND_REG_IMM_FP64, 118 OPERAND_REG_IMM_FP16, 119 120 /// Operands with register or inline constant 121 OPERAND_REG_INLINE_C_INT16, 122 OPERAND_REG_INLINE_C_INT32, 123 OPERAND_REG_INLINE_C_INT64, 124 OPERAND_REG_INLINE_C_FP16, 125 OPERAND_REG_INLINE_C_FP32, 126 OPERAND_REG_INLINE_C_FP64, 127 OPERAND_REG_INLINE_C_V2FP16, 128 OPERAND_REG_INLINE_C_V2INT16, 129 130 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 131 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16, 132 133 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 134 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_V2INT16, 135 136 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 137 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 138 139 // Operand for source modifiers for VOP instructions 140 OPERAND_INPUT_MODS, 141 142 // Operand for SDWA instructions 143 OPERAND_SDWA_VOPC_DST, 144 145 /// Operand with 32-bit immediate that uses the constant bus. 146 OPERAND_KIMM32, 147 OPERAND_KIMM16 148 }; 149 } 150 151 namespace SIStackID { 152 enum StackTypes : uint8_t { 153 SCRATCH = 0, 154 SGPR_SPILL = 1 155 }; 156 } 157 158 // Input operand modifiers bit-masks 159 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 160 namespace SISrcMods { 161 enum { 162 NEG = 1 << 0, // Floating-point negate modifier 163 ABS = 1 << 1, // Floating-point absolute modifier 164 SEXT = 1 << 0, // Integer sign-extend modifier 165 NEG_HI = ABS, // Floating-point negate high packed component modifier. 166 OP_SEL_0 = 1 << 2, 167 OP_SEL_1 = 1 << 3, 168 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 169 }; 170 } 171 172 namespace SIOutMods { 173 enum { 174 NONE = 0, 175 MUL2 = 1, 176 MUL4 = 2, 177 DIV2 = 3 178 }; 179 } 180 181 namespace VGPRIndexMode { 182 enum { 183 SRC0_ENABLE = 1 << 0, 184 SRC1_ENABLE = 1 << 1, 185 SRC2_ENABLE = 1 << 2, 186 DST_ENABLE = 1 << 3 187 }; 188 } 189 190 namespace AMDGPUAsmVariants { 191 enum { 192 DEFAULT = 0, 193 VOP3 = 1, 194 SDWA = 2, 195 SDWA9 = 3, 196 DPP = 4 197 }; 198 } 199 200 namespace AMDGPU { 201 namespace EncValues { // Encoding values of enum9/8/7 operands 202 203 enum { 204 SGPR_MIN = 0, 205 SGPR_MAX = 101, 206 TTMP_VI_MIN = 112, 207 TTMP_VI_MAX = 123, 208 TTMP_GFX9_MIN = 108, 209 TTMP_GFX9_MAX = 123, 210 INLINE_INTEGER_C_MIN = 128, 211 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 212 INLINE_INTEGER_C_MAX = 208, 213 INLINE_FLOATING_C_MIN = 240, 214 INLINE_FLOATING_C_MAX = 248, 215 LITERAL_CONST = 255, 216 VGPR_MIN = 256, 217 VGPR_MAX = 511 218 }; 219 220 } // namespace EncValues 221 } // namespace AMDGPU 222 223 namespace AMDGPU { 224 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 225 226 enum Id { // Message ID, width(4) [3:0]. 227 ID_UNKNOWN_ = -1, 228 ID_INTERRUPT = 1, 229 ID_GS, 230 ID_GS_DONE, 231 ID_SYSMSG = 15, 232 ID_GAPS_LAST_, // Indicate that sequence has gaps. 233 ID_GAPS_FIRST_ = ID_INTERRUPT, 234 ID_SHIFT_ = 0, 235 ID_WIDTH_ = 4, 236 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 237 }; 238 239 enum Op { // Both GS and SYS operation IDs. 240 OP_UNKNOWN_ = -1, 241 OP_SHIFT_ = 4, 242 // width(2) [5:4] 243 OP_GS_NOP = 0, 244 OP_GS_CUT, 245 OP_GS_EMIT, 246 OP_GS_EMIT_CUT, 247 OP_GS_LAST_, 248 OP_GS_FIRST_ = OP_GS_NOP, 249 OP_GS_WIDTH_ = 2, 250 OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_), 251 // width(3) [6:4] 252 OP_SYS_ECC_ERR_INTERRUPT = 1, 253 OP_SYS_REG_RD, 254 OP_SYS_HOST_TRAP_ACK, 255 OP_SYS_TTRACE_PC, 256 OP_SYS_LAST_, 257 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 258 OP_SYS_WIDTH_ = 3, 259 OP_SYS_MASK_ = (((1 << OP_SYS_WIDTH_) - 1) << OP_SHIFT_) 260 }; 261 262 enum StreamId { // Stream ID, (2) [9:8]. 263 STREAM_ID_DEFAULT_ = 0, 264 STREAM_ID_LAST_ = 4, 265 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 266 STREAM_ID_SHIFT_ = 8, 267 STREAM_ID_WIDTH_= 2, 268 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 269 }; 270 271 } // namespace SendMsg 272 273 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 274 275 enum Id { // HwRegCode, (6) [5:0] 276 ID_UNKNOWN_ = -1, 277 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 278 ID_MODE = 1, 279 ID_STATUS = 2, 280 ID_TRAPSTS = 3, 281 ID_HW_ID = 4, 282 ID_GPR_ALLOC = 5, 283 ID_LDS_ALLOC = 6, 284 ID_IB_STS = 7, 285 ID_MEM_BASES = 15, 286 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 287 ID_SYMBOLIC_LAST_ = 16, 288 ID_SHIFT_ = 0, 289 ID_WIDTH_ = 6, 290 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 291 }; 292 293 enum Offset { // Offset, (5) [10:6] 294 OFFSET_DEFAULT_ = 0, 295 OFFSET_SHIFT_ = 6, 296 OFFSET_WIDTH_ = 5, 297 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 298 299 OFFSET_SRC_SHARED_BASE = 16, 300 OFFSET_SRC_PRIVATE_BASE = 0 301 }; 302 303 enum WidthMinusOne { // WidthMinusOne, (5) [15:11] 304 WIDTH_M1_DEFAULT_ = 31, 305 WIDTH_M1_SHIFT_ = 11, 306 WIDTH_M1_WIDTH_ = 5, 307 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 308 309 WIDTH_M1_SRC_SHARED_BASE = 15, 310 WIDTH_M1_SRC_PRIVATE_BASE = 15 311 }; 312 313 } // namespace Hwreg 314 315 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 316 317 enum Id { // id of symbolic names 318 ID_QUAD_PERM = 0, 319 ID_BITMASK_PERM, 320 ID_SWAP, 321 ID_REVERSE, 322 ID_BROADCAST 323 }; 324 325 enum EncBits { 326 327 // swizzle mode encodings 328 329 QUAD_PERM_ENC = 0x8000, 330 QUAD_PERM_ENC_MASK = 0xFF00, 331 332 BITMASK_PERM_ENC = 0x0000, 333 BITMASK_PERM_ENC_MASK = 0x8000, 334 335 // QUAD_PERM encodings 336 337 LANE_MASK = 0x3, 338 LANE_MAX = LANE_MASK, 339 LANE_SHIFT = 2, 340 LANE_NUM = 4, 341 342 // BITMASK_PERM encodings 343 344 BITMASK_MASK = 0x1F, 345 BITMASK_MAX = BITMASK_MASK, 346 BITMASK_WIDTH = 5, 347 348 BITMASK_AND_SHIFT = 0, 349 BITMASK_OR_SHIFT = 5, 350 BITMASK_XOR_SHIFT = 10 351 }; 352 353 } // namespace Swizzle 354 355 namespace SDWA { 356 357 enum SdwaSel { 358 BYTE_0 = 0, 359 BYTE_1 = 1, 360 BYTE_2 = 2, 361 BYTE_3 = 3, 362 WORD_0 = 4, 363 WORD_1 = 5, 364 DWORD = 6, 365 }; 366 367 enum DstUnused { 368 UNUSED_PAD = 0, 369 UNUSED_SEXT = 1, 370 UNUSED_PRESERVE = 2, 371 }; 372 373 enum SDWA9EncValues{ 374 SRC_SGPR_MASK = 0x100, 375 SRC_VGPR_MASK = 0xFF, 376 VOPC_DST_VCC_MASK = 0x80, 377 VOPC_DST_SGPR_MASK = 0x7F, 378 379 SRC_VGPR_MIN = 0, 380 SRC_VGPR_MAX = 255, 381 SRC_SGPR_MIN = 256, 382 SRC_SGPR_MAX = 357, 383 SRC_TTMP_MIN = 364, 384 SRC_TTMP_MAX = 379, 385 }; 386 387 } // namespace SDWA 388 389 namespace DPP { 390 391 enum DppCtrl { 392 QUAD_PERM_FIRST = 0, 393 QUAD_PERM_LAST = 0xFF, 394 DPP_UNUSED1 = 0x100, 395 ROW_SHL0 = 0x100, 396 ROW_SHL_FIRST = 0x101, 397 ROW_SHL_LAST = 0x10F, 398 DPP_UNUSED2 = 0x110, 399 ROW_SHR0 = 0x110, 400 ROW_SHR_FIRST = 0x111, 401 ROW_SHR_LAST = 0x11F, 402 DPP_UNUSED3 = 0x120, 403 ROW_ROR0 = 0x120, 404 ROW_ROR_FIRST = 0x121, 405 ROW_ROR_LAST = 0x12F, 406 WAVE_SHL1 = 0x130, 407 DPP_UNUSED4_FIRST = 0x131, 408 DPP_UNUSED4_LAST = 0x133, 409 WAVE_ROL1 = 0x134, 410 DPP_UNUSED5_FIRST = 0x135, 411 DPP_UNUSED5_LAST = 0x137, 412 WAVE_SHR1 = 0x138, 413 DPP_UNUSED6_FIRST = 0x139, 414 DPP_UNUSED6_LAST = 0x13B, 415 WAVE_ROR1 = 0x13C, 416 DPP_UNUSED7_FIRST = 0x13D, 417 DPP_UNUSED7_LAST = 0x13F, 418 ROW_MIRROR = 0x140, 419 ROW_HALF_MIRROR = 0x141, 420 BCAST15 = 0x142, 421 BCAST31 = 0x143, 422 DPP_LAST = BCAST31 423 }; 424 425 } // namespace DPP 426 } // namespace AMDGPU 427 428 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 429 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 430 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 431 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 432 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 433 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 434 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 435 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 436 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 437 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 438 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 439 440 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 441 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 442 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 443 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 444 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 445 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 446 #define C_00B84C_USER_SGPR 0xFFFFFFC1 447 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 448 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 449 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 450 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 451 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 452 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 453 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 454 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 455 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 456 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 457 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 458 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 459 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 460 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 461 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 462 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 463 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 464 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 465 /* CIK */ 466 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 467 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 468 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 469 /* */ 470 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 471 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 472 #define C_00B84C_LDS_SIZE 0xFF007FFF 473 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 474 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 475 #define C_00B84C_EXCP_EN 476 477 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 478 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 479 480 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 481 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 482 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 483 #define C_00B848_VGPRS 0xFFFFFFC0 484 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 485 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 486 #define C_00B848_SGPRS 0xFFFFFC3F 487 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 488 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 489 #define C_00B848_PRIORITY 0xFFFFF3FF 490 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 491 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 492 #define C_00B848_FLOAT_MODE 0xFFF00FFF 493 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 494 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 495 #define C_00B848_PRIV 0xFFEFFFFF 496 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 497 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 498 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 499 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 500 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 501 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 502 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 503 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 504 #define C_00B848_IEEE_MODE 0xFF7FFFFF 505 506 507 // Helpers for setting FLOAT_MODE 508 #define FP_ROUND_ROUND_TO_NEAREST 0 509 #define FP_ROUND_ROUND_TO_INF 1 510 #define FP_ROUND_ROUND_TO_NEGINF 2 511 #define FP_ROUND_ROUND_TO_ZERO 3 512 513 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 514 // precision. 515 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 516 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 517 518 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 519 #define FP_DENORM_FLUSH_OUT 1 520 #define FP_DENORM_FLUSH_IN 2 521 #define FP_DENORM_FLUSH_NONE 3 522 523 524 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 525 // precision. 526 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 527 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 528 529 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 530 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 531 532 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 533 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 534 535 #define R_SPILLED_SGPRS 0x4 536 #define R_SPILLED_VGPRS 0x8 537 } // End namespace llvm 538 539 #endif 540