| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
200 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 168 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
224 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 92 const MCPhysReg OffsetReg = X86::R11; in addProlog() local
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| D | X86CallLowering.cpp | 116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 60 unsigned OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); in lowerParameterPtr() local
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| D | R600InstrInfo.cpp | 1041 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1055 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1124 unsigned OffsetReg, in buildIndirectWrite()
1156 unsigned OffsetReg, in buildIndirectRead()
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| D | SIRegisterInfo.cpp | 321 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
674 unsigned OffsetReg = AMDGPU::M0; in spillSGPR() local
844 unsigned OffsetReg = AMDGPU::M0; in restoreSGPR() local
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| D | AMDGPUInstructionSelector.cpp | 556 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectSMRD() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 1059 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1073 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1143 unsigned OffsetReg, in buildIndirectWrite()
1175 unsigned OffsetReg, in buildIndirectRead()
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| D | SIRegisterInfo.cpp | 293 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in materializeFrameBaseRegister() local
346 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in resolveFrameIndex() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 540 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
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| D | Thumb2SizeReduction.cpp | 528 unsigned OffsetReg = 0; in ReduceLoadStore() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
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| D | Thumb2SizeReduction.cpp | 422 unsigned OffsetReg = 0; in ReduceLoadStore() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 562 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
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| D | ARMCallLowering.cpp | 104 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 139 unsigned OffsetReg = MRI.createGenericVirtualRegister(s64); in getStackAddress() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 130 unsigned OffsetReg; member
623 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 115 unsigned OffsetReg; member
608 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 715 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 159 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
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| D | MipsSEInstrInfo.cpp | 880 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 147 unsigned OffsetReg = MI->getOperand(2).getReg(); in canRemoveAddasl() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 166 unsigned OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 614 unsigned OffsetReg = in translateGetElementPtr() local
648 unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset)); in translateGetElementPtr() local
|