| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.cpp | 63 template <> const char *InstMIPS32Abs_d::Opcode = "abs.d"; member in Ice::MIPS32::InstMIPS32Abs_d
64 template <> const char *InstMIPS32Abs_s::Opcode = "abs.s"; member in Ice::MIPS32::InstMIPS32Abs_s
65 template <> const char *InstMIPS32Addi::Opcode = "addi"; member in Ice::MIPS32::InstMIPS32Addi
66 template <> const char *InstMIPS32Add::Opcode = "add"; member in Ice::MIPS32::InstMIPS32Add
67 template <> const char *InstMIPS32Add_d::Opcode = "add.d"; member in Ice::MIPS32::InstMIPS32Add_d
68 template <> const char *InstMIPS32Add_s::Opcode = "add.s"; member in Ice::MIPS32::InstMIPS32Add_s
69 template <> const char *InstMIPS32Addiu::Opcode = "addiu"; member in Ice::MIPS32::InstMIPS32Addiu
70 template <> const char *InstMIPS32Addu::Opcode = "addu"; member in Ice::MIPS32::InstMIPS32Addu
71 template <> const char *InstMIPS32And::Opcode = "and"; member in Ice::MIPS32::InstMIPS32And
72 template <> const char *InstMIPS32Andi::Opcode = "andi"; member in Ice::MIPS32::InstMIPS32Andi
[all …]
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| D | IceAssemblerMIPS32.cpp | 207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt()
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16()
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt, in emitRtRsImm16Rel()
255 void AssemblerMIPS32::emitFtRsImm16(IValueT Opcode, const Operand *OpFt, in emitFtRsImm16()
268 void AssemblerMIPS32::emitRdRtSa(IValueT Opcode, const Operand *OpRd, in emitRdRtSa()
281 void AssemblerMIPS32::emitRdRsRt(IValueT Opcode, const Operand *OpRd, in emitRdRsRt()
295 void AssemblerMIPS32::emitCOP1Fcmp(IValueT Opcode, FPInstDataFormat Format, in emitCOP1Fcmp()
309 void AssemblerMIPS32::emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFsFd()
322 void AssemblerMIPS32::emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtFtFsFd()
339 void AssemblerMIPS32::emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format, in emitCOP1FmtRtFsFd()
[all …]
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| D | IceInstARM32.cpp | 111 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode, in dumpOpcodePred()
162 void InstARM32Pred::emitUnaryopGPR(const char *Opcode, in emitUnaryopGPR()
177 void InstARM32Pred::emitUnaryopFP(const char *Opcode, FPSign Sign, in emitUnaryopFP()
200 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Instr, in emitTwoAddr()
214 void InstARM32Pred::emitThreeAddr(const char *Opcode, in emitThreeAddr()
230 void InstARM32::emitThreeAddrFP(const char *Opcode, FPSign SignType, in emitThreeAddrFP()
245 void InstARM32::emitFourAddrFP(const char *Opcode, FPSign SignType, in emitFourAddrFP()
261 void InstARM32Pred::emitFourAddr(const char *Opcode, const InstARM32Pred *Instr, in emitFourAddr()
313 void InstARM32Pred::emitCmpLike(const char *Opcode, const InstARM32Pred *Instr, in emitCmpLike()
1823 template <> const char *InstARM32Movt::Opcode = "movt"; member in Ice::ARM32::InstARM32Movt
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 187 bool isSALU(uint16_t Opcode) const { in isSALU()
195 bool isVALU(uint16_t Opcode) const { in isVALU()
203 bool isVMEM(uint16_t Opcode) const { in isVMEM()
211 bool isSOP1(uint16_t Opcode) const { in isSOP1()
219 bool isSOP2(uint16_t Opcode) const { in isSOP2()
227 bool isSOPC(uint16_t Opcode) const { in isSOPC()
235 bool isSOPK(uint16_t Opcode) const { in isSOPK()
243 bool isSOPP(uint16_t Opcode) const { in isSOPP()
251 bool isVOP1(uint16_t Opcode) const { in isVOP1()
259 bool isVOP2(uint16_t Opcode) const { in isVOP2()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 304 bool isSALU(uint16_t Opcode) const { in isSALU()
312 bool isVALU(uint16_t Opcode) const { in isVALU()
320 bool isVMEM(uint16_t Opcode) const { in isVMEM()
328 bool isSOP1(uint16_t Opcode) const { in isSOP1()
336 bool isSOP2(uint16_t Opcode) const { in isSOP2()
344 bool isSOPC(uint16_t Opcode) const { in isSOPC()
352 bool isSOPK(uint16_t Opcode) const { in isSOPK()
360 bool isSOPP(uint16_t Opcode) const { in isSOPP()
368 bool isVOP1(uint16_t Opcode) const { in isVOP1()
376 bool isVOP2(uint16_t Opcode) const { in isVOP2()
[all …]
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 59 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty) { in buildInstr()
72 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
77 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
88 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, in buildInstr()
95 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) { in buildInstr()
99 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, in buildInstr()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 141 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
155 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
165 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 144 static inline bool isSPLSOpcode(unsigned Opcode) { in isSPLSOpcode()
158 static inline bool isRMOpcode(unsigned Opcode) { in isRMOpcode()
168 static inline bool isRRMOpcode(unsigned Opcode) { in isRRMOpcode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/tools/llvm-exegesis/X86/ |
| D | SnippetGeneratorTest.cpp | 56 SnippetPrototype checkAndGetConfigurations(unsigned Opcode) { in checkAndGetConfigurations()
79 const unsigned Opcode = llvm::X86::ADC16i16; in TEST_F() local
100 const unsigned Opcode = llvm::X86::ADD16ri; in TEST_F() local
118 const unsigned Opcode = llvm::X86::CMP64rr; in TEST_F() local
132 const unsigned Opcode = llvm::X86::LAHF; in TEST_F() local
147 const unsigned Opcode = llvm::X86::BNDCL32rr; in TEST_F() local
164 const unsigned Opcode = llvm::X86::CDQ; in TEST_F() local
181 const unsigned Opcode = llvm::X86::CMOVA32rr; in TEST_F() local
204 const unsigned Opcode = llvm::X86::CMOV_GR32; in TEST_F() local
223 Instruction createInstruction(unsigned Opcode) { in createInstruction()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 74 void EmitInt8(unsigned Opcode) { in EmitInt8()
79 void EmitInt16(unsigned Opcode) { in EmitInt16()
85 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMUnwindOpAsm.h | 73 void EmitInt8(unsigned Opcode) { in EmitInt8()
78 void EmitInt16(unsigned Opcode) { in EmitInt16()
84 void EmitBytes(const uint8_t *Opcode, size_t Size) { in EmitBytes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCPredicates.cpp | 19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { in getSwappedPredicate()
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| /external/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 97 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
102 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
120 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
128 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
132 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
138 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
144 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
161 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
187 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 101 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
107 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
126 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
131 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
136 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn() local
141 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn() local
148 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn() local
155 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000() local
172 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128() local
199 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_101101nn() local
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 53 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
76 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
269 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
294 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
412 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
483 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
496 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZAsmPrinter.cpp | 31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh()
59 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) { in lowerRIEfLow()
85 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorLoad()
95 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { in lowerSubvectorStore()
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| D | SystemZShortenInst.cpp | 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 109 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) { in shortenOn0()
119 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) { in shortenOn01()
131 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) { in shortenOn001()
144 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) { in shortenOn001AddCC()
157 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) { in shortenFPConv()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 108 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
281 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
304 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
310 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { in getCmpSelInstrCost()
314 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { in getVectorInstrCost()
353 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
410 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 91 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, in getIntImmCodeSizeCost()
99 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
136 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, in getCastInstrCost()
330 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, in getVectorInstrCost()
355 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, in getCmpSelInstrCost()
457 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
528 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
541 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetOpcodes.h | 31 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode()
37 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 113 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, in getIntImmCost()
328 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, in getArithmeticInstrCost()
351 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, in getCastInstrCost()
358 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, in getCmpSelInstrCost()
363 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { in getVectorInstrCost()
402 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, in getMemoryOpCost()
472 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetTransformInfo.cpp | 153 unsigned HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
191 unsigned HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, in getMaskedMemoryOpCost()
201 unsigned HexagonTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy, in getGatherScatterOpCost()
207 unsigned HexagonTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, in getInterleavedMemoryOpCost()
214 unsigned HexagonTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
224 unsigned HexagonTTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, in getArithmeticInstrCost()
237 unsigned HexagonTTIImpl::getCastInstrCost(unsigned Opcode, Type *DstTy, in getCastInstrCost()
250 unsigned HexagonTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 64 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, in getIntImmCost()
179 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { in getCastInstrCost()
294 int AArch64TTIImpl::getExtractWithExtendCost(unsigned Opcode, Type *Dst, in getExtractWithExtendCost()
349 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, in getVectorInstrCost()
375 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, in getArithmeticInstrCost()
435 int AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, in getCmpSelInstrCost()
466 int AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost()
495 int AArch64TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, in getInterleavedMemoryOpCost()
|