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Searched defs:Orders (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp636 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, in ProcessSDDbgValues()
668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders, in ProcessSourceNode()
695 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp701 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSDDbgValues()
731 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSourceNode()
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp703 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSDDbgValues()
732 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSourceNode()
804 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.h91 std::vector<SmallVector<Record*, 16> > Orders; variable
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DFastISel.h572 DenseMap<MachineInstr *, unsigned> Orders; member
/external/llvm/lib/CodeGen/
DInlineSpiller.cpp1142 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders()
1233 SmallVector<MachineDomTreeNode *, 32> Orders; in runHoistSpills() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DInlineSpiller.cpp1198 SmallVectorImpl<MachineDomTreeNode *> &Orders, in getVisitOrders()
1289 SmallVector<MachineDomTreeNode *, 32> Orders; in runHoistSpills() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DConstantHoisting.cpp233 SmallVector<BasicBlock *, 16> Orders; in findBestInsertionSet() local
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.h295 std::vector<SmallVector<Record*, 16>> Orders; variable
/external/llvm/utils/TableGen/
DCodeGenRegisters.h269 std::vector<SmallVector<Record*, 16> > Orders; variable
/external/clang/lib/CodeGen/
DCGBuiltin.cpp1450 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1516 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local