1 /******************************************************************************** 2 Copyright (C) 2016 Marvell International Ltd. 3 4 Marvell BSD License Option 5 6 If you received this File from Marvell, you may opt to use, redistribute and/or 7 modify this File under the following licensing terms. 8 Redistribution and use in source and binary forms, with or without modification, 9 are permitted provided that the following conditions are met: 10 11 * Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 * Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 * Neither the name of Marvell nor the names of its contributors may be 19 used to endorse or promote products derived from this software without 20 specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 23 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 26 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 33 *******************************************************************************/ 34 35 #ifndef __COMPHY_H__ 36 #define __COMPHY_H__ 37 38 #include <Library/ArmLib.h> 39 #include <Library/ArmPlatformLib.h> 40 #include <Library/DebugLib.h> 41 #include <Library/PcdLib.h> 42 #include <Library/MemoryAllocationLib.h> 43 #include <Library/IoLib.h> 44 #include <Library/TimerLib.h> 45 #include <Library/ParsePcdLib.h> 46 47 #define MAX_LANE_OPTIONS 10 48 #define MAX_CHIPS 4 49 50 /***** Parsing PCD *****/ 51 #define GET_TYPE_STRING(id) PcdGetPtr(PcdChip##id##Compatible) 52 #define GET_LANE_TYPE(id) PcdGetPtr(PcdChip##id##ComPhyTypes) 53 #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) 54 #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) 55 #define GET_COMPHY_BASE_ADDR(id) PcdGet64(PcdChip##id##ComPhyBaseAddress) 56 #define GET_HPIPE3_BASE_ADDR(id) PcdGet64(PcdChip##id##Hpipe3BaseAddress) 57 #define GET_MUX_BIT_COUNT(id) PcdGet32(PcdChip##id##ComPhyMuxBitCount) 58 #define GET_MAX_LANES(id) PcdGet32(PcdChip##id##ComPhyMaxLanes) 59 60 #define FillLaneMap(chip_struct, lane_struct, id) { \ 61 ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount, NULL, lane_struct[id].TypeStr); \ 62 ParsePcdString((CHAR16 *) GET_LANE_SPEED(id), chip_struct[id].LanesCount, lane_struct[id].SpeedValue, NULL); \ 63 ParsePcdString((CHAR16 *) GET_LANE_INV(id), chip_struct[id].LanesCount, lane_struct[id].InvFlag, NULL); \ 64 } 65 66 #define GetComPhyPcd(chip_struct, lane_struct, id) { \ 67 chip_struct[id].ChipType = (CHAR16 *) GET_TYPE_STRING(id); \ 68 chip_struct[id].ComPhyBaseAddr = GET_COMPHY_BASE_ADDR(id); \ 69 chip_struct[id].Hpipe3BaseAddr = GET_HPIPE3_BASE_ADDR(id); \ 70 chip_struct[id].MuxBitCount = GET_MUX_BIT_COUNT(id); \ 71 chip_struct[id].LanesCount = GET_MAX_LANES(id); \ 72 FillLaneMap(chip_struct, lane_struct, id); \ 73 } 74 75 /***** ComPhy *****/ 76 #define PHY_SPEED_ERROR 0 77 #define PHY_SPEED_1_25G 1 78 #define PHY_SPEED_1_5G 2 79 #define PHY_SPEED_2_5G 3 80 #define PHY_SPEED_3G 4 81 #define PHY_SPEED_3_125G 5 82 #define PHY_SPEED_5G 6 83 #define PHY_SPEED_6G 7 84 #define PHY_SPEED_6_25G 8 85 #define PHY_SPEED_10_3125G 9 86 #define PHY_SPEED_MAX 10 87 #define PHY_SPEED_INVALID 0xff 88 89 #define PHY_TYPE_UNCONNECTED 0 90 #define PHY_TYPE_PCIE0 1 91 #define PHY_TYPE_PCIE1 2 92 #define PHY_TYPE_PCIE2 3 93 #define PHY_TYPE_PCIE3 4 94 #define PHY_TYPE_SATA0 5 95 #define PHY_TYPE_SATA1 6 96 #define PHY_TYPE_SATA2 7 97 #define PHY_TYPE_SATA3 8 98 #define PHY_TYPE_SGMII0 9 99 #define PHY_TYPE_SGMII1 10 100 #define PHY_TYPE_SGMII2 11 101 #define PHY_TYPE_SGMII3 12 102 #define PHY_TYPE_QSGMII 13 103 #define PHY_TYPE_USB3_HOST0 14 104 #define PHY_TYPE_USB3_HOST1 15 105 #define PHY_TYPE_USB3_DEVICE 16 106 #define PHY_TYPE_XAUI0 17 107 #define PHY_TYPE_XAUI1 18 108 #define PHY_TYPE_XAUI2 19 109 #define PHY_TYPE_XAUI3 20 110 #define PHY_TYPE_RXAUI0 21 111 #define PHY_TYPE_RXAUI1 22 112 #define PHY_TYPE_KR 23 113 #define PHY_TYPE_MAX 24 114 #define PHY_TYPE_INVALID 0xff 115 116 #define PHY_POLARITY_NO_INVERT 0 117 #define PHY_POLARITY_TXD_INVERT 1 118 #define PHY_POLARITY_RXD_INVERT 2 119 #define PHY_POLARITY_ALL_INVERT (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) 120 121 /***** SerDes IP registers *****/ 122 #define SD_EXTERNAL_CONFIG0_REG 0 123 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 124 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) 125 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 126 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) 127 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 128 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) 129 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 130 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) 131 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 132 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) 133 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 134 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) 135 136 #define SD_EXTERNAL_CONFIG1_REG 0x4 137 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 138 #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) 139 #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 140 #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) 141 #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 142 #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) 143 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 144 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) 145 146 147 #define SD_EXTERNAL_STATUS0_REG 0x18 148 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 149 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) 150 #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 151 #define SD_EXTERNAL_STATUS0_PLL_RX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) 152 #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 153 #define SD_EXTERNAL_STATUS0_RX_INIT_MASK (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) 154 155 /***** HPIPE registers *****/ 156 #define HPIPE_PWR_PLL_REG 0x4 157 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 158 #define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) 159 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 160 #define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) 161 162 #define HPIPE_KVCO_CALIB_CTRL_REG 0x8 163 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12 164 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET) 165 166 #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 167 168 #define HPIPE_DFE_REG0 0x01C 169 #define HPIPE_DFE_RES_FORCE_OFFSET 15 170 #define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) 171 172 173 #define HPIPE_DFE_F3_F5_REG 0x028 174 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 175 #define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) 176 #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 177 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) 178 179 #define HPIPE_G1_SET_0_REG 0x034 180 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 181 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) 182 183 #define HPIPE_G1_SET_1_REG 0x038 184 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 185 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) 186 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 187 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) 188 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 189 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) 190 191 #define HPIPE_G2_SETTINGS_1_REG 0x040 192 193 #define HPIPE_LOOPBACK_REG 0x08c 194 #define HPIPE_LOOPBACK_SEL_OFFSET 1 195 #define HPIPE_LOOPBACK_SEL_MASK (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) 196 197 #define HPIPE_SYNC_PATTERN_REG 0x090 198 199 #define HPIPE_INTERFACE_REG 0x94 200 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 201 #define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) 202 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 203 #define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) 204 205 #define HPIPE_ISOLATE_MODE_REG 0x98 206 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0 207 #define HPIPE_ISOLATE_MODE_GEN_RX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET) 208 #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4 209 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET) 210 211 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104 212 213 #define HPIPE_PCIE_REG0 0x120 214 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 215 #define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) 216 #define HPIPE_PCIE_SEL_BITS_OFFSET 13 217 #define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) 218 219 #define HPIPE_LANE_ALIGN_REG 0x124 220 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 221 #define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) 222 223 #define HPIPE_MISC_REG 0x13C 224 #define HPIPE_MISC_CLK100M_125M_OFFSET 4 225 #define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) 226 #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 227 #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) 228 #define HPIPE_MISC_CLK500_EN_OFFSET 7 229 #define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) 230 #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 231 #define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) 232 233 #define HPIPE_RX_CONTROL_1_REG 0x140 234 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 235 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) 236 #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 237 #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) 238 239 #define HPIPE_PWR_CTR_REG 0x148 240 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 241 #define HPIPE_PWR_CTR_RST_DFE_MASK (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) 242 #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 243 #define HPIPE_PWR_CTR_SFT_RST_MASK (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) 244 245 #define HPIPE_PLLINTP_REG1 0x150 246 247 #define HPIPE_PWR_CTR_DTL_REG 0x184 248 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 0x2 249 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) 250 251 #define HPIPE_RX_REG3 0x188 252 253 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C 254 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 255 #define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) 256 #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 257 #define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) 258 #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 259 #define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) 260 261 #define HPIPE_PCIE_REG1 0x288 262 #define HPIPE_PCIE_REG3 0x290 263 264 #define HPIPE_TX_TRAIN_REG 0x31C 265 #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 266 #define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) 267 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 268 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) 269 270 #define HPIPE_G1_SETTINGS_3_REG 0x440 271 #define HPIPE_G1_SETTINGS_4_REG 0x444 272 #define HPIPE_G2_SETTINGS_3_REG 0x448 273 #define HPIPE_G2_SETTINGS_4_REG 0x44C 274 275 #define HPIPE_DFE_CTRL_28_REG 0x49C 276 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 277 #define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) 278 279 #define HPIPE_LANE_CONFIG0_REG 0x604 280 #define HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET 9 281 #define HPIPE_LANE_CONFIG0_MAX_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_MAX_PLL_OFFSET) 282 #define HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET 10 283 #define HPIPE_LANE_CONFIG0_GEN2_PLL_MASK (0x1 << HPIPE_LANE_CONFIG0_GEN2_PLL_OFFSET) 284 285 #define HPIPE_LANE_STATUS0_REG 0x60C 286 #define HPIPE_LANE_STATUS0_PCLK_EN_OFFSET 0 287 #define HPIPE_LANE_STATUS0_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS0_PCLK_EN_OFFSET) 288 289 #define HPIPE_LANE_CFG4_REG 0x620 290 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 291 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) 292 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 293 #define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) 294 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 295 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) 296 297 #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 298 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 299 #define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) 300 301 #define HPIPE_RST_CLK_CTRL_REG 0x704 302 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 303 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) 304 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 305 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) 306 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 307 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) 308 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 309 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) 310 311 #define HPIPE_CLK_SRC_LO_REG 0x70c 312 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 313 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) 314 315 #define HPIPE_CLK_SRC_HI_REG 0x710 316 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 317 #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) 318 #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 319 #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) 320 #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 321 #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) 322 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 323 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) 324 325 #define HPIPE_GLOBAL_MISC_CTRL 0x718 326 #define HPIPE_GLOBAL_PM_CTRL 0x740 327 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 328 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) 329 330 /***** COMPHY registers *****/ 331 #define COMMON_PHY_CFG1_REG 0x0 332 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 333 #define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) 334 #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 335 #define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) 336 #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 337 #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) 338 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 339 #define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) 340 #define COMMON_PHY_PHY_MODE_OFFSET 15 341 #define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) 342 343 #define COMMON_PHY_CFG6_REG 0x14 344 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 345 #define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) 346 347 #define COMMON_SELECTOR_PHY_OFFSET 0x140 348 #define COMMON_SELECTOR_PIPE_OFFSET 0x144 349 350 /***** SATA registers *****/ 351 #define SATA3_VENDOR_ADDRESS 0xA0 352 #define SATA3_VENDOR_ADDR_OFSSET 0 353 #define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) 354 #define SATA3_VENDOR_DATA 0xA4 355 356 #define SATA_CONTROL_REG 0x0 357 #define SATA3_CTRL_SATA0_PD_OFFSET 6 358 #define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) 359 #define SATA3_CTRL_SATA1_PD_OFFSET 14 360 #define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) 361 #define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 362 #define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) 363 #define SATA3_CTRL_SATA_SSU_OFFSET 23 364 #define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) 365 366 #define SATA_MBUS_SIZE_SELECT_REG 0x4 367 #define SATA_MBUS_REGRET_EN_OFFSET 7 368 #define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) 369 370 /***************************/ 371 372 typedef struct _CHIP_COMPHY_CONFIG CHIP_COMPHY_CONFIG; 373 374 typedef struct { 375 UINT32 Type; 376 UINT32 MuxValue; 377 } COMPHY_MUX_OPTIONS; 378 379 typedef struct { 380 UINT32 MaxLaneValues; 381 COMPHY_MUX_OPTIONS MuxValues[MAX_LANE_OPTIONS]; 382 } COMPHY_MUX_DATA; 383 384 typedef struct { 385 UINT32 Type; 386 UINT32 Speed; 387 UINT32 Invert; 388 } COMPHY_MAP; 389 390 typedef struct { 391 CHAR16 *TypeStr[MAX_LANE_OPTIONS]; 392 UINTN SpeedValue[MAX_LANE_OPTIONS]; 393 UINTN InvFlag[MAX_LANE_OPTIONS]; 394 } PCD_LANE_MAP; 395 396 typedef 397 EFI_STATUS 398 (*COMPHY_CHIP_INIT) ( 399 IN CHIP_COMPHY_CONFIG *PtrChipCfg 400 ); 401 402 struct _CHIP_COMPHY_CONFIG { 403 CHAR16* ChipType; 404 COMPHY_MAP MapData[MAX_LANE_OPTIONS]; 405 COMPHY_MUX_DATA *MuxData; 406 EFI_PHYSICAL_ADDRESS ComPhyBaseAddr; 407 EFI_PHYSICAL_ADDRESS Hpipe3BaseAddr; 408 COMPHY_CHIP_INIT Init; 409 UINT32 LanesCount; 410 UINT32 MuxBitCount; 411 }; 412 413 VOID 414 ComPhyMuxInit ( 415 IN CHIP_COMPHY_CONFIG *PtrChipCfg, 416 IN COMPHY_MAP *ComPhyMapData, 417 IN EFI_PHYSICAL_ADDRESS SelectorBase 418 ); 419 420 EFI_STATUS 421 ComPhyCp110Init ( 422 IN CHIP_COMPHY_CONFIG * First 423 ); 424 425 VOID 426 RegSet ( 427 IN EFI_PHYSICAL_ADDRESS Addr, 428 IN UINT32 Data, 429 IN UINT32 Mask 430 ); 431 432 VOID 433 RegSetSilent ( 434 IN EFI_PHYSICAL_ADDRESS Addr, 435 IN UINT32 Data, 436 IN UINT32 Mask 437 ); 438 439 VOID 440 RegSet16 ( 441 IN EFI_PHYSICAL_ADDRESS Addr, 442 IN UINT16 Data, 443 IN UINT16 Mask 444 ); 445 446 VOID 447 RegSetSilent16( 448 IN EFI_PHYSICAL_ADDRESS Addr, 449 IN UINT16 Data, 450 IN UINT16 Mask 451 ); 452 #endif // __COMPHY_H__ 453