1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_DEF_H 7 #define _DDR3_TRAINING_IP_DEF_H 8 9 #define PATTERN_55 0x55555555 10 #define PATTERN_AA 0xaaaaaaaa 11 #define PATTERN_80 0x80808080 12 #define PATTERN_20 0x20202020 13 #define PATTERN_01 0x01010101 14 #define PATTERN_FF 0xffffffff 15 #define PATTERN_00 0x00000000 16 17 /* 16bit bus width patterns */ 18 #define PATTERN_55AA 0x5555aaaa 19 #define PATTERN_00FF 0x0000ffff 20 #define PATTERN_0080 0x00008080 21 22 #define INVALID_VALUE 0xffffffff 23 #define MAX_NUM_OF_DUNITS 32 24 /* 25 * length *2 = length in words of pattern, first low address, 26 * second high address 27 */ 28 #define TEST_PATTERN_LENGTH 4 29 #define KILLER_PATTERN_DQ_NUMBER 8 30 #define SSO_DQ_NUMBER 4 31 #define PATTERN_MAXIMUM_LENGTH 64 32 #define ADLL_TX_LENGTH 64 33 #define ADLL_RX_LENGTH 32 34 35 #define PARAM_NOT_CARE 0 36 #define PARAM_UNDEFINED 0xffffffff 37 38 #define READ_LEVELING_PHY_OFFSET 2 39 #define WRITE_LEVELING_PHY_OFFSET 0 40 41 #define MASK_ALL_BITS 0xffffffff 42 43 #define CS_BIT_MASK 0xf 44 45 /* DFX access */ 46 #define BROADCAST_ID 28 47 #define MULTICAST_ID 29 48 49 #define XSB_BASE_ADDR 0x00004000 50 #define XSB_CTRL_0_REG 0x00000000 51 #define XSB_CTRL_1_REG 0x00000004 52 #define XSB_CMD_REG 0x00000008 53 #define XSB_ADDRESS_REG 0x0000000c 54 #define XSB_DATA_REG 0x00000010 55 #define PIPE_ENABLE_ADDR 0x000f8000 56 #define ENABLE_DDR_TUNING_ADDR 0x000f829c 57 58 #define CLIENT_BASE_ADDR 0x00002000 59 #define CLIENT_CTRL_REG 0x00000000 60 61 #define TARGET_INT 0x1801 62 #define TARGET_EXT 0x180e 63 #define BYTE_EN 0 64 #define CMD_READ 0 65 #define CMD_WRITE 1 66 67 #define INTERNAL_ACCESS_PORT 1 68 #define EXECUTING 1 69 #define ACCESS_EXT 1 70 #define CS2_EXIST_BIT 2 71 #define TRAINING_ID 0xf 72 #define EXT_TRAINING_ID 1 73 #define EXT_MODE 0x4 74 75 #define GET_RESULT_STATE(res) (res) 76 #define SET_RESULT_STATE(res, state) (res = state) 77 78 #define _1K 0x00000400 79 #define _4K 0x00001000 80 #define _8K 0x00002000 81 #define _16K 0x00004000 82 #define _32K 0x00008000 83 #define _64K 0x00010000 84 #define _128K 0x00020000 85 #define _256K 0x00040000 86 #define _512K 0x00080000 87 88 #define _1M 0x00100000 89 #define _2M 0x00200000 90 #define _4M 0x00400000 91 #define _8M 0x00800000 92 #define _16M 0x01000000 93 #define _32M 0x02000000 94 #define _64M 0x04000000 95 #define _128M 0x08000000 96 #define _256M 0x10000000 97 #define _512M 0x20000000 98 99 #define _1G 0x40000000 100 #define _2G 0x80000000 101 #define _4G 0x100000000 102 #define _8G 0x200000000 103 104 #define ADDR_SIZE_512MB 0x04000000 105 #define ADDR_SIZE_1GB 0x08000000 106 #define ADDR_SIZE_2GB 0x10000000 107 #define ADDR_SIZE_4GB 0x20000000 108 #define ADDR_SIZE_8GB 0x40000000 109 110 enum hws_edge_compare { 111 EDGE_PF, 112 EDGE_FP, 113 EDGE_FPF, 114 EDGE_PFP 115 }; 116 117 enum hws_control_element { 118 HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */ 119 HWS_CONTROL_ELEMENT_DQ_SKEW, 120 HWS_CONTROL_ELEMENT_DQS_SKEW 121 }; 122 123 enum hws_search_dir { 124 HWS_LOW2HIGH, 125 HWS_HIGH2LOW, 126 HWS_SEARCH_DIR_LIMIT 127 }; 128 129 enum hws_page_size { 130 PAGE_SIZE_1K, 131 PAGE_SIZE_2K 132 }; 133 134 enum hws_operation { 135 OPERATION_READ = 0, 136 OPERATION_WRITE = 1 137 }; 138 139 enum hws_training_ip_stat { 140 HWS_TRAINING_IP_STATUS_FAIL, 141 HWS_TRAINING_IP_STATUS_SUCCESS, 142 HWS_TRAINING_IP_STATUS_TIMEOUT 143 }; 144 145 enum hws_ddr_cs { 146 CS_SINGLE, 147 CS_NON_SINGLE 148 }; 149 150 enum hws_ddr_phy { 151 DDR_PHY_DATA = 0, 152 DDR_PHY_CONTROL = 1 153 }; 154 155 enum hws_dir { 156 OPER_WRITE, 157 OPER_READ, 158 OPER_WRITE_AND_READ 159 }; 160 161 enum hws_wl_supp { 162 PHASE_SHIFT, 163 CLOCK_SHIFT, 164 ALIGN_SHIFT 165 }; 166 167 enum mv_ddr_tip_bit_state { 168 BIT_LOW_UI, 169 BIT_HIGH_UI, 170 BIT_SPLIT_IN, 171 BIT_SPLIT_OUT, 172 BIT_STATE_LAST 173 }; 174 175 enum mv_ddr_tip_byte_state{ 176 BYTE_NOT_DEFINED, 177 BYTE_HOMOGENEOUS_LOW = 0x1, 178 BYTE_HOMOGENEOUS_HIGH = 0x2, 179 BYTE_HOMOGENEOUS_SPLIT_IN = 0x4, 180 BYTE_HOMOGENEOUS_SPLIT_OUT = 0x8, 181 BYTE_SPLIT_OUT_MIX = 0x10, 182 BYTE_STATE_LAST 183 }; 184 185 struct reg_data { 186 unsigned int reg_addr; 187 unsigned int reg_data; 188 unsigned int reg_mask; 189 }; 190 191 enum dm_direction { 192 DM_DIR_INVERSE, 193 DM_DIR_DIRECT 194 }; 195 196 #endif /* _DDR3_TRAINING_IP_DEF_H */ 197