1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PMC_H__ 8 #define __PMC_H__ 9 10 #include <mmio.h> 11 #include <tegra_def.h> 12 #include <utils_def.h> 13 14 #define PMC_CONFIG U(0x0) 15 #define PMC_PWRGATE_STATUS U(0x38) 16 #define PMC_PWRGATE_TOGGLE U(0x30) 17 #define PMC_TOGGLE_START U(0x100) 18 #define PMC_SCRATCH39 U(0x138) 19 #define PMC_SECURE_DISABLE2 U(0x2c4) 20 #define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) 21 #define PMC_SECURE_SCRATCH22 U(0x338) 22 #define PMC_SECURE_DISABLE3 U(0x2d8) 23 #define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) 24 #define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) 25 #define PMC_SECURE_SCRATCH34 U(0x368) 26 #define PMC_SECURE_SCRATCH35 U(0x36c) 27 tegra_pmc_read_32(uint32_t off)28static inline uint32_t tegra_pmc_read_32(uint32_t off) 29 { 30 return mmio_read_32(TEGRA_PMC_BASE + off); 31 } 32 tegra_pmc_write_32(uint32_t off,uint32_t val)33static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) 34 { 35 mmio_write_32(TEGRA_PMC_BASE + off, val); 36 } 37 38 void tegra_pmc_cpu_setup(uint64_t reset_addr); 39 void tegra_pmc_lock_cpu_vectors(void); 40 void tegra_pmc_cpu_on(int32_t cpu); 41 __dead2 void tegra_pmc_system_reset(void); 42 43 #endif /* __PMC_H__ */ 44