| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 132 unsigned PredR = 0; member
254 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
711 unsigned PredR, bool IfTrue) { in predicateInstr()
764 unsigned PredR, bool IfTrue) { in predicateBlockNB()
781 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux()
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| D | HexagonGenMux.cpp | 93 unsigned PredR = 0; member
109 unsigned DefR, PredR; member
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| D | HexagonExpandCondsets.cpp | 746 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred()
916 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange()
965 unsigned PredR = MP.getReg(); in predicate() local
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| D | HexagonHardwareLoops.cpp | 462 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
1338 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1917 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
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| D | HexagonISelLowering.cpp | 287 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 113 unsigned PredR; member
227 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
708 unsigned PredR, bool IfTrue) { in predicateInstr()
757 unsigned PredR, bool IfTrue) { in predicateBlockNB()
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| D | HexagonGenMux.cpp | 62 unsigned PredR; member
73 unsigned DefR, PredR; member
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| D | HexagonExpandCondsets.cpp | 743 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred()
917 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange()
967 unsigned PredR = MP.getReg(); in predicate() local
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| D | HexagonHardwareLoops.cpp | 443 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
1298 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1877 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
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| D | HexagonBitSimplify.cpp | 2692 unsigned PredR = 0; in processLoop() local
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| D | HexagonISelLowering.cpp | 636 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 318 ICmpInst::Predicate &PredR) { in getMaskedTypeForICmpPair()
447 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
577 ICmpInst::Predicate PredL, ICmpInst::Predicate PredR, in foldLogOpOfMaskedICmpsAsymmetric()
612 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in foldLogOpOfMaskedICmps() local
909 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in foldAndOfICmps() local
1089 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in foldLogicOfFCmps() local
1780 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in foldOrOfICmps() local
2359 ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in foldXorOfICmps() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 1703 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
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