1 /*
2 * Copyright © 2009 Corbin Simpson
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 #ifndef RADEON_DRM_WINSYS_H
28 #define RADEON_DRM_WINSYS_H
29
30 #include "gallium/drivers/radeon/radeon_winsys.h"
31 #include "pipebuffer/pb_cache.h"
32 #include "pipebuffer/pb_slab.h"
33 #include "util/u_queue.h"
34 #include "util/list.h"
35 #include <radeon_drm.h>
36
37 struct radeon_drm_cs;
38
39 enum radeon_generation {
40 DRV_R300,
41 DRV_R600,
42 DRV_SI
43 };
44
45 #define RADEON_SLAB_MIN_SIZE_LOG2 9
46 #define RADEON_SLAB_MAX_SIZE_LOG2 14
47
48 struct radeon_drm_winsys {
49 struct radeon_winsys base;
50 struct pipe_reference reference;
51 struct pb_cache bo_cache;
52 struct pb_slabs bo_slabs;
53
54 int fd; /* DRM file descriptor */
55 int num_cs; /* The number of command streams created. */
56 uint64_t allocated_vram;
57 uint64_t allocated_gtt;
58 uint64_t mapped_vram;
59 uint64_t mapped_gtt;
60 uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
61 uint64_t num_gfx_IBs;
62 uint64_t num_sdma_IBs;
63 uint64_t num_mapped_buffers;
64 uint32_t next_bo_hash;
65
66 enum radeon_generation gen;
67 struct radeon_info info;
68 uint32_t va_start;
69 uint32_t va_unmap_working;
70 uint32_t accel_working2;
71
72 /* List of buffer GEM names. Protected by bo_handles_mutex. */
73 struct util_hash_table *bo_names;
74 /* List of buffer handles. Protectded by bo_handles_mutex. */
75 struct util_hash_table *bo_handles;
76 /* List of buffer virtual memory ranges. Protectded by bo_handles_mutex. */
77 struct util_hash_table *bo_vas;
78 mtx_t bo_handles_mutex;
79 mtx_t bo_va_mutex;
80 mtx_t bo_fence_lock;
81
82 uint64_t va_offset;
83 struct list_head va_holes;
84 bool check_vm;
85
86 struct radeon_surface_manager *surf_man;
87
88 uint32_t num_cpus; /* Number of CPUs. */
89
90 struct radeon_drm_cs *hyperz_owner;
91 mtx_t hyperz_owner_mutex;
92 struct radeon_drm_cs *cmask_owner;
93 mtx_t cmask_owner_mutex;
94
95 /* multithreaded command submission */
96 struct util_queue cs_queue;
97 };
98
99 static inline struct radeon_drm_winsys *
radeon_drm_winsys(struct radeon_winsys * base)100 radeon_drm_winsys(struct radeon_winsys *base)
101 {
102 return (struct radeon_drm_winsys*)base;
103 }
104
105 void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
106
107 #endif
108