| /external/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 41 ROR, ///< Bit rotate right. enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.h | 42 ROR, ///< Bit rotate right. enumerator
|
| /external/python/cpython3/Modules/ |
| D | sha256module.c | 112 #define ROR(x, y)\ macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 398 ROR, enumerator
|
| /external/python/cpython2/Modules/ |
| D | sha256module.c | 113 #define ROR(x, y)\ macro
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 357 ROR, enumerator
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 37 ROR, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 37 ROR, enumerator
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 240 ROR = 3 << 5, // Rotate right. enumerator
|
| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 1051 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enumerator
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 962 ### ROR ### subsection
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 369 ROR = 0x3, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2773 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); in visitOR() local
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 285 ROR = 0x3, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3835 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1)) in visitOR() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5127 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1)) in visitOR() local
|