1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DW_UFS_H__ 8 #define __DW_UFS_H__ 9 10 #include <sys/types.h> 11 12 /* Bus Throtting */ 13 #define BUSTHRTL 0xC0 14 /* Outstanding OCP Requests */ 15 #define OOCPR 0xC4 16 /* Fatal Error Interrupt Enable */ 17 #define FEIE 0xC8 18 /* C-Port Direct Access Configuration register */ 19 #define CDACFG 0xD0 20 /* C-Port Direct Access Transmit 1 register */ 21 #define CDATX1 0xD4 22 /* C-Port Direct Access Transmit 2 register */ 23 #define CDATX2 0xD8 24 /* C-Port Direct Access Receive 1 register */ 25 #define CDARX1 0xDC 26 /* C-Port Direct Access Receive 2 register */ 27 #define CDARX2 0xE0 28 /* C-Port Direct Access Status register */ 29 #define CDASTA 0xE4 30 /* UPIU Loopback Configuration register */ 31 #define LBMCFG 0xF0 32 /* UPIU Loopback Status */ 33 #define LBMSTA 0xF4 34 /* Debug register */ 35 #define DBG 0xF8 36 /* HClk Divider register */ 37 #define HCLKDIV 0xFC 38 39 #define TX_HIBERN8TIME_CAP_OFFSET 0x000F 40 #define TX_FSM_STATE_OFFSET 0x0041 41 #define TX_FSM_STATE_LINE_RESET 7 42 #define TX_FSM_STATE_LINE_CFG 6 43 #define TX_FSM_STATE_HS_BURST 5 44 #define TX_FSM_STATE_LS_BURST 4 45 #define TX_FSM_STATE_STALL 3 46 #define TX_FSM_STATE_SLEEP 2 47 #define TX_FSM_STATE_HIBERN8 1 48 #define TX_FSM_STATE_DISABLE 0 49 50 #define RX_MIN_ACTIVATETIME_CAP_OFFSET 0x008F 51 #define RX_HS_G2_SYNC_LENGTH_CAP_OFFSET 0x0094 52 #define RX_HS_G3_SYNC_LENGTH_CAP_OFFSET 0x0095 53 54 #define PA_AVAIL_TX_DATA_LANES_OFFSET 0x1520 55 #define PA_TX_SKIP_OFFSET 0x155C 56 #define PA_TX_SKIP_PERIOD_OFFSET 0x155D 57 #define PA_LOCAL_TX_LCC_ENABLE_OFFSET 0x155E 58 #define PA_ACTIVE_TX_DATA_LANES_OFFSET 0x1560 59 #define PA_CONNECTED_TX_DATA_LANES_OFFSET 0x1561 60 #define PA_TX_TRAILING_CLOCKS_OFFSET 0x1564 61 #define PA_TX_GEAR_OFFSET 0x1568 62 #define PA_TX_TERMINATION_OFFSET 0x1569 63 #define PA_HS_SERIES_OFFSET 0x156A 64 #define PA_PWR_MODE_OFFSET 0x1571 65 #define PA_ACTIVE_RX_DATA_LANES_OFFSET 0x1580 66 #define PA_CONNECTED_RX_DATA_LANES_OFFSET 0x1581 67 #define PA_RX_PWR_STATUS_OFFSET 0x1582 68 #define PA_RX_GEAR_OFFSET 0x1583 69 #define PA_RX_TERMINATION_OFFSET 0x1584 70 #define PA_SCRAMBLING_OFFSET 0x1585 71 #define PA_MAX_RX_PWM_GEAR_OFFSET 0x1586 72 #define PA_MAX_RX_HS_GEAR_OFFSET 0x1587 73 #define PA_PACP_REQ_TIMEOUT_OFFSET 0x1590 74 #define PA_PACP_REQ_EOB_TIMEOUT_OFFSET 0x1591 75 #define PA_REMOTE_VER_INFO_OFFSET 0x15A0 76 #define PA_LOGICAL_LANE_MAP_OFFSET 0x15A1 77 #define PA_TACTIVATE_OFFSET 0x15A8 78 #define PA_PWR_MODE_USER_DATA0_OFFSET 0x15B0 79 #define PA_PWR_MODE_USER_DATA1_OFFSET 0x15B1 80 #define PA_PWR_MODE_USER_DATA2_OFFSET 0x15B2 81 #define PA_PWR_MODE_USER_DATA3_OFFSET 0x15B3 82 #define PA_PWR_MODE_USER_DATA4_OFFSET 0x15B4 83 #define PA_PWR_MODE_USER_DATA5_OFFSET 0x15B5 84 85 #define DL_TC0_TX_FC_THRESHOLD_OFFSET 0x2040 86 #define DL_AFC0_CREDIT_THRESHOLD_OFFSET 0x2044 87 #define DL_TC0_OUT_ACK_THRESHOLD_OFFSET 0x2045 88 89 #define DME_FC0_PROTECTION_TIMEOUT_OFFSET 0xD041 90 #define DME_TC0_REPLAY_TIMEOUT_OFFSET 0xD042 91 #define DME_AFC0_REQ_TIMEOUT_OFFSET 0xD043 92 #define DME_FC1_PROTECTION_TIMEOUT_OFFSET 0xD044 93 #define DME_TC1_REPLAY_TIMEOUT_OFFSET 0xD045 94 #define DME_AFC1_REQ_TIMEOUT_OFFSET 0xD046 95 96 #define VS_MPHY_CFG_UPDT_OFFSET 0xD085 97 #define VS_MK2_EXTN_SUPPORT_OFFSET 0xD0AB 98 #define VS_MPHY_DISABLE_OFFSET 0xD0C1 99 #define VS_MPHY_DISABLE_MPHYDIS (1 << 0) 100 101 typedef struct dw_ufs_params { 102 uintptr_t reg_base; 103 uintptr_t desc_base; 104 size_t desc_size; 105 unsigned long flags; 106 } dw_ufs_params_t; 107 108 int dw_ufs_init(dw_ufs_params_t *params); 109 110 #endif /* __DW_UFS_H__ */ 111